CPCI-6115 CompactPCI Single Board Computer Installation and Use 6806800A68D March 2008
© Copyright 2008, 2007, 2006 Motorola, Inc. All rights reserved. Printed in the United States of America. Trademarks Motorola® and the Motorola symbol are registered trademarks of Motorola, Inc. CompactPCI® is a registered trademark of PCI Industrial Computer Manufacturers Group. All other product or service names mentioned in this document are trademarks or registered trademarks of their respective holders.
Contents About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Safety Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1 Introduction . . . . . . . . . . . . .
Contents 3 Controls, LEDs, and Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.1 3.2 3.3 3.4 3.5 4 49 50 50 52 52 52 53 53 54 54 55 56 57 59 63 63 64 64 65 65 65 66 66 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.1 4.2 4.3 2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 4.4 5 4.3.4.13 PCI Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4.14 Board Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4.15 MV64360 MPP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4.16 MV64360 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 System Memory . . . . . . . . . .
Contents 5.6 Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 CompactFlash Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 COM1 and COM2 Asynchronous Serial Ports Jumpers . . . . . . . . . . . . . . . . . . . . . . . 5.7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.
Contents 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 A Default Processor Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default PCI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suggested PCI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 6 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
List of Tables Table 1-1 Table 1-2 Table 1-3 Table 1-4 Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 3-15 Table 3-16 Table 3-17 Table 3-18 Table 3-19 Table 3-20 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 5-1 Table 5-2 Table 5-3 Table 5-4 CPCI-6115 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 7-1 Table 8-1 Table 8-2 Table 8-3 Table 8-4 Table 8-5 Table 8-6 Table A-1 Table A-2 Table A-3 8 PMC I/O Module 2 - Host I/O Connector Pin Assignments, J20 . . . . . . . . . . . . . . . . . 95 PMC I/O Modules 1 and 2 - PMC I/O Connector Pin Assignments, J14/24 . . . . . . . . . 96 User I/O Connector Pinout, J3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figures Figure 2-1 Figure 2-2 Figure 2-3 Figure 2-4 Figure 2-5 Figure 2-6 Figure 2-7 Figure 2-8 Figure 2-9 Figure 2-10 Figure 2-11 Figure 3-1 Figure 3-2 Figure 4-1 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 Figure 5-9 Figure 5-10 CPCI-6115 Thermally Significant Components (Primary Side) . . . . . . . . . . . . . . . . . . 34 CPCI-6115 Thermally Significant Components (Secondary Side) . . . . . . . . . . . . . . . . 35 Switch and Jumper Locations . . . .
List of Figures 10 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
About this Manual Overview of Contents This manual, CPCI-6115 CompactPCI Single Board Computer Installation and Use, provides general information, hardware preparation and installation instructions, operating instructions, firmware information, functional descriptions and pin assignments for the CPCI-6115 Single Board Computer (SBC).
About this Manual Appendix A, Related Documentation, provides a list of related documents including those produced by Motorola, as well as third parties. It also provides a list of industry related specifications.
About this Manual Abbreviation Description IEEE Institute of Electrical and Electronics Engineers, Inc.
About this Manual Abbreviation Description SDMA Space-Division Multiple Access SDRAM Synchronous Dynamic Random Access Memory SELV Safety Extra Low Voltage SPD Serial Presence Detect SRAM Static Random Access Memory SROM Serial Read Only Memory TFTP Trivial File Transfer Protocol TPE Twisted Pair Ethernet UART Universal Asynchronous Receiver Transmitter UL Underwriters Laboratory VCCI Voluntary Control Council for Interference VITA VMEBUS International Trade Association VME Versa
About this Manual Notation Description .. Ranges, for example: 0..4 means one of the integers 0,1,2,3, and 4 (used in registers) | Logical OR Indicates a hazardous situation which, if not avoided, could result in death or serious injury Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message No danger encountered. Pay attention to important information Summary of Changes The following changes have been made to this manual.
About this Manual Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to: z z Embedded Communications Computing Reader Comments DW164 2900 S. Diablo Way, Suite 190 Tempe, Arizona 85282 eccrc@motorola.com In all your correspondence, please list your name, position, and company. Be sure to include the title and part number of the manual and tell how you used it.
Safety Notes This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment.
Safety Notes Board products are tested in a representative system to show compliance with the above mentioned requirements. A proper installation in a compliant system will maintain the required performance. Use only shielded cables when connecting peripherals to assure that appropriate radio frequency emissions compliance is maintained. Operation Damage of the Product Surface of the Product High humidity and condensation on the product surface causes short circuits.
Safety Notes Damage of Circuits Electrostatic discharge and incorrect installation and removal of the product can damage circuits or shorten their life. Before touching the product or electronic components, make sure that your are working in an ESD-safe environment. Product Damage Inserting or removing modules in a non-hot-swap chassis with power applied may result in damage to module components.
Safety Notes z Make sure that TPE connectors near your working area are clearly marked as network connectors. z Verify that the length of an electric cable connected to a TPE bushing does not exceed 100 m. z Make sure the TPE bushing of the product is connected only to safety extra low voltage circuits (SELV circuits) If in doubt, ask your system administrator.
Sicherheitshinweise Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des Produktes innerhalb Ihrer Betriebsumgebung notwendig sind.
Sicherheitshinweise Das Produkt arbeitet im Hochfrequenzbereich und erzeugt Störstrahlung. Bei unsachgemäßem Einbau und anderem als in diesem Handbuch beschriebenen Betrieb können Störungen im Hochfrequenzbereich auftreten. Wird das Produkt in einem Wohngebiet betrieben, so kann dies mit grosser Wahrscheinlichkeit zu starken Störungen führen, welche dann auf Kosten des Produktanwenders beseitigt werden müssen.
Sicherheitshinweise Beschädigung des Produktes Das Verstellen von Schaltern während des laufenden Betriebes kann zur Beschädigung des Produktes führen. Prüfen und ändern Sie die Schaltereinstellungen, bevor Sie das Produkt installieren. Installation Schwere Verletzungen oder Tod Dieses System wird mit gefährlichen Spannungen betrieben, die schwere Verletzungen oder Tod Verursachen können.
Sicherheitshinweise Beschädigung des Produktes, der Backplane oder von System Komponenten Verbogene Pins oder lose Komponenten können zu einer Beschädigung des Produktes, der Backplane oder von Systemkomponenten führen. Überprüfen Sie daher das Produkt sowie die Backplane vor der Installation sorgältig und stellen Sie sicher, dass sich beide in einwandfreien Zustand befinden und keine Pins verbogen sind.
Introduction 1.1 1 Features The following table summarizes the features of the CPCI-6115 Single Board Computer (SBC). The CPCI-6115 was formerly offered as the MCPN905 SBC. Table 1-1 CPCI-6115 Features Feature Description Processor Single MPC7457 Processor Core Frequency to 1.
Introduction Standard Compliances Table 1-1 CPCI-6115 Features (continued) Feature Description Watchdog Timers Four programmable timer/counters in the Marvel MV64360 One watchdog timer in the Marvell MV64360 One watchdog timer in the M48T37V Peripheral Support Three Gigabit Ethernet interfaces IDE channel to support CompactFlash on transition module Two async serial ports (two rear I/O or one front panel, one rear I/O).
Ordering Information Introduction Table 1-2 Board Standard Compliances (continued) Standard Description NEBS Standard GR-63-CORE Environmental Requirements ETSI EN 300 019 series Directive 2002/95/EC 1.3 Directive on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS) Ordering Information When ordering board variants or board accessories, use the order numbers given in the following tables.
Introduction 28 Ordering Information CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Hardware Preparation and Installation 2.1 2 Overview This chapter provides a brief product description and preparation and installation instructions for the CPCI-6115 CompactPCI CPU board. These instructions include hardware preparation instructions, including jumper settings, system considerations, and installation instructions for the baseboard, as well as the PMCs and transition module associated with this board. The CPCI-6115 can be used in both a CompactPCI or a PICMG 2.16 compatible chassis.
Hardware Preparation and Installation Environmental, Power, and Thermal Requirements Shipment Inspection To inspect the shipment, perform the following steps: 1. Verify that you have received all items of your shipment. 2. Check for damage and report any damage or differences to customer service. 3. Remove the desiccant bag shipped together with the board and dispose of it according to your country’s legislation. The product is thoroughly inspected before shipment.
Environmental Requirements Hardware Preparation and Installation Table 2-1 CPCI-6115 Specifications (continued) Characteristics Specifications Storage temperature –40°C to +70° C (104°F to ‘158°F) Relative humidity 5% to 90% (operating) 5% to 95% (nonoperating) Vibration 1.0G sine sweep, 5-200 Hz, .25 octaves/min, all 3 axis (operating) .5 G sine sweep, 5 - 50 Hz, .1 octaves/min 3.0 G sine sweep, 50 - 500 Hz, .
Hardware Preparation and Installation 2.3.2 Power Requirements Power Requirements The board's power requirements depend on the installed hardware accessories. The following table gives examples of typical power requirements for +5 V and +3.3 V for a processor running at 600 MHz without any accessories. If you want to install any accessories, the load of the respective accessory has to be added to the load of the used board variant.
Thermal Requirements Hardware Preparation and Installation This section provides systems integrators with information that can be used to conduct thermal evaluations of the board in their specific system configuration. It identifies thermally significant components and lists the corresponding maximum allowable component operating temperatures. It also provides sample procedures for component-level temperature measurements.
Hardware Preparation and Installation Figure 2-1 Thermal Requirements CPCI-6115 Thermally Significant Components (Primary Side) U10 U160 U159 J5 U9 U8 U146 U7 U23 U6 U5 U22 U40 U4 J3 U3 U2 J2 U14 U32 U13 34 U36 J1 CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Getting Started Figure 2-2 Hardware Preparation and Installation CPCI-6115 Thermally Significant Components (Secondary Side) U101 U89 U102 2.4 U96 Getting Started This section provides an overview of the steps necessary to install and power up the CPCI6115, any additional equipment requirements, and a brief section on unpacking and ESD precautions. As identified in the following table, several steps can be omitted if your board has been shipped with PMCs already installed. 2.4.
Hardware Preparation and Installation Equipment Required Table 2-4 Startup Overview (continued) 2.4.2 Task Section or Manual Reference Page Install the PMC Module (if required) Installing PMC Modules on the CPCI-6115 43 Install the CPCI-6115 in the chassis. Installing the CPCI-6115 Baseboard 46 Install the transition module. Appendix A, Transition Module Preparation and Installation 113 Connect any other equipment you will be using.
Setting Switches and Jumpers 2.5.2 Hardware Preparation and Installation Setting Switches and Jumpers Figure 2-2 on page 35 illustrates the placement of the switches, jumper headers, connectors and LED indicators on the CPCI-6115. Use this figure to help identify the approximate location of the jumpers on the CPCI-6115. There are seven manually configured headers on the baseboard.
Hardware Preparation and Installation Figure 2-3 J6, Bus Mode Selection Switch and Jumper Locations J9 J6 J10 J15 J16 J17 J99 SW2 J25 J20 U22 SW1 U32 U36 J98 2.5.3 J6, Bus Mode Selection A three-pin header is located on the board to select the correct bus mode operation (60x or MPX). No jumper or a jumper between pins 2 and 3 allows the board to be in MPX mode. A jumper placed between pins 1 and 2 enables 60x mode.
J9, Standalone Operating Mode 2.5.4 Hardware Preparation and Installation J9, Standalone Operating Mode The CPCI-6115 has a standalone operating mode that allows the CPCI-6115 to function without a system slot controller board. Installing a jumper across pins 1 and 2 of J9 enables the standalone mode. The J9 jumper must be removed for normal operation. Figure 2-5 Jumper Settings for J9 An CPCI-6115 configured for standalone mode should not be installed in a chassis with a system slot controller board.
Hardware Preparation and Installation 2.5.6 J15, +/-12 V Present Header J15, +/-12 V Present Header A 2-pin header on the board is used to allow operation with or without +12 V or -12 V supplies. A jumper placed between pins 1 and 2 allows board operation without +/-12 V supplies. No jumper implies that +12 V and -12 V are present at the backplane. Figure 2-7 2.5.7 Jumper Settings for J15 J20, Safe Start Header A 3-pin header is used to select programmed or safe start settings.
J25, SROM Initialization Enable Header 2.5.8 Hardware Preparation and Installation J25, SROM Initialization Enable Header A 3-pin header is used to enable or disable the SROM initialization. A jumper placed between pins 1 and 2 enables the device initialization via the I2C SROM. No jumper or a jumper placed between pins 2 and 3 disables the initialization sequence. Figure 2-9 2.5.
Hardware Preparation and Installation 2.5.10 SW2, Geographic Address SW2, Geographic Address SW2 allows user to set the CPCI-6115's Geographic Address when installed in a chassis that does not supply this information. Setting ON grounds signal, OFF pulls up. 2.
Installing PMC Modules on the CPCI-6115 Hardware Preparation and Installation When it is determined that there are no bent pins on the board connectors or backplane, carefully slide the board into the backplane slots until the board ejector handles come in contact with the system chassis. Do not force the board into the backplane slot. As the handles engage, apply forward pressure while pushing the ejector handles toward each other.
Hardware Preparation and Installation Installing PMC Modules on the CPCI-6115 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure. 2. Remove chassis or system cover(s) as necessary for access to the board. Personal Injury or Death Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing and adjusting. 3.
Installing PMC Modules on the CPCI-6115 Hardware Preparation and Installation The PMC 2 I/O voltage key should be installed in the appropriate position for the PMC to be used. If installed in the +5 V position, PMC 2 is set to +5 V I/O. If installed in the +3.3 V position, PMC 2 is set to +3.3 V I/O. If the PMC accepts either key, install the key in the +3.3 V position (factory default). +3.3 V I/O voltage is required for any PCI/PCI-X operation faster than 33 MHz. 6.
Hardware Preparation and Installation 2.7.2 Installing the CPCI-6115 Baseboard Installing the CPCI-6115 Baseboard Procedure With PMC modules installed (if applicable) and headers properly configured, proceed as follows to install the CPCI-6115 in the CompactPCI chassis: 1. Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure. 2.
Connecting to a Console Port 2.8 Hardware Preparation and Installation Connecting to a Console Port On the CPCI-6115 baseboard, the standard serial console port (COM1) serves as the MOTLoad debugger console port. The firmware console should be set up as follows: z Eight bits per character z One stop bit per character z Parity disabled (no parity) z Baud rate of 9600 9600 baud is the power-up default for serial ports on CPCI-6115 boards.
Hardware Preparation and Installation Applying Power For further information on MOTLoad, refer to Chapter 7, MOTLoad Firmware in this manual, or to the MOTLoad Firmware Package User’s Manual referenced in Appendix A, Related Documentation. Figure 2-11 MOTLoad System Startup The CPCI-6115 front panel has one ABORT/RESET switch and three LED (light-emitting diode) status indicators (BFL, CPU, and HOT SWAP STATUS). For more information on front panel operation, refer to Chapter 4, Functional Description.
Controls, LEDs, and Connectors 3.1 3 Overview This chapter illustrates the placement of the on-board jumper headers and connectors as well as the front panel connectors and LED indicators on the CPCI-6115. Also included are the pin assignments for the connectors and headers on the CPCI-6115 CompactPCI Single Board Computer. Pinout listings can be found in Front Panel Connectors and LEDs on page 50 and On-Board Connectors and Headers on page 52.
Controls, LEDs, and Connectors 3.2 Board Layout Board Layout This figure provides the location and reference designators for major components, switches, and connectors on the base board. Figure 3-1 Component Layout J9 J6 J10 J15 J16 J17 J99 U10 U160 U159 J5 SW2 U9 J25 J21 J23 J11 J13 U8 J20 U7 U6 J22 J24 J12 J14 U5 U22 U4 J3 U3 U2 SW1 J2 J95 U1 U14 U32 J19 U13 J98 3.
Front Panel Connectors and LEDs Controls, LEDs, and Connectors Table 3-1 Front Panel LEDs (continued) LED Indicator Color Status HS Blue Glows solid when the board is ready to extract. SPD/LNK Green/Yellow Shows link status of the Ethernet link (Ethernet 2). Glows solid green: a valid 1000 megabit link. Glows solid yellow: a valid 10/100 megabit link. Off: No link. ALT Green Glows solid: activity is present on the Ethernet link.
Controls, LEDs, and Connectors 3.4 ABORT/Reset Switch ABORT/Reset Switch The CPCI-6115 contains a single push button switch that provides both ABORT and RESET functions. When the switch is depressed for less than 3 seconds, an ABORT interrupt is generated to the processor. If the switch is held for more than 3 seconds, a board hard reset is generated. 3.5 On-Board Connectors and Headers The CPCI-6115 CPU board provides the on-board connectors and jumper headers listed in the next table.
J95, Front Panel 10/100/1000 Megabits/s Ethernet Connector Controls, LEDs, and Connectors Table 3-2 COM1 Pin Assignments, J19 (continued) 3.5.2 Pin # Signal Direction 2 RTS OUTPUT 3 GNDC N/A 4 TXD OUTPUT 5 RXD INPUT 6 GNDC N/A 7 CTS INPUT 8 DTR OUTPUT J95, Front Panel 10/100/1000 Megabits/s Ethernet Connector The CPCI-6115 has one front panel 10/100/1000 megabit/s Gigabit Ethernet connector.
Controls, LEDs, and Connectors 3.5.4 CompactPCI Bus Connector CompactPCI Bus Connector Pinouts for the J1 CompactPCI Bus connector on the CPCI-6115 are as follows: Table 3-4 CompactPCI Connector, J1 Pin Row A Row B Row C Row D Row E 25 +5.0 V REQ64# ENUM# +3.3 V +5.0 V 24 AD[1] +5.0 V V(IO)1 AD[0] ACK64# 23 +3.3 V AD[4] AD[3] +5.0 V1 AD[2] 22 AD[7] GND +3.3 V1 AD[6] AD[5] 21 +3.3 V AD[9] AD[8] M66EN C/BE[0]# 20 AD[12] GND V(IO) AD[11] AD[10] 19 +3.
CompactPCI User I/O Connector Controls, LEDs, and Connectors Table 3-5 CompactPCI Connector, J2 (continued) Pin Row A Row B Row C Row D Row E 19 GND GND RSV RSV RSV 18 BRSVP2A18 BRSVP2B18 BRSVP2C18 GND BRSVP2E18 17 BRSVP2A17 GND RSV RSV RSV 16 BRSVP2A16 BRSVP2B16 RSV GND BRSVP2E16 15 BRSVP2A15 GND RSV RSV RSV 14 AD[35] AD[34] AD[33] GND AD[32] 13 AD[38] GND V(IO) AD[37] AD[36] 12 AD[42] AD[41] AD[40] GND AD[39] 11 AD[45] GND V(IO) AD[44] AD[43] 1
Controls, LEDs, and Connectors CompactPCI Connector Table 3-6 User I/O Connector Pinout, J3 (continued) Pin Row A Row B Row C Row D Row E Pin 14 +3.3 V +3.3 V +3.
CompactPCI User I/O Connector 3.5.8 Controls, LEDs, and Connectors CompactPCI User I/O Connector Connector J5 is a 110-pin AMP Z-pack 2mm hard metric type B connector. This connector routes the I/O signals for one PMC site, an IDE channel, two asynchronous serial ports and the I2C clock and data signals to the CompactPCI backplane. The pin assignments for J5 are as follows: (Note that outer row F is assigned and used as ground pins but is not shown in the table).
Controls, LEDs, and Connectors CompactPCI User I/O Connector Signal Descriptions IDE Port, TTL Levels: DIOW_L I/O write IORDY indicates drive ready for I/O DD(15:0) data lines DRESET_L reset signal to drive CS1FX_L chip select drive 0 or command register block select CS3FX_L chip select drive 1 or command register block select DA(2:0) drive register and data port address lines INTRQ drive interrupt request Asynchronous Serial Ports 1-2, TTL Levels: Signal Description COMxRD receive data
PCI Mezzanine Card (PMC) Connectors 3.5.9 Controls, LEDs, and Connectors PCI Mezzanine Card (PMC) Connectors There are four 64-pin EIA E700 AAAB SMT connectors for each PMC slot on the CPCI-6115 to provide the two 32/64-bit PCI interface and optional I/O interface to the PMC. When the front-panel Gigabit Ethernet is populated, PMC 1 has a 32-bit interface. In this case, these pins are not connected on J13.
Controls, LEDs, and Connectors PCI Mezzanine Card (PMC) Connectors Table 3-8 PMC Connector Pin Assignments, J11/J21 (continued) Pin J11/J21 Pin 61 AD00 +5 V 62 63 GND REQ64# 64 PCI_RSVD = PCI Reserved pin. Table 3-9 PMC ConnectorPin Assignments, J12/J22 60 Pin J12 J22 Pin 1 +12 V TRST# 2 3 TMS TDO 4 5 TDI GND 6 7 GND PCI_RSVD 8 9 PCI_RSVD PCI_RSVD 10 11 MOT_RSVD +3.3 V 12 13 RST# MOT_RSVD 14 15 +3.
PCI Mezzanine Card (PMC) Connectors Controls, LEDs, and Connectors Table 3-9 PMC ConnectorPin Assignments, J12/J22 (continued) Pin J12 J22 Pin 59 GND NC (RESETOUT_L) 60 61 ACK64# +3.
Controls, LEDs, and Connectors PCI Mezzanine Card (PMC) Connectors Table 3-10 PMC Connector Pin Assignments, J13/J23 (continued) Pin J13/J23 Pin 51 GND AD36 (Note 1) 52 53 AD35 (Note 1) AD34 (Note 1) 54 55 AD33 (Note 1) GND 56 57 VIO AD32 (Note 1) 58 59 PCI_RSVD PCI_RSVD 60 61 PCI_RSVD GND 62 63 GND PCI_RSVD 64 Table 3-11 PMC Connector Pin Assignments , J14/J24 Pin 62 J14/J24 Pin 1 PMCIO1 PMCIO2 2 3 PMCIO3 PMCIO4 4 5 PMCIO5 PMCIO6 6 7 PMCIO7 PMCIO8 8 9 P
Boundary Scan JTAG Header Controls, LEDs, and Connectors Table 3-11 PMC Connector Pin Assignments , J14/J24 (continued) Pin 3.5.10 J14/J24 Pin 51 PMCIO51 PMCIO52 52 53 PMCIO53 PMCIO54 54 55 PMCIO55 PMCIO56 56 57 PMCIO57 PMCIO58 58 59 PMCIO59 PMCIO60 60 61 PMCIO61 PMCIO62 62 63 PMCIO63 PMCIO64 64 Boundary Scan JTAG Header This 2x7 0.1" header is used to provide boundary scan testing of all onboard JTAG devices in a single scan chain.
Controls, LEDs, and Connectors Stand-Alone Operation Select Header Table 3-13 Processor JTAG/COP Header Pin Assignments, J17 (continued) 3.5.12 Pin Signal Pin Signal 9 CPUTMS 10 NC 11 SRESET_L 12 NC 13 CPURST_L 14 KEY (no pin) 15 CHKSTPO_L 16 GND Stand-Alone Operation Select Header There is a 0.1", 2-pin header located on the CPCI-6115 to control standalone operation.
Safe Start Header 3.5.14 Controls, LEDs, and Connectors Safe Start Header A 3-pin 2 mm header is located on the board to select programmed or safe start ENV settings. No jumper or a jumper between pins 1 and 2 indicates that the programmed (e.g., VPD, SPD) settings should be used during boot. A jumper between pins 2 and 3 indicates that the safe start settings should be used. The pin assignments for this header are as follows: Table 3-16 Safe Start ENV Header Pin Assignments, J20 3.5.
Controls, LEDs, and Connectors 3.5.17 Flash Bank A Write Protect Header Flash Bank A Write Protect Header A 2-pin 2 mm header is located on the board to enable/disable programming of Flash Bank A to protect the contents from being corrupted. No jumper installed disables all Flash Bank A programming by driving the FLASH VPEN pin to a logic low. The jumper must be installed for erasing array blocks, programming data or configuring lock-bits.
Functional Description 4.1 4 Overview This chapter describes the CPCI-6115 single-board computer on a block diagram level. The General Description section provides an overview of the CPCI-6115, followed by a detailed description of several blocks of circuitry. Figure 4-1 shows a block diagram of the overall board architecture.
Functional Description 4.2 Block Diagram Block Diagram The block diagram below illustrates the architecture of the CPCI-6115 baseboard. Figure 4-1 CPCI-6115 Baseboard Block Diagram L2 Cache + Private Memory 1MB/2MB Processor MPC7457 Init User VPD SPD 60x or MPX Bus 133 MHz Flash A 32MB I2C Flash B 8MB MV64360 System Controller NVRAM RTC M48T37V DDR SDRAM (3 bankS) Device Bus Battery PCI/PCI-X Bus 0.
General Description 4.3 Functional Description General Description The CPCI-6115 is a peripheral slot CompactPCI CPU board based on the MPC7457 processor family and MV64360 PCI-Host bridge/system memory controller and the Intel 21555 PCI-toPCI bridge. The CPCI-6115 supports up to 1.5 GB of DDR SDRAM, two PMC sites, 8MB of boot flash, 32MB of soldered flash, three Gigabit Ethernet ports and one IDE port. The CPCI6115 also supports the CompactPCI Packet Switching Backplane (PICMG 2.16) specification.
Functional Description Processor The MPC7457 processor uses +2.5 V signal levels on the processor bus. Care should be taken that probe boards attached to the debug connector do not pull up or drive signals in violation of this. The JTAG port is tolerant of +3.3 V signals. Arbitration on the processor bus is provided by the MV64360 chip. 4.3.2 Processor The CPCI-6115 has the 360-pin CBGA foot print that supports the MPC7457 family of processors.
MV64360 System Controller z One I2C interface z One four-channel Independent DMA controller Functional Description All of the above interfaces are connected through a cross-bar fabric. The cross-bar enables concurrent transactions between units. For example, the cross-bar can simultaneously control the: 4.3.4.
Functional Description 4.3.4.3 MV64360 System Controller MV64360 32-bit Interface to Devices The device controller supports up to five banks of devices, of which three are used for Flash Bank A and B, NVRAM/RTC, and serial ports on the CPCI-6115. Each bank supports up to 512 MB of address space, resulting in total device space of 1.5 GB. Each bank has its own parameters register as shown in the following table. Table 4-1 Device Bus Parameters 4.3.4.
MV64360 System Controller 4.3.4.6 Functional Description MV64360 Integrated 2 Megabit SRAM The MV64360 integrates 2 megabit (144-bit wide and 2 KB deep) of general purpose SRAM. It is accessible from the CPU or any of the other interfaces. It can be used as fast CPU access memory (6 cycles latency) and for off-loading DRAM traffic. A typical usage of the SRAM could be as a descriptor RAM for the Gigabit Ethernet port. 4.3.4.
Functional Description MV64360 System Controller the second function, the controller is used by the system software to read the contents of the VPD EEPROM contained on the CPCI-6115 board, along with the SPD EEPROMs for the onboard memory banks, to further initialize the memory controller and other interfaces. See the programming model section of this document for more information including I2C bus device addressing.
MV64360 System Controller Functional Description 4.3.4.14 Board Reset Logic The board reset logic is implemented in a programmable logic device (PLD) in order to provide maximum flexibility of the circuit. Refer to Sources of Reset on page 86 for a summary of potential reset sources. 4.3.4.15 MV64360 MPP Configuration The MV64360 contains a 32-bit multi-purpose port (MPP).
Functional Description MV64360 System Controller Table 4-2 MV64360 MPP Pin Function Assignments (continued) MPP Pin Number Input/Output 22 I CompactPCI Bus Interrupts - INTC# 23 I CompactPCI Bus Interrupts - INTD# Function MPP[17:16] PCI_1 Interrupts MPP[19:18] PCI_0 Interrupts, MPP[23:20] CompactPCI Interrupts 24 O MV64360 SROM initialization active (InitAct) 25 O Watchdog Timer Expired output (WDE#) 26 O Watchdog Timer NMI output (WDNMI#) 27 I Unused 28 O PCI Bus 0.
MV64360 System Controller Functional Description The default settings are indicated by bold cell ruling. Table 4-3 MV64360 Power-Up Configuration Settings Device AD Bus Signal Select Option Default Power-Up Setting AD[0] Jumper X Description State of Bit vs.
Functional Description MV64360 System Controller Table 4-3 MV64360 Power-Up Configuration Settings (continued) Device AD Bus Signal Select Option Default Power-Up Setting Description State of Bit vs.
System Memory Functional Description Table 4-3 MV64360 Power-Up Configuration Settings (continued) Device AD Bus Signal WE[3:0], Select Option Default Power-Up Setting X X DP[3:0] Description State of Bit vs.
Functional Description 4.3.6 Flash Memory Flash Memory The CPCI-6115 contains two banks of flash memory accessed via the device controller bus contained within the MV64360 chip. Bank B consists of two Intel StrataFlash +3.3 V devices, configured to operate in 16-bit mode, to form a 32-bit flash bank. Bank B provides a minimum of 8 MB of flash memory. Bank A consists of two Intel StrataFlash +3.3 V devices, configured to operate in 16-bit mode, to form a 32-bit flash bank.
TL16C550C UART Devices 4.3.8 Functional Description TL16C550C UART Devices The CPCI-6115 board contains two Texas Instruments TL16C550C UART devices connected to the MV64360 device controller bus to provide asynchronous serial communication ports. Serial port COM1 can be routed to connector J5 for rear-panel I/O, or through EIA-232 drivers and receivers to an RJ-45 connector on the front panel. When used with a rear transition module (RTM), the routing is selectable via a jumper on the RTM.
Functional Description IDE Controller This bus is limited to 33 MHz PCI because the IDE controller is a 33 MHz-only device. PCI Bus 1.0 is compliant to PCI Revision 2.1. VIO is limited to +5 V only. Do not alter the location of PMC1 keying pin. 4.3.13 IDE Controller The CPCI-6115 uses the CMD Technology PCI646U2 IDE Controller to provide a single IDE channel for external storage devices. The IDE Controller supports ATA/33 transfer rates.
PMC Slots Functional Description from the PMC J14 connector to the CompactPCI J3 I/O connector while the PMC J24 connector signals are routed to the CompactPCI J5 I/O connector. Both PMC I/O connectors are routed to their respective CompactPCI I/O connector following the PIM differential signalling recommendations. The CPCI-6115 front panel allows for front I/O through the PMC faceplate.
Functional Description Miscellaneous Table 4-6 Processor PMC Support (continued) 4.4 PrPMC Signal Support MONARCH# The CPCI-6115 leaves the MONARCH# pin floating, causing any installed processor PMC to operate as a slave module. Processor PMC monarch mode is not supported. IDSELB These IDSELB pins are resistively coupled to the appropriate PCI AD pins. REQB# These REQB# pins are routed to the appropriate PCI bus arbiters. GNTB# These GNTB# pins are routed to the appropriate PCI bus arbiters.
Interrupt Handling 4.4.2.1 Functional Description MV64360 Interrupt Controller The CPCI-6115 uses the MV64360 interrupt controller to route internal and external interrupt requests to the CPU and the PCI bus. The MV64360 interrupt controller registers are implemented as part of the CPU interface unit in order to have minimum read latency from CPU interrupt handler. The external interrupt sources use the GPP interface to register external interrupts.
Functional Description Interrupt Handling 3. The interrupting device is addressed from the MC64360 Device Bus. 4. The interrupting device is addressed from the MV64360 I2C Bus. 5. The interrupting device is addressed from the MV64360 PCI Bus 1.0 through the 21555 PCI-to-PCI bridge. 6. The DS1621 Digital Thermometer and Thermostat provides 9-bit temperature readings which indicate the temperature of the device.
Onboard Power Supplies Functional Description For software compatibility with the GT-64120/130 devices, the MV64360 maintains MByteSwap and MWordSwap bits in the PCI Command register. If the PCI Command register’s MSwapEn bit is set to "1", the MV64360 PCI master performs data swapping according to PCISwap bits setting. If set to "0" (default), it works according to MByteSwap and MWordSwap bits setting, as in the GT-64120/130 devices.
Functional Description 88 Intel 21555 Hot Swap Support z The 21555 contains an Removal Status bit (REM_STAT) in the CompactPCI Hot Swap Control Register to indicate an impending hot swap event. z The 21555 contains an Insertion Status bit (INS_STAT) in the CompactPCI Hot Swap Control Register to indicate that the serial preload is complete and the Primary Lockout bit has been cleared, indicating that the card is ready for host initialization.
5 Transition Module Preparation and Installation 5.1 5 Overview This chapter provides hardware preparation and installation instructions for the CPCI-6115MCPTM transition module. Refer to Chapter 3, Controls, LEDs, and Connectors for pin assignments. The CPCI-6115-MCPTM transition module provides additional I/O capabilities to the CPCI6115 SBC.
Transition Module Preparation and Installation 5.2 Block Diagram Block Diagram The block diagram for the CPCI-6115-MCPTM is shown in the following figure.
Preparing the Transition Module 5.3 Transition Module Preparation and Installation Preparing the Transition Module The CPCI-6115-MCPTM (refer to Figure 5-2) is used in conjunction with the CPCI-6115 baseboard.
Transition Module Preparation and Installation 5.4 Rear Panel Connectors Rear Panel Connectors The rear panel port connectors on the CPCI-6115-MCPTM are listed in Table 5-1 and shown in Figure 5-2 on page 91. Refer to Table 5-10 on page 100 for connector pinout information. Table 5-1 CPCI-6115-MCPTM Rear Panel Connectors 5.5 Type Number Description Serial Ports J25 Routed to four RJ-45 connectors for COM1, COM2, COM3, and COM4 connections (MXP version). Note: COM3 and COM4 are not used.
IDE CompactFlash Connector 5.5.1 Transition Module Preparation and Installation IDE CompactFlash Connector One 50-pin Type II CompactFlash card header connector located on both standard and MXP versions of the CPCI-6115-MCPTM transition module provides the IDE interface to one CompactFlash plug-in module. This CompactFlash interface is connected to the primary IDE channel. The pin assignments for these connectors are as follows: Table 5-3 CompactFlash IDE Connector Pin Assignments, J1 Pin 5.5.
Transition Module Preparation and Installation PMC I/O Module Connectors On the host I/O connectors, a PMC I/O module only uses power, ground and the OUT-going serial port pins. A host I/O module could potentially use all pins except the OUT-going serial port. On the PMC I/O connector, pin meaning is defined entirely by the PMC residing on the host. A host I/O module would not use any pins on this connector. 5.5.2.
PMC I/O Module Connectors Transition Module Preparation and Installation Table 5-4 PMC I/O Module 1 - Host I/O Connector Pin Assignments, J10 (continued) Pin J10 Pin 47 Not Connected Not Connected 48 49 Not Connected GND 50 51 Not Connected Not Connected 52 53 +5 V OUT_DCD 54 55 OUT_DTR Not Connected 56 57 OUT_CTS +3.
Transition Module Preparation and Installation PMC I/O Module Connectors Table 5-5 PMC I/O Module 2 - Host I/O Connector Pin Assignments, J20 (continued) Pin 5.5.2.2 J20 Pin 47 Not Connected Not Connected 48 49 Not Connected GND 50 51 Not Connected Not Connected 52 53 +5 V OUT_DCD 54 55 OUT_DTR Not Connected 56 57 OUT_CTS +3.
CompactPCI User I/O Connector Transition Module Preparation and Installation Table 5-6 PMC I/O Modules 1 and 2 - PMC I/O Connector Pin Assignments, J14/24 (continued) Pin 5.5.
Transition Module Preparation and Installation CompactPCI User I/O Connector Table 5-7 User I/O Connector Pinout, J3 (continued) Pin Row A Row B Row C Row D Row E Pin 5 PMC1IO45 PMC1IO44 PMC1IO43 PMC1IO42 PMC1IO41 5 4 PMC1IO50 PMC1IO49 PMC1IO48 PMC1IO47 PMC1IO46 4 3 PMC1IO55 PMC1IO54 PMC1IO53 PMC1IO52 PMC1IO51 3 2 PMC1IO60 PMC1IO59 PMC1IO58 PMC1IO57 PMC1IO56 2 1 IPMI_PWR PMC1IO64 PMC1IO63 PMC1IO62 PMC1IO61 1 *Not connected on MXP version Signal Description PMCIO:
CompactPCI User I/O Connector Transition Module Preparation and Installation Table 5-8 User I/O Connector Pinout, J5 (continued) Pin Row A Row B Row C Row D Row E Pin 12 PMC2IO10 PMC2IO9 PMC2IO8 PMC2IO7 PMC2IO6 12 11 PMC2IO15 PMC2IO14 PMC2IO13 PMC2IO12 PMC2IO11 11 10 PMC2IO20 PMC2IO19 PMC2IO18 PMC2IO17 PMC2IO16 10 9 PMC2IO25 PMC2IO24 PMC2IO23 PMC2IO22 PMC2IO21 9 8 PMC2IO30 PMC2IO29 PMC2IO28 PMC2IO27 PMC2IO26 8 7 PMC2IO35 PMC2IO34 PMC2IO33 PMC2IO32 PMC2IO31 7
Transition Module Preparation and Installation 10/100/1000BaseTx Connectors Signal Descriptions 5.5.5 I2C_CLK - I2C Serial Clock for transition module EEPROM I2C_DATA - I2C Serial Data for transition module EEPROM 10/100/1000BaseTx Connectors Two 10/100/1000BaseTx RJ-45 connectors are located on the rear panel of the standard version of the CPCI-6115-MCPTM to support Ethernet I/O from the CPCI-6115 SBC.
RJ-45 to DB-9 Adapter for COM1 to PC COM1 Transition Module Preparation and Installation Table 5-10 COM1, COM2 Connector Pin Assignments (continued) 5.5.7 Pin Signal 5 RXD 6 GND 7 CTS 8 DTR RJ-45 to DB-9 Adapter for COM1 to PC COM1 The following information is provided for those users wishing to attach a console to an CPCI6115 COM1 port for the purpose of terminal emulation.
Transition Module Preparation and Installation 5.6 Jumper Settings Jumper Settings This section describes the jumper settings that are required for proper operation prior to installing the CPCI-6115-MCPTM transition module into a chassis backplane. Many boards are already factory configured based on customer requirements, but the jumper settings should be verified before installation. Damage of the Product Setting/resetting the switches during operation can cause damage of the product.
Functional Description Transition Module Preparation and Installation Jumper J6 on the transition module controls the routing of the COM1 port to either the processor board front panel or through the PIM 1 socket on the transition module. When pins 1 and 2 are jumpered on J6, the COM1 signal is routed to the PIM1 socket on the transition module. When pins 2 and 3 are jumpered on J6 the COM1 signal is routed to the processor board front panel.
Transition Module Preparation and Installation Ethernet Interface (CompactPCI Version) The CPCI-6115-MCPTM also routes the IDE signals to the host I/O connector of PMC I/O module 2. Refer to Jumper Settings on page 102 for more details. Currently available CompactFlash memory cards provide from 2MB to 512MB. Once configured, this memory appears as a standard ATA (IDE) disk drive. 5.7.2 Ethernet Interface (CompactPCI Version) The CPCI-6115 SBC provides three 10/100/1000Base-T Ethernet interfaces.
Asynchronous Serial Ports Transition Module Preparation and Installation Due to pin limitations of the J5 connector, the CPCI-6115 SBC multiplexes the serial channel control signals between the CPCI-6115 SBC and the CPCI-6115-MCPTM. This hardware function is transparent to software. The block diagram for the signal multiplexing on the transition module is shown in the following figure: Figure 5-5 5.7.6.
Transition Module Preparation and Installation Asynchronous Serial Ports Table 5-12 Multiplexing Sequence of the IOMX Function (continued) MXDO (From CPCI-6115 SBC) MXDI (From CPCI-6115-MCPTM or CPCI-6106) Time Slot Signal Name Time Slot Signal Name 4 RTS4 4 RI3 5 DTR4 5 CTS4 6 Reserved 6 DSR4 7 Reserved 7 DCD4 8 Reserved 8 CTS2 9 DTR1 9 RI4 10 DTR2 10 RI1 11 Reserved 11 DSR1 12 Reserved 12 DCD1 13 Reserved 13 RI2 14 Reserved 14 DSR2 15 Reserved 15 DCD2
Asynchronous Serial Ports Transition Module Preparation and Installation Serial Port Signal Descriptions 5.7.6.2 RIn ring indicator RTSn request to send Serial Port Redirection It is expected that many PMCs will include a serial debug port in addition to their other I/O.
Transition Module Preparation and Installation 5.7.6.4 PMC I/O Module Port Configuration Diagrams The following interface configuration diagrams describe the interface between the CPCI-6115 SBC and the CPCI-6115-MCPTM.
PMC I/O Module Form Factor Transition Module Preparation and Installation the system integration level. PMC I/O depends entirely upon which, if any, PMC is installed in one or both of the CPCI-6115 SBC PMC sites. To accommodate the pluggable nature of a PMC, a custom form factor pluggable I/O module is presented here. A physical representation of the CPCI-6115-MCPTM and I/O modules is shown below. Figure 5-8 5.7.
Transition Module Preparation and Installation PMC I/O Connector The 80mm is “cut out of the middle” of the PMC I/O module. This means that features in the front half of the module keep their positioning relative to the front edge of the board while features in the back half of the board keep their positioning relative to the back edge of the board. 5.7.
Installing the PIM 5.8 Transition Module Preparation and Installation Installing the PIM Procedure If a PIM has already been installed on the CPCI-6115-MCPTM, or you are installing a transition module as it has been shipped from the factory, disregard this section, and proceed to the main installation section titled Installing the Transition Module on page 113. For PIM installation, perform the following steps: 1. Attach an ESD strap to your wrist.
Transition Module Preparation and Installation Installing the PIM 6. Slide the face plate (front bezel) of the PIM module into the front panel opening from behind and pace the PIM module on top of the transition module, aligned with the appropriate two PIM connectors (P0 and P4). The two connectors on the underside of the PIM module should then connect smoothly with the corresponding connectors on the transition module (J10 and J14). Refer to the following figure for proper screw/board alignment.
Installing the Transition Module 5.9 Transition Module Preparation and Installation Installing the Transition Module After all peripheral modules have been installed and all of the appropriate jumpers have been set, you are ready to install the transition module in its chassis slot. At this point, follow the steps below: Procedure To Install the rear transition module, follow these steps: 1. Attach an ESD strap to your wrist. Attach the other end of the strap to the chassis as a ground.
Transition Module Preparation and Installation 5.10 Removing the Transition Module in a Hot-Swap Chassis Removing the Transition Module in a Hot-Swap Chassis Although the CPCI-6115 SBC can be removed and inserted while power is applied in a hotswap capable backplane, the CPCI-6115-MCPTMs are not hot-swap capable. Inserting or removing the transition module while the CPU board is active may affect the normal operation of the CPU board.
Remote Start via the PCI Bus 6.1 6 Overview This chapter describes the remote interface provided by the firmware to the host CPU via the CompactPCI bus. This interface facilitates the host obtaining information about the board, downloading code and/or data, and execution of the downloaded program. For boards where the 21555 is disabled, the remote start function, as described in the MOTLoad Firmware Package User’s Manual will not work.
Remote Start via the PCI Bus Command/Response Register Description MOTLoad uses certain areas of memory and I/O devices for its own operation. This interface allows the host CPU to write and read any location on the local CPU bus including those in use by the firmware.
MOTLoad Firmware 7.1 7 Overview This chapter describes the basic features of the MOTLoad firmware product, designed by Motorola as the next generation initialization, debugger and diagnostic tool for highperformance embedded board products using state-of-the-art system memory controllers and bridge chips, such as the MV64360.
MOTLoad Firmware 7.4 MOTLoad Commands MOTLoad Commands CPCI-6115 CompactPCI Single Board Computer supports two types of commands (applications): utilities and tests. Both types of commands are invoked from the CPCI-6115 CompactPCI Single Board Computer command line in a similar fashion. Beyond that, CPCI6115 CompactPCI Single Board Computer utilities and CPCI-6115 CompactPCI Single Board Computer tests are distinctly different. 7.
Using MOTLoad MOTLoad Firmware Most MOTLoad tests can be organized to execute as a group of related tests (a testSuite) through the use of the testSuite command. The expert operator can customize their testing by defining and creating a custom testSuite(s). The list of built-in and user-defined MOTLoad testSuites, and their test contents, can be obtained by entering testSuite -dtestSuite at the MOTLoad prompt.
MOTLoad Firmware Command Line Help Example: CPCI-6115> ver Copyright: Motorola Inc. 1999-2002, All Rights Reserved MOTLoad RTOS Version 2.0 PAL Version 0.1 (Motorola CPCI-6115) If the partial command string cannot be resolved to a single unique command, MOTLoad will inform the user that the command was ambiguous. Example: CPCI-6115> te "te" ambiguous CPCI-6115> 7.7.
MOTLoad Command List MOTLoad Firmware z The argument/option identifier character is always preceded by a hyphen (“-”) character. z Options are identified by a single character. z Option arguments immediately follow (no spaces) the option. z All commands, command options, device tree strings, etc., are case sensitive. Example: CPCI-6115> flashProgram -d/dev/flash0 -n00100000 For more information on MOTLoad operation and function, refer to the MOTLoad Firmware Package User’s Manual. 7.
MOTLoad Firmware MOTLoad Command List Table 7-1 MOTLoad Commands (continued) Command Description csb Checksum Byte/Halfword/Word , csh , csw 122 devShow Display (Show) Device/Node Table diskBoot Disk Boot (Direct-Access Mass-Storage Device) downLoad Down Load S-Record from Host ds One-Line Instruction Disassembler echo Echo a Line of Text elfLoader ELF Object File Loader errorDisplay Display the Contents of the Test Error Status Table eval Evaluate Expression execProgram Execute Pro
MOTLoad Command List MOTLoad Firmware Table 7-1 MOTLoad Commands (continued) Command Description mmb mmh mmw Memory Modify Bytes/Halfwords/Words mpuFork Execute program from idle processor mpuShow Display multi-processor control structure mpuSwitch Resets board switching master MPU netBoot Network Boot (BOOT/TFTP) netShow Display Network Interface Configuration Data netShut Disable (Shutdown) Network Interface netStats Display Network Interface Statistics Data noCm Turns off Concurrent
MOTLoad Firmware MOTLoad Command List Table 7-1 MOTLoad Commands (continued) 124 Command Description testRamBitToggle RAM Bit Toggle testRamBounce RAM Bounce testRamCodeCopy RAM Code Copy and Execute testRamEccMonitor Monitor for ECC Errors testRamMarch RAM March testRamPatterns RAM Patterns testRamPerm RAM Permutations testRamQuick RAM Quick testRamRandom RAM Random Data Patterns testRtcAlarm RTC Alarm testRtcReset RTC Reset testRtcRollOver RTC Rollover testRtcTick RTC Tick
Memory Maps 8.1 8 Overview This chapter supplies information for use of the CPCI-6115 family of Single Board Computers in a system configuration. Here you will find descriptions of the memory maps and software initialization. 8.
Memory Maps Processor Memory Map Table 8-1 Default Processor Memory Map (continued) Start End Size Definition 1C80 0000 1CFF FFFF 8 MB Device CS1* 1D00 0000 1DFF FFFF 16 MB Device CS2* 1E00 0000 1FFF FFFF 32 MB Unassigned 2000 0000 21FF FFFF 32 MB PCI Bus 1 I/O 2200 0000 23FF FFFF 32 MB PCI Bus 1 Memory Space 0 2400 0000 25FF FFFF 32 MB PCI Bus 1 Memory Space 1 2600 0000 27FF FFFF 32 MB PCI Bus 1 Memory Space 2 2800 0000 29FF FFFF 32 MB PCI Bus 1 Memory Space 3 2A00 00
Default PCI Memory Map Memory Maps This is a suggested map only. Motorola developed firmware and software adheres to the following mapping, but end user applications are free to select an alternate mapping.
Memory Maps Suggested PCI Memory Map Table 8-3 Default PCI Address Map (continued) Start End Size Definition 1E00 0000 1FFF FFFF 32 MB Unassigned 2000 0000 21FF FFFF 32 MB PCI Bus 0 P2P I/O Space 2200 0000 23FF FFFF 32 MB PCI Bus 0 P2P Memory Space 0 2400 0000 25FF FFFF 32 MB PCI Bus 0 P2P Memory Space 1 2600 0000 41FF FFFF 448 MB Unassigned 4200 0000 4303 FFFF 256 KB MV64360 Integrated SRAM 4304 0000 F1FF FFFF 2800 MB Unassigned F200 0000 F3FF FFFF 32 MB PCI Bus 1 P2P
System I/O Memory Map 8.2.5 Memory Maps System I/O Memory Map System resources including system control and status registers, NVRAM/RTC and the 16550 UART are mapped into a 1 MB address range assigned to Device Bank 1.
Memory Maps 8.2.8 Address Decoding with the 21555 Address Decoding with the 21555 The 21555 implements multiple base address registers on both the primary and secondary interfaces that denote separate address ranges for both downstream and upstream transactions. It also has base registers for access to its Control and Status Register (CSR) space.
A Related Documentation A.1 A Embedded Communications Computing Documents The Motorola publications listed below are referenced in this manual, or apply to systems that use this product. You can obtain paper or electronic copies of Embedded Communications Computing publications by: z Contacting your local Motorola sales office, or z Visiting the Embedded Communications Computing World Wide Web literature site, http://www.motorola.com/computer literature. Table A-1 Motorola ECC Documents A.
Related Documentation Related Specifications Table A-2 Manufacturers’ Documents (continued) Document Title and Source Publication Number or Search Term Intel 21555 Non-Transport PCI-to-PCI Bridge 278320xx Texas Instruments http://www.ti.com TL 16C550C UART SLLS177C ATMEL http://www.atmel.com/atmel/support ATMEL Nonvolitile Memory Data Book AT24Cxx AT93CV6 Broadcom http://www.broadcom.com BCM5421S 10/100/1000Base-T Gigabit Transceiver with SERDES Interface 5421S-DS02R 09/25/01 CMD http://www.cmd.
Related Specifications Related Documentation Table A-3 Related Specifications (continued) Document Title and Source PowerPC Reference Platform (PRP) Specification, Third Edition, Version 1.0, Volumes I and II Publication Number MPR-PPC-RPU-02 International Business Machines Corporation http://www.ibm.com PCI-X Addendum to the PCI Local Bus Specification http://www.pcisig.com (PCI Special Interest Group) Rev. 1.
Related Documentation 134 Related Specifications CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Index Numerics I 21555 dual address mapping role 130 inspecting shipment 29 A J10 address decoding with 21555 130 applying power 47 asynchronous serial ports pin assignments 52 C COM1 pin assignments (905) 52 command line rules MOTLoad 120 comments, sending 16 CompactPCI bus 21555 limited address selection 130 CompactPCI Memory Map 129 compliances 26 Control and Status Register 130 CPCI-6115 block diagram 68 described 69 features 25 D damage reporting 30 disposal of product 27, 30 E EMC requiremen
J10 connector (TM) 93 J10 header (905) 64 J11/J21 connectors (905) 59 J12/J22 connectors (905) 60 J13/J23 connectors (905) 61 J14/J24 connectors (905) 62 J14/J24 connectors (TM) 96 J15 header (905) 66 J16 header (905) 63 J17 header (905) 63 J2 connector (905) 54 J20 connector (TM) 95 J20 header (905) 65 J25 (MXP version) connector (TM) 100 J25 connector (TM) 100 J25 header (905) 65 J3 connector (905) 55 J3 connector (TM) 97 J5 connector (905) 57 J5 connector (TM) 98 J6 header (905) 65 J9 header (905) 64 J99
