700/800-Series MVME162LX Embedded Controller Installation and Use V162-7A/IH1
Notice While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Preface This document provides general information and basic installation instructions for the 700/800-series MVME162LX VME Embedded Controller, which is available in the versions listed below.
Safety Summary Safety Depends On You The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with speciÞc warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola, Inc. assumes no liability for the customer's failure to comply with these requirements.
Lithium Battery Caution The board contains a lithium battery to power the clock and calendar circuitry. ! CAUTION ! Attention ! Vorsicht Danger of explosion if battery is replaced incorrectly. Replace only with the same or equivalent type recommended by the equipment manufacturer. Dispose of used batteries according to the manufacturerÕs instructions. Il y a danger dÕexplosion sÕil y a remplacement incorrect de la batterie.
All Motorola PWBs (printed wiring boards) are manufactured by UL-recognized manufacturers, with a ßammability rating of 94V-0. ! WARNING This equipment generates, uses, and can radiate electromagnetic energy. It may cause or be susceptible to electro-magnetic interference (EMI) if not installed and used in a cabinet with adequate EMI protection. European Notice: Board products with the CE marking comply with the EMC Directive (89/336/EEC).
Contents Lithium Battery Caution 5 Introduction 1-1 Overview 1-1 Related Documentation 1-3 Documents for the MVME162LX 1-4 Other Applicable Motorola Publications 1-4 Applicable Non-Motorola Publications 1-5 Requirements 1-6 Features 1-6 SpeciÞcations 1-9 Cooling Requirements 1-10 Special Considerations for Elevated-Temperature Operation 1-10 FCC Compliance 1-12 Manual Terminology 1-12 Block Diagram 1-14 Functional Description 1-14 Front Panel Switches and Indicators 1-14 Data Bus Structure 1-16 Microprocess
Software-Programmable Hardware Interrupts 1-26 Local Bus Timeout 1-26 Local Bus Arbiter 1-27 Connectors 1-27 Memory Maps 1-28 Local Bus Memory Map 1-28 Normal Address Range 1-28 VMEbus Memory Map 1-34 VMEbus Accesses to the Local Bus 1-34 VMEbus Short I/O Memory Map 1-34 Introduction 2-1 Unpacking Instructions 2-1 Hardware Preparation 2-1 System Controller Select Header (J1) 2-3 IP Bus Clock Header (J11) 2-5 SCSI Terminator Enable Header (J12) 2-6 SRAM Backup Power Source Select Header (J14) 2-6 Flash Write
Memory Requirements 3-13 Disk I/O Support 3-15 Blocks Versus Sectors 3-15 Device Probe Function 3-16 Disk I/O via 162Bug Commands 3-16 IOI (Input/Output Inquiry) 3-16 IOP (Physical I/O to Disk) 3-16 IOT (I/O Teach) 3-17 IOC (I/O Control) 3-17 BO (Bootstrap Operating System) 3-17 BH (Bootstrap and Halt) 3-17 Disk I/O via 162Bug System Calls 3-17 Default 162Bug Controller and Device Parameters 3-19 Disk I/O Error Codes 3-19 Network I/O Support 3-19 Intel 82596 LAN Coprocessor Ethernet Driver 3-20 UDP/IP Proto
Calling System Utilities from User Programs 4-11 Preserving the Debugger Operating Environment 4-11 162Bug Vector Table and Workspace 4-12 Examples 4-12 Hardware Functions 4-13 Exception Vectors Used by 162Bug 4-13 Exception Vector Tables 4-15 Using 162Bug Target Vector Table 4-15 Creating a New Vector Table 4-16 Floating Point Support 4-18 Single Precision Real 4-19 Double Precision Real 4-19 ScientiÞc Notation 4-20 The 162Bug Debugger Command Set 4-20 ConÞgure Board Information Block A-1 Set Environment t
1Board Level Hardware Description 1 Introduction This chapter describes the board level hardware features of the 700/800-series MVME162LX VME Embedded Controller. The chapter is organized with a board level overview and features list in this introduction, followed by a more detailed hardware functional description. Front panel switches and indicators are included in the detailed hardware functional description. The chapter closes with some general memory maps.
1 Board Level Hardware Description connector, and four 8-pin RJ-45 serial connectors on the front panel. In addition, the panel has cutouts for routing of flat cables to the optional IndustryPack modules. The following ASICs are used on the MVME162LX: ❏ VMEchip2. (VMEbus interface).
Introduction Related Documentation The MVME162LX ships with an installation and use manual (the document you are presently reading, Motorola publications number VME162-7A/IH) which includes installation instructions, jumper configuration information, memory maps, debugger/ monitor commands, and any other information needed to start up the board.
1 Board Level Hardware Description Documents for the MVME162LX The following MCG publications are applicable to the 700/800series MVME162LX and may provide additional helpful information. If they are not shipped with this product, you can obtain them by contacting your local Motorola sales office.
Introduction Applicable Non-Motorola Publications The following non-Motorola publications are also available from the sources indicated. Document Title VME64 SpeciÞcation, order number ANSI/VITA 1-1994 Note: An earlier version of the VME speciÞcation is available as Versatile Backplane Bus: VMEbus, ANSI/IEEE Std 1014-1987 (VMEbus SpeciÞcation). This is also available as Microprocessor System Bus for 1 to 4 Byte Data (IEC 821 BUS). Source VITA (VMEbus International Trade Association) 7825 E. Gelding Dr.
1 Board Level Hardware Description Document Title NCR 53C710 SCSI I/O Processor Data Manual, order number NCR53C710DM NCR 53C710 SCSI I/O Processor ProgrammerÕs Guide, order number NCR53C710PG Source NCR Corporation Microelectronics Products Division 1635 Aeroplaza Dr. Colorado Springs, CO 80916 SGS-THOMSON 64K (8K x 8) Timekeeper¨ SRAM Data Sheet, order number M48T08/18 SGS-THOMSON Microelectronics Group Marketing Headquarters 1000 East Bell Rd.
Introduction Table 1-1.
1 Board Level Hardware Description Table 1-1.
Introduction Specifications Table 1-2 lists the specifications for a 700/800-series MVME162LX without IPs. Table 1-2. 700/800-Series MVME162LX: Specifications Characteristics SpeciÞcations Power requirements (with EPROMs; without IPs) +5Vdc (± 5%), 3.5 A typical, 4.
1 Board Level Hardware Description Cooling Requirements The Motorola MVME162LX VME Embedded Controller is specified, designed, and tested to operate reliably with an incoming air temperature range from 0û to 55û C (32û to 131û F) with forced air cooling at a velocity typically achievable by using a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VME system chassis.
Introduction The MVME162LX uses commercial-grade devices. Therefore, it can operate in an environment with ambient air temperatures from 0û C to 70û C. Several factors influence the ambient temperature seen by components on the MVME162LX. Among them are inlet air temperature; airflow characteristics; number, types, and locations of IP modules; power dissipation of adjacent boards in the system, etc.
1 Board Level Hardware Description FCC Compliance The MVME162LX is a board-level product and is meant to be used in standard VME applications. As such, it is the responsibility of system integrators to to meet the regulatory guidelines pertaining to a given application. The MVME162LX has been tested in a representative chassis for CE class B EMC certification. Compliance was achieved under the following conditions: 1. Shielded cables on all external I/O ports. 2.
Introduction An asterisk (*) following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low. An asterisk (*) following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high-to-low transition. In this manual, assertion and negation are used to specify forcing a signal to a particular state.
1 Board Level Hardware Description Block Diagram Refer to Figure 1-1 on page 1-15 for a block diagram of the 700/800series MVME162LX. Functional Description This section contains a functional description of the major blocks on the MVME162LX. Front Panel Switches and Indicators There are two switches and four LEDs on the front panel of the MVME162LX. switch. Resets all onboard devices (including IP modules, if installed) and drives SYSRESET* if the board is system controller.
Optional MC68040 MC68040 MPU IP2 IndustryPack Interface VMEchip2 VMEbus Interface A32/D32 IndustryPack I/O 2 Channels VMEbus A32/24:D64/32/16/08 Master/Slave Optional 4,8,16,32MB ECC DRAM Memory Array 53C710 SCSI Coprocessor SCSI Peripherals 68-pin Front Panel SCSI Connector Configuration Dependent 4,8,16MB Parity DRAM Memory Array i82596CA Ethernet Controller Ethernet Transceiver DB-15 Front Panel Connector Optional MC2chip Two 32-pin EPROM Sockets 128KB SRAM Memory Array w/Battery M48T5
1 Board Level Hardware Description Data Bus Structure The local bus on the MVME162LX is a 32-bit synchronous bus that is based on the MC68040 bus, and which supports burst transfers and snooping. The various local bus master and slave devices use the local bus to communicate. The local bus is arbitrated by priority type arbiter and the priority of the local bus masters from highest to lowest is: 82596CA LAN, 53C710 SCSI, VMEbus, and MPU.
Functional Description No-VMEbus-Interface Option The 700/800-series MVME162LX may be operated as an embedded controller without the VMEbus interface. For this option, the VMEchip2 ASIC and the VMEbus buffers are not populated. Also, the bus grant daisy chain and the interrupt acknowledge daisy chain have zero-ohm bypass resistors installed. To support this feature, certain logic in the VMEchip2 has been duplicated in the MC2chip. This logic is inhibited in the MC2chip when the VMEchip2 is present.
1 Board Level Hardware Description DRAM performance is specified in the section on the DRAM Memory Controller in the MC2chip Programming Model in the MVME162LX Embedded Controller ProgrammerÕs Reference Guide. The DRAM map decoder may be programmed to accommodate different base address(es) and sizes of mezzanine boards. The onboard DRAM is disabled by a local bus reset and must be programmed before the DRAM may be accessed.
Functional Description VMEbus +5V STDBY pin and the secondary source may be the onboard battery. If the system source should fail or the board is removed from the chassis, the onboard battery takes over. Refer to Chapter 2 for the jumper configurations. ! Caution For proper operation of the SRAM, some jumper combination must be installed on the respective Backup Power Source Select Header (J14). If one of the jumpers is used to select the battery, the battery must be installed on the MVME162LX.
1 Board Level Hardware Description battery as a power source, whether primary or secondary, it is necessary to reconfigure the jumpers on J14 before installing the board. Refer to SRAM Backup Power Source Select Header (J14) on page 2-6 for available jumper configurations The power leads from the battery are exposed on the solder side of the board. The board should not be placed on a conductive surface or stored in a conductive bag unless the battery is removed.
Functional Description EPROM and Flash Memory The MVME162LX may be ordered with 2MB of Flash memory and two EPROM sockets ready for the installation of the EPROMs, which may be ordered separately. Flash memory is a single Intel 28F016SA device organized in a 2Mbit x 8 configuration. The EPROM locations are standard JEDEC 32-pin DIP sockets that accommodate three jumper-selectable densities (256 Kbit x 8; 512 Kbit x 8, the factory default; 1 Mbit x8).
1 Board Level Hardware Description Note that the ABORT switch logic in the VMEchip2 is not used. The GPI inputs to the VMEchip2 which are located at $FFF40088 bits 70 are not used. The ABORT switch interrupt is integrated into the MC2chip ASIC at location $FFF42043. The GPI inputs are integrated into the MC2chip ASIC at location $FFF4202C bits 23-16. I/O Interfaces The MVME162LX provides onboard I/O for many system applications.
Functional Description IndustryPack (IP) Interfaces Up to two IP modules may be installed on the 700/800-series MVME162LX as an option. The interface between the IPs and MVME162LX is the IndustryPack Interface Controller (IP2) ASIC. Access to the IPs is provided by two 3M connectors located behind the MVME162LX front panel. Refer to the chapter on the IP2 in the MVME162LX Embedded Controller ProgrammerÕs Reference Guide for detailed features of the IP interface.
1 Board Level Hardware Description Support functions for the 82596CA are provided by the MC2chip. Refer to the 82596CA user's guide and to the MC2chip description in the MVME162LX Embedded Controller ProgrammerÕs Reference Guide for detailed programming information. Optional SCSI Interface The MVME162LX supports mass storage subsystems through the industry-standard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices.
Functional Description Local Resources The MVME162LX includes many resources for the local processor. These include tick timers, software-programmable hardware interrupts, watchdog timer, and local bus timeout. Programmable Tick Timers Six 32-bit programmable tick timers with 1µs resolution are provided, four in the MC2chip and two in the optional VMEchip2. The tick timers may be programmed to generate periodic interrupts to the processor.
1 Board Level Hardware Description Software-Programmable Hardware Interrupts Eight software-programmable hardware interrupts are provided by the VMEchip2. These interrupts allow software to create a hardware interrupt. Refer to the VMEchip2 description in the MVME162LX Embedded Controller ProgrammerÕs Reference Guide for detailed programming information. Local Bus Timeout The MVME162LX provides a timeout function in the VMEchip2 and the MC2chip for the local bus.
Functional Description Local Bus Arbiter The local bus arbiter implements a fixed priority, which is described in the following table. Table 1-3. Local Bus Arbitration Priority Device Priority Note LAN 0 Highest IndustryPack DMA 1 SCSI 2 ... VMEbus 3 Next lowest MC68040 Connectors The MVME162LX has two 96-position DIN connectors: P1 and P2. P1 rows A, B, C, and P2 row B provide the VMEbus interconnection. P2 rows A and C are not used.
1 Board Level Hardware Description Memory Maps There are two points of view for memory maps: 1) the mapping of all resources as viewed by local bus masters (local bus memory map), and 2) the mapping of onboard resources as viewed by external masters (VMEbus memory map). The memory and I/O maps that are described in the next three tables are correct for all local bus masters. There is some address translation capability in the VMEchip2.
Memory Maps I/O space must be marked cache inhibit and serialized in its page table. Table 1-5 on page 1-31 further defines the map for the local I/O devices. Table 1-4.
1 Board Level Hardware Description Table 1-4. Local Bus Memory Map (Continued) Address Range Devices Accessed Port Width Size Software Cache Inhibit Notes -- 512KB N 6 $FFE80000-$FFEFFFFF Not decoded $FFF00000-$FFFEFFFF Local I/O devices (see next table) D32-D8 878KB Y 3 $FFFF0000-$FFFFFFFF VMEbus A16 D32/D1 6 64KB ? 2, 4 Notes 1. Devices mapped at $FFF80000-$FFF9FFFF also appear at $00000000- $001FFFFF when the ROM0 bit in the MC2chip EPROM control register is high (ROM0=1).
Memory Maps Note The IP2 chip on the MVME162LX supports up to four IP interfaces, designated IP_a through IP_d. The 700/800-series MVME162LX itself accommodates two IPs: IP_a and IP_b. In the following map, the segments applicable to IP_c and IP_d are not used in the 700/800series MVME162LX. Table 1-5.
1 Board Level Hardware Description Table 1-5.
Memory Maps Table 1-5. Local I/O Devices Memory Map (Continued) Address Range Devices Accessed $FFFBD000 - $FFFBFFFF Reserved $FFFC0000 - $FFFCFFFF M48T58 (BBRAM, TOD Clock) $FFFD0000 - $FFFEFFFF Reserved Port Width Size Notes -- 12KB 4 D32-D8 64KB 1, 9 -- 128KB 4 Notes 1. For a complete description of the register bits, refer to the data sheet for the specific chip. For a more detailed memory map, refer to the MVME162LX Embedded Controller ProgrammerÕs Reference Guide. 2.
1 Board Level Hardware Description VMEbus Memory Map This section describes the mapping of local resources as viewed by VMEbus masters. Default addresses for the slave, master, and GCSR address decoders are provided by the ENV command. Refer to Appendix A. VMEbus Accesses to the Local Bus The VMEchip2 includes a user-programmable map decoder for the VMEbus-to-local-bus interface. The map decoder allows you to program the starting and ending address and the modifiers that the MVME162LX responds to.
2Hardware Preparation and Installation 2 Introduction This chapter provides unpacking instructions, hardware preparation guidelines, and installation instructions for the 700/800-series MVME162LX VME Embedded Controller. Unpacking Instructions Note If the shipping carton is damaged upon receipt, request that the carrier's agent be present during the unpacking and inspection of the equipment. Unpack the equipment from the shipping carton. Refer to the packing list and verify that all items are present.
Hardware Preparation and Installation Chapter 4, and/or in the MVME162FX Embedded Controller Programmer's Reference Guide as listed in Related Documentation in Chapter 1.) 2 Figure 2-1 illustrates the placement of the switches, jumper headers, connectors, and LED indicators on the MVME162LX. Manually configurable items on the board are listed in the following table. Default settings are enclosed in brackets. Table 2-1.
Hardware Preparation MVME162LX embedded controllers are factory tested and shipped with the default configurations listed above and described in the following sections. The MVME162LXÕs required and factoryinstalled debug monitor, MVME162Bug (162Bug), operates with those factory settings. System Controller Select Header (J1) The MVME162LX is factory-configured as a VMEbus system controller by a jumper across J1 pins 1 and 2.
Hardware Preparation and Installation 2 MVME 162-7XX A1 B1 C1 J6 J5 DS2 49 50 24 25 49 50 24 25 27 26 2 1 27 26 2 1 1 2 S2 P1 49 50 24 25 49 50 24 25 15 J8 J7 J9 BT1 1 2 3 8 J4 1 RESET J3 J2 ABORT 49 50 DS1 1 2 FUSES SCON 49 50 19 20 J1 S1 1 9 ETHERNET PORT 1 1 J11 J12 3 2 16 2 J21 J20 A1 B1 C1 15 1 15 1 1 J19 3 1 1 2 1 2 J14 2 4 2 2 16 J18 J16 5 6 J23 P2 2 8 1 2 J17 7 C 7 8 1 2 4 D 99 100 B J22 8 1 1 2 7 3 99 100 A 2 J
Hardware Preparation IP Bus Clock Header (J11) 2 J11 selects the speed of the IP bus clock. You can either set the IP bus clock to 8MHz or allow it to match the the local bus clock, which is 32MHz for the MC68040. The factory configuration has a jumper between J11 pins 1 and 2 for an 8MHz clock. If the jumper is installed between J11 pins 2 and 3, the IP bus clock speed is the same as that of the MC68040 bus clock, that is 32MHz, allowing the IP module to run with a 32MHz MPU.
Hardware Preparation and Installation 2 SCSI Terminator Enable Header (J12) The MVME162LX provides terminators for the SCSI bus. The SCSI terminators are enabled/disabled by a jumper on header J12. The SCSI terminators may be configured as follows. J12 1 2 Onboard SCSI Bus Terminator Enabled (Factory Configuration) Note J12 1 2 Onboard SCSI Bus Terminator Disabled If the MVME162LX is to be used at one end of the SCSI bus, the SCSI bus terminators must be enabled.
Hardware Preparation Removing all jumpers may temporarily disable the SRAM. Do not remove all jumpers from J14, except for storage.
Hardware Preparation and Installation 2 IP Bus Strobe Select Header (J18) Some IP bus implementations make use of the Strobe∗ signal (pin 46) as an input to the IP modules from the IP2 chip. Other IP interfaces require that the strobe be disconnected. With a jumper installed between J18 pins 1 and 2, a programmable frequency source is connected to the Strobe∗ signal on the IP bus (for details, refer to the IP2 chip programming model in the MVME162LX Embedded Controller ProgrammerÕs Reference Guide).
Hardware Preparation The following table lists the snoop operations represented by the setting of J19. Table 2-2. J19 Snoop Control Encoding Pins 1-2 Pins 3-4 X 0 Snoop disabled X 1 Snoop enabled Snoop Operation X = donÕt care Jumper installed = logic 0 Jumper removed = logic 1 EPROM/Flash Configuration Header (J20) The MVME162LX can be ordered with 2MB of Flash memory and two EPROM sockets ready for the installation of the EPROMs, which may be ordered separately.
Hardware Preparation and Installation 2 J20 J20 15 16 15 16 1 2 1 2 CONFIGURATION 1: 256K x 8 EPROMs CONFIGURATION 2: 512K x 8 EPROMs (FACTORY DEFAULT) J20 J20 15 16 15 16 1 2 1 2 CONFIGURATION 3: 1M x 8 EPROMs CONFIGURATION 4: 1M x 8 EPROMs ONBOARD FLASH DISABLED The next four tables show the address range for each EPROM socket in all four configurations.
Hardware Preparation . 2 Table 2-3. EPROM/Flash Mapping — 256K x 8 EPROMs GPI3 Removed Installed 1 0 Address Range Device Accessed $FF800000 - $FF83FFFF EPROM A (XU1) $FF840000 - $FF87FFFF EPROM B (XU2) $FFA00000 - $FFBFFFFF Onboard Flash $FF800000 - $FF9FFFFF Onboard Flash $FFA00000 - $FFA3FFFF EPROM A (XU1) $FFA40000 - $FFA7FFFF EPROM B (XU2) Table 2-4.
Hardware Preparation and Installation Table 2-6. EPROM/Flash Mapping — 1M x 8 EPROMs, Onboard Flash Disabled 2 GPI3 Removed Installed 1 0 Address Range Device Accessed $FF800000 - $FF8FFFFF EPROM A (XU1) $FF900000 - $FF9FFFFF EPROM B (XU2) Not used Onboard Flash Not used Onboard Flash $FF800000 - $FF8FFFFF EPROM A (XU1) $FF900000 - $FF9FFFFF EPROM B (XU2) General-Purpose Readable Jumpers Header (J21) Header J21 provides eight readable jumpers.
Hardware Preparation 2 J21 162BUG INSTALLED USER CODE INSTALLED USER-DEFINABLE USER-DEFINABLE GPI6 USER-DEFINABLE USER-DEFINABLE GPI5 USER-DEFINABLE USER-DEFINABLE GPI4 USER-DEFINABLE USER-DEFINABLE IN=FLASH; OUT=EPROM IN=FLASH; OUT=EPROM GPI2 REFER TO 162BUG MANUAL USER-DEFINABLE GPI1 REFER TO 162BUG MANUAL USER-DEFINABLE REFER TO 162BUG MANUAL USER-DEFINABLE GPI7 15 GPI3 GPI0 16 7 8 1 2 EPROMs Selected (factory configuration except on no-VMEbus models) Memory Mezzanine O
Hardware Preparation and Installation When the mezzanines are stacked, the following combinations are possible: 2 Table 2-7. Memory Mezzanine Stacking Options Upper Mezzanine None None Parity DRAM ECC DRAM Lower Mezzanine Parity DRAM ECC DRAM ECC DRAM ECC DRAM Note When equipped with a single memory mezzanine, MVME162LX VMEmodules maintain a single VME slot width. With two memory mezzanines, the MVME162LX extends into the adjacent VME slot. The latter versions have double-wide front panels.
Installation Instructions IP Installation on the MVME162LX 2 Up to two IPs may be installed on the 700/800-series MVME162LX. Install the IPs on the board as follows: 1. Each IP has two 50-pin connectors that plug into two corresponding 50-pin connectors on the MVME162LX: J5/J6, J7/J8. See Figure 2-1 for the MVME162LX connector locations. Ð Orient the IP(s) so that the tapered connector shells mate properly. Plug IP_a into connectors J5 and J6; plug IP_b into J7 and J8.
Hardware Preparation and Installation 2 MVME162LX Installation With EPROMs and IPs installed and headers properly configured, proceed as follows to install the MVME162LX in the VME chassis: 1. Turn all equipment power OFF and disconnect the power cable from the AC power source. ! Inserting or removing modules while power is applied could result in damage to module components. Caution ! Warning Dangerous voltages, capable of causing death, are present in this equipment.
Installation Instructions 6. On the chassis backplane, remove the INTERRUPT ACKNOWLEDGE (IACK) and BUS GRANT (BG) jumpers from the header for the card slot occupied by the MVME162LX. Note Some VME backplanes (e.g., those used in Motorola ÔÔModular ChassisÕÕ systems) have an autojumpering feature for automatic propagation of the IACK and BG signals. Step 6 does not apply to such backplane designs. 7.
Hardware Preparation and Installation 2 System Considerations The 700/800-series MVME162LX draws power from both the P1 and the P2 connectors on the VMEbus backplane. P2 is also used for the upper 16 bits of data in 32-bit transfers, and for the upper 8 address lines in extended addressing mode. The MVME162LX may not operate properly without its main board connected to VMEbus backplane connectors P1 and P2.
Installation Instructions Note If you are installing multiple MVME162LXs in an MVME945 chassis, do not install one in slot 12. The height of the IP modules may cause clearance difficulties in that slot position. 2 Other MPUs on the VMEbus can interrupt, disable, communicate with, and determine the operational status of the processor(s).
Hardware Preparation and Installation Figure 2-2 diagrams the pin assignments required in a cable to adapt a DB-25 DTE device to the RJ-45 connectors. 2 DB-25 DTE DEVICE RJ-45 JACK DSR 6 DCD 8 1 RTS 4 2 3 TXD 2 4 RXD 3 5 SG 7 6 CTS 5 7 DTR 20 8 Figure 2-2. DB-25 DTE-to-RJ-45 Adapter Figure 2-3 diagrams the pin assignments required in a cable to adapt a DB-25 DCE device to a RJ-45 connector.
Installation Instructions Figure 2-4 diagrams the pin assignments required in a typical 8conductor serial cable having RJ-45 connectors at both ends. Note that all wires are crossed. RJ-45 CONNECTOR RJ-45 CONNECTOR DCD 1 1 RTS 2 2 SG 3 3 TXD 4 4 RXD 5 5 SG 6 6 CTS 7 7 DTR 8 8 Figure 2-4.
Hardware Preparation and Installation 2 2-22
3Debugger General Information 3 Overview of M68000 Firmware The firmware for the M68000-based (68K) series of board and system level products has a common genealogy, deriving from the debugger firmware currently used on all Motorola M68000-based CPU modules. The M68000 firmware family provides a high degree of functionality and user friendliness, and yet stresses portability and ease of maintenance.
Debugger General Information 3 ❏ A command-driven diagnostic package for the MVME162LX hardware, described in the MVME162Bug Diagnostics Manual and hereinafter referred to as ÔÔthe diagnosticsÕÕ. ❏ A user interface that accepts commands from the system console terminal. When using 162Bug, you operate out of either the debugger directory or the diagnostic directory.
162Bug Implementation 162Bug Implementation MVME162Bug is written largely in the ÔÔCÕÕ programming language, providing benefits of portability and maintainability. Where necessary, assembler has been used in the form of separately compiled modules containing only assembler code Ñ no mixed language modules are used. Physically, 162Bug is contained in a single 27C040 DIP EPROM installed in socket XU2, providing 512KB (128K longwords) of storage.
Debugger General Information Models with no VMEbus interface have a jumper between pins 7-8 as well. These readable jumpers are read as a register (at $FFF4202D) on the Memory Controller (MC2chip) ASIC. The bit values are read as a zero when the jumper is installed, and as a one when the jumper is removed. This jumper block (header J21) contains eight bits. Refer also to the MVME162LX Embedded Controller Programmer's Reference Guide for more information on the MC2chip.
Installation and Startup Note that when the MVME162LX comes up in a cold reset, 162Bug runs in Board Mode. Using the Environment (ENV) or MENU commands can make 162Bug run in System Mode. Refer to Appendix A for details. 2. Configure header J1 by installing/removing a jumper between pins 1 and 2. A jumper installed/removed enables/disables the system controller function of the MVME162LX. 3. The jumper on header J11 configures the IP bus clock for either 8MHz or 32MHz.
Debugger General Information After power-up, you can reconfigure the baud rate of the debug port if necessary by using the 162Bug firmwareÕs Port Format (PF) command. 3 Note In order for high-baud rate serial communication between 162Bug and the terminal to work, the terminal must do some form of handshaking. If the terminal being used does not do hardware handshaking via the CTS line, then it must do XON/XOFF handshaking.
Autoboot 11. Before using the MVME162LX after the initial installation, set the date and time using the following command line structure: 162-Bug> SET 3 [mmddyyhhmm]|[<+/-CAL>;C] For example, the following command line starts the real-time clock and sets the date and time to 10:37 a.m., November 7, 1997: 162-Bug> SET 1107971037 The boardÕs self-tests and operating systems require that the real-time clock be running. Prom Versions When you are using a PROM version of the 162Bug (e.g.
Debugger General Information controllers and devices in a specified sequence until a valid bootable device containing a boot media is found or the list is exhausted. If a valid bootable device is found, a boot from that device is started. The controller scanning sequence goes from the lowest controller Logical Unit Number (LUN) detected to the highest LUN detected. Controllers, devices, and their LUNs are listed in Appendix B.
ROMboot ROMboot As shipped from the factory, 162Bug occupies an EPROM installed in socket XU2. This leaves one socket (XU1) and the Flash memory available for your use. Contact your Motorola sales office for assistance. This function is configured/enabled by the Environment (ENV) command (refer to Appendix A) and executed at powerup (optionally also at reset) or by the RB command assuming there is valid code in the memory devices (or optionally elsewhere on the board or VMEbus) to support it.
Debugger General Information Network Boot Network Auto Boot is a software routine contained in the 162Bug Flash/PROM that provides a mechanism for booting an operating system using a network (local Ethernet interface) as the boot device. If enabled (via ENV Ñ refer to Appendix A), the Network Auto Boot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing a boot media is found or the list is exhausted.
Restarting the System The debugger has a special feature available for reset conditions. You activate it by pressing the RESET and ABORT switches at the same time, releasing RESET first, then releasing ABORT seven seconds later. This ÔÔdouble-button resetÕÕ feature instructs the debugger to use the default setup/operation parameters in ROM versus your setup/operation parameters in NVRAM. You can use this feature in the event your setup/operation parameters are corrupted or do not meet a sanity check.
Debugger General Information For this reason, abort is most appropriate when terminating a user program that is being debugged. Abort should be used to regain control if the program gets caught in a loop, etc. The target PC, register contents, etc., help to pinpoint the malfunction. 3 Pressing and releasing the ABORT switch generates a local board condition which may interrupt the processor if enabled.
Memory Requirements ❏ self test (if system mode) has completed with error ❏ MPU clock speed calculation failure After debugger initialization is done and none of the above situations have occurred, the SYSFAIL∗ line is negated. This indicates to the user or VMEbus masters the state of the debugger. In a multi-computer configuration, other VMEbus masters could view the pertinent control and status registers to determine which CPU is asserting SYSFAIL∗.
Debugger General Information Type of Memory Present 3 A single DRAM mezzanine A single SRAM mezzanine A DRAM mezzanine stacked with an SRAM mezzanine Two DRAM mezzanines stacked Default DRAM Base Address $00000000 N/A $00000000 $00000000 Default SRAM Base Address $FFE00000 (onboard SRAM) $00000000 $E1000000 $FFE00000 (onboard SRAM) DRAM can be ECC or parity type. DRAM mezzanines are mapped in contiguously starting at zero ($00000000), largest first.
Disk I/O Support Disk I/O Support 162Bug can initiate disk input/output by communicating with intelligent disk controller modules over the VMEbus. Disk support facilities built into 162Bug consist of command-level disk operations, disk I/O system calls (only via one of the TRAP #15 instructions) for use by user programs, and defined data structures for disk parameters.
Debugger General Information Device Probe Function A device probe with entry into the device descriptor table is done whenever a specified device is accessed; i.e., when system calls .DSKRD, .DSKWR, .DSKCFIG, .DSKFMT, and .DSKCTRL, and debugger commands BH, BO, IOC, IOP, IOT, MAR, and MAW are used. 3 The device probe mechanism utilizes the SCSI commands Inquiry and Mode Sense. If the specified controller is non-SCSI, the probe simply returns a status of ÔÔdevice present and unknownÕÕ.
Disk I/O Support IOT (I/O Teach) IOT allows you to change any configurable parameters and attributes of the device. In addition, it allows you to see the controllers available in the system. 3 IOC (I/O Control) IOC allows you to send command packets as defined by the particular controller directly. IOC can also be used to look at the resultant device packet after using the IOP command.
Debugger General Information The following system calls are provided to allow user programs to do disk I/O: 3 .DSKRD Disk read. System call to read blocks from a disk into memory. .DSKWR Disk write. System call to write blocks from memory onto a disk. .DSKCFIG Disk conÞgure. This function allows you to change the conÞguration of the speciÞed device. .DSKFMT Disk format. This function allows you to send a format command to the speciÞed device. .DSKCTRL Disk control.
Network I/O Support specifically tailored for the disk drive controller it is sent to. Refer to documentation on the particular controller module for the format of its packets, and for using the IOC command. 3 Default 162Bug Controller and Device Parameters 162Bug initializes the parameter tables for a default configuration of controllers and devices (refer to Appendix B).
Debugger General Information The booting process is executed in two distinct phases. ❏ The first phase allows the diskless remote node to discover its network identify and the name of the file to be booted. ❏ The second phase has the diskless remote node reading the boot file across the network into its memory. 3 The various modules (capabilities) and the dependencies of these modules that support the overall network boot function are described in the following paragraphs.
Network I/O Support RARP/ARP Protocol Modules The Reverse Address Resolution Protocol (RARP) basically consists of an identity-less node broadcasting a ÔÔwhoamiÕÕ packet onto the Ethernet, and waiting for an answer. The RARP server fills an Ethernet reply packet up with the target's Internet Address and sends it. The Address Resolution Protocol (ARP) basically provides a method of converting protocol addresses (e.g., IP addresses) to local area network addresses (e.g., Ethernet addresses).
Debugger General Information Network I/O Error Codes 162Bug returns an error code if an attempted network operation is unsuccessful. 3 Multiprocessor Support The MVME162LX dual-port RAM feature makes the shared RAM available to remote processors as well as to the local processor. This can be done by either of the following two methods. Either method can be enabled/disabled by the ENV command as its Remote Start Switch Method (refer to Appendix A).
Multiprocessor Support You can only program Flash memory by the MPCR method. Refer to the .PFLASH system call in the Debugging Package for Motorola 68K CISC CPUs User's Manual for a description of the Flash memory program control packet structure. The status codes that may be set by the bus master are: ASCII G (HEX 47) - Use Go Direct (GD) logic specifying the MPAR address. ASCII B (HEX 42) - Install breakpoints using the Go (G) logic.
Debugger General Information In either sequence, an E is placed in the MPCR to indicate that execution is underway just before control is passed to RAM. (Any remote processor could examine the MPCR contents.) 3 If the code being executed in dual-port RAM is to reenter the debug monitor, a TRAP #15 call using function $0063 (SYSCALL .RETURN) returns control to the monitor with a new display prompt.
Diagnostic Facilities The address appears as: GPCSR0 GPCSR1 3 Diagnostic Facilities The 162Bug package includes a set of hardware diagnostics for testing and troubleshooting the MVME162LX. To use the diagnostics, switch directories to the diagnostic directory. If you are in the debugger directory, you can switch to the diagnostic directory with the debugger command Switch Directories (SD). The diagnostic prompt 162-Diag> appears.
Debugger General Information If either string is in the first location of NVRAM ($FFFC0000), the test process starts.
4Using the 162Bug Debugger 4 In This Chapter This chapter covers the following subjects: ❏ Entering debugger command lines ❏ Entering and debugging programs ❏ Calling system utilities from user programs ❏ Preserving the debugger operating environment ❏ Floating point support ❏ The 162Bug debugger command set Entering Debugger Command Lines 162Bug is command-driven and performs its various operations in response to user commands entered at the keyboard.
Using the 162Bug Debugger Note 4 The presence of the upward caret ( ^ ) before a character indicates that the Control (CTRL) key must be held down while striking the character key. ^X (cancel line) The cursor is backspaced to the beginning of the line. ^H (backspace) The cursor is moved back one position. Delete key (delete) Performs the same function as ^H. ^D (redisplay) The entire command line as entered so far is redisplayed on the following line. ^A (repeat) Repeats the previous line.
Entering Debugger Command Lines Debugger Command Syntax In general, a debugger command is made up of the following parts: ❏ The command identifier (i.e., MD or md for the Memory Display command). Note that either upper- or lowercase characters are allowed. ❏ A port number if the command is set up to work with more than one port. ❏ At least one intervening space before the first argument. ❏ Any required arguments, as specified by the command.
Using the 162Bug Debugger Numeric values may be expressed in either hexadecimal, decimal, octal, or binary notation by immediately preceding them with the proper base identifier. Base 4 IdentiÞer Examples Hexadecimal $ $FFFFFFFF Decimal & &1974, &10-&4 Octal @ @456 Binary % %1000110 If no base identifier is specified, then the numeric value is assumed to be hexadecimal. A numeric value may also be expressed as a string literal of up to four characters.
Entering Debugger Command Lines Valid expression examples: Expression Result (In Hex) Notes FF0011 FF0011 45+99 DE &45+&99 90 @35+@67+@10 5C %10011110+%1001 A7 88<<4 880 shift left AA&F0 A0 logical AND 4 The total value of the expression must be between 0 and $FFFFFFFF. Address as a Parameter Many commands use addr as a parameter. The syntax accepted by 162Bug is similar to the one accepted by the MC68040 one-line assembler. All control addressing modes are allowed.
Using the 162Bug Debugger Address Formats Table 4-1 summarizes the address formats that are acceptable for address parameters in debugger command lines. Table 4-1. Debugger Address Parameter Formats 4 Format Example Description N 140 Absolute address+contents of automatic offset register. N+Rn 130+R5 Absolute address+contents of the speciÞed offset register (not an assembler-accepted syntax). (An) (A1) Address register indirect.
Entering Debugger Command Lines Note In commands with range specified as addr addr, and with size option W or L chosen, data at the second (ending) address is acted on only if the second address is a proper boundary for a word or longword, respectively. 4 Offset Registers Eight pseudo-registers (R0 through R7) called offset registers are used to simplify the debugging of relocatable and positionindependent modules.
Using the 162Bug Debugger 8 0 00000008 5340 9 0 0000000A 12D8 LOOP SUBQ.W#1,D0 MOVE.B(A0)+,(A1)+ 10 0 0000000C 51C8FFFC MOVS DBRA 11 0 00000010 4CDF0101 MOVEM.L(A7)+,D0/A0 12 0 00000014 4E75 RTS D0,LOOP 13 4 14 END ****** TOTAL ERRORS END 0ÑÑ ****** TOTAL WARNINGS 0ÑÑ The above program was loaded at address $0001327C.
Entering and Debugging Programs For additional information about the offset registers, refer to the Debugging Package for Motorola 68K CISC CPUs User's Manual. Port Numbers Some 162Bug commands give you the option to choose the port to be used to input or output. Valid port numbers which may be used for these commands are as follows: 1. MVME162 EIA-232-D Debug (Terminal Port 0 or 00) (Port 1 on the MVME162LX J17 front panel connector).
Using the 162Bug Debugger Creating a Program with the Assembler/Disassembler You can create a program using the Memory Modify (MM) command with the assembler/disassembler option. 1. Enter the program one source line at a time. 4 2. After each source line is entered, it is assembled and the object code is loaded to memory. Refer to the Debugging Package for Motorola 68K CISC CPUs User's Manual for details on the 162Bug Assembler/Disassembler.
Calling System Utilities from User Programs Calling System Utilities from User Programs A convenient way of doing character input/output and many other useful operations has been provided so that you do not have to write these routines into the target code. You can access various 162Bug routines via one of the MC68040 TRAP instructions, using vector #15.
Using the 162Bug Debugger 162Bug Vector Table and Workspace As described in the Memory Requirements section of Chapter 3, the 162Bug firmware needs 64KB of read/write memory to operate. 162Bug reserves ... 4 For ... 1024-byte area A user program vector table area 1024-byte area An exception vector table for the debugger itself to use Space for static variables, and initializes these static variables to predeÞned default values.
Preserving the Debugger Operating Environment Hardware Functions The only hardware resources used by the debugger are the EIA232-D ports, which are initialized to interface to the debug terminal and a host. If these ports are reprogrammed, the terminal characteristics must be modified to suit, or the ports should be restored to the debugger-set characteristics prior to reinvoking the debugger. Exception Vectors Used by 162Bug The exception vectors used by the debugger are listed below.
Using the 162Bug Debugger pointer values just before the exception occurred. In this way, the operation of the debugger facility (through an exception) is transparent to users. Example: Trace one instruction using the debugger firmware. 172-Bug>rd 4 PC =00010000 SR =2708=TR:OFF_S._7_N.. VBR =00000000 SSP =0000FFFC USP =00010000 DFC =1=UD CACR =00000000=D: ....._B:..._I:...
Preserving the Debugger Operating Environment Exception Vector Tables Notice in the preceding example that the value of the target stack pointer register (A7) has not changed even though a trace exception has taken place. Your program may either use the exception vector table provided by 162Bug or it may create a separate exception vector table of its own. The two following sections detail these two methods.
Using the 162Bug Debugger Creating a New Vector Table Your program may create a separate vector table in memory to contain its exception vectors. If this is done, the program must change the value of the VBR to point at the new vector table. In order to use the debugger facilities you can copy the proper vectors from the 162Bug vector table into the corresponding vector locations in your program vector table.
Preserving the Debugger Operating Environment It may turn out that your program uses one or more of the exception vectors that are required for debugger operation. Debugger facilities may still be used, however, if your exception handler can determine when to handle the exception itself and when to pass the exception to the debugger. When an exception occurs which you want to pass on to the debugger (i.e.
Using the 162Bug Debugger Floating Point Support The floating point unit (FPU) of the MC68040 microprocessor chip is supported in 162Bug. The MD, MM, RM, and RS commands have been extended to allow display and modification of floating point data in registers and in memory. Floating point instructions can be assembled and disassembled with the DI option of the MD and MM commands.
Floating Point Support 4. The sign field, the exponent field, and at least the first digit of the mantissa field must be present (any unspecified digits in the mantissa field are set to zero). 5. Each field must be separated from adjacent fields by an underscore. 6. All the digit positions in the sign and exponent fields must be present. Single Precision Real This format would appear in memory as: 1-bit sign Þeld (1 binary digit) 8-bit biased exponent Þeld (2 hex digits.
Using the 162Bug Debugger Scientific Notation This format provides a convenient way to enter and display a floating point decimal number. Internally, the number is assembled into a packed decimal number and then converted into a number of the specified data type. 4 Entering data in this format requires the following fields: ❏ An optional sign bit (+ or -). ❏ One decimal digit followed by a decimal point. ❏ Up to 17 decimal digits (at least one must be entered).
The 162Bug Debugger Command Set Table 4-3.
Using the 162Bug Debugger Table 4-3.
The 162Bug Debugger Command Set Table 4-3.
Using the 162Bug Debugger Table 4-3.
AConfigure and Environment Commands A Configure Board Information Block CNFG [;[I][M]] This command is used to display and configure the board information block. This block is resident within the Non-Volatile RAM (NVRAM). Refer to the Debugging Package for Motorola 68K CISC CPUs User's Manual for the actual location. The information block contains various elements detailing specific operation parameters of the hardware.
A Configure and Environment Commands Parity Memory Mezzanine (PWA) Serial Number = " " Static Memory Mezzanine Artwork (PWA) Identifier = " " Static Memory Mezzanine (PWA) Serial Number = " " ECC Memory Mezzanine #1 Artwork (PWA) Identifier = " " ECC Memory Mezzanine #1 (PWA) Serial Number = " " ECC Memory Mezzanine #2 Artwork (PWA) Identifier = " " ECC Memory Mezzanine #2 (PWA) Serial Number = " " Serial Port 2 Personality Artwork (PWA) Identifier = " " Serial Port 2 Personality Module (PWA) Serial Numbe
Set Environment to Bug/Operating System Modification is possible through use of the commandÕs M option. At the end of the modification session, you are prompted for the update to Non-Volatile RAM (NVRAM). A Y response must be made for the update to occur; any other response terminates the update (disregards all changes). The update also recalculates the checksum. Be cautious when modifying parameters.
A Configure and Environment Commands If the ENV command is invoked with no options on the command line, you are prompted to configure all operational parameters. If the ENV command is invoked with the option D, ROM defaults will be loaded into NVRAM. The parameters to be configured are listed in the following table. Table A-1.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Auto Boot at power-up only [Y/N] Y Auto Boot is attempted at power-up reset only. Auto Boot Controller LUN 00 LUN of a disk/tape controller module currently supported by the Bug. Default is $0. Auto Boot Device LUN 00 LUN of a disk/tape device currently supported by the Bug. Default is $0.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Network Auto Boot Enable [Y/N] N Network Auto Boot function is disabled. Network Auto Boot at powerup only [Y/N] Y Network Auto Boot is attempted at power up reset only. Network Auto Boot Controller LUN 00 LUN of a disk/tape controller module currently supported by the Bug. Default is $0.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Memory Search Ending Address 00100000 Top limit of the Bug's search for a work page. If a contiguous block of memory, 64KB in size, is not found in the range speciÞed by Memory Search Starting Address and Memory Search Ending Address parameters, then the bug will place its work page in the onboard static RAM on the MVME162LX.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Memory Search Delay Address FFFFD20F Default address is $FFFFD20F. This is the MVME162LX GCSR (global control/status register) GPCSR0 as accessed through VMEbus A16 space. It is assumed that the MVME162LX GRPAD (group address) and BDAD (board address within group) switches are set to ÔÔonÕÕ.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Memory ConÞguration Defaults: The default conÞguration for Dynamic RAM mezzanine boards will position the mezzanine with the largest memory size to start at the address selected with the ENV parameter ÔÔBase Address of Dynamic MemoryÕÕ. The Base Address parameter defaults to 0. The smaller sized mezzanine will follow immediately above the larger in the memory map.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default ENV asks the following series of questions to set up the VMEbus interface for the MVME162LX modules. You should have a working knowledge of the VMEchip2 as given in the MVME162LX Embedded Controller Programmer's Reference Guide in order to perform this conÞguration. Also included in this series are questions for setting ROM and Flash access time.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Slave Ending Address #2 00000000 Ending address of the local resource that is accessible by the VMEbus. Default is 0. Slave Address Translation Address #2 00000000 Works the same as Slave Address Translation Address #1. Default is 0. Slave Address Translation Select #2 00000000 Works the same as Slave Address Translation Select #1. Default is 0.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Master Control #2 Default 00 Meaning of Default DeÞnes the access characteristics for the address space deÞned with this master address decoder. Default is $00. Master Enable #3 [Y/N] Y/N (Depends on calculated size of local RAM) Yes, set up and enable the Master Address Decoder #3. This is the default if the board contains less than 16MB of calculated RAM.
Set Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Master Address Translation Address #4 00000000 Allows the VMEbus address and the local address to differ. The value in this register is the base address of the VMEbus resource that is associated with the starting and ending address selection from the previous questions. Default is 0.
A Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default VMEC2 GCSR Group Base Address D2 SpeciÞes the group address ($FFFFXX00) in Short I/O for this board. Default = $D2. VMEC2 GCSR Board Base Address 00 SpeciÞes the base address ($FFFFD2XX) in Short I/O for this board. Default = $00. VMEbus Global Time Out Code 01 Controls the VMEbus timeout when the MVME162LX is operating as system controller.
Set Environment to Bug/Operating System Base address for mapping IP modules. Only the upper 16 bits are significant.
A Configure and Environment Commands IP D/C/B/A Interrupt 0 Control = 00000000? Define the interrupt control requirements for the IP modules channel 0: Bits IP Register Address 31-24 D FFFBC016 23-16 C FFFBC014 15-08 B FFFBC012 07-00 A FFFBC010 IP D/C/B/A Interrupt 1 Control = 00000000? Define the interrupt control requirements for the IP modules channel 1: ! Caution A-16 Bits IP Register Address 31-24 D FFFBC017 23-16 C FFFBC015 15-08 B FFFBC013 07-00 A FFFBC011 Before
Set Environment to Bug/Operating System ENV warning example: WARNING: Memory MAP Overlap Condition Exists S-Address $00000000 $FFE00000 $01000000 $00000000 $00000000 $00000000 $F0000000 $FFFF0000 $FF800000 $FFF00000 $00000000 $00000000 $00000000 $00000000 $00000000 $00000000 E-Address $FFFFFFFF $FFE7FFFF $EFFFFFFF $00000000 $00FFFFFF $00000000 $FF7FFFFF $FFFFFFFF $FFBFFFFF $FFFEFFFF $00000000 $00000000 $00000000 $00000000 $00000000 $00000000 Enable Yes Yes Yes No Yes No Yes Yes Yes Yes No No No No No No
A Configure and Environment Commands A-18
BDisk/Tape Controller Data B Disk/Tape Controller Modules Supported The following VMEbus disk/tape controller modules are supported by the 162Bug. The default address for each controller type is First Address and the controller can be addressed by First CLUN during commands BH, BO, or IOP, or during TRAP #15 calls .DSKRD or .DSKWR.
Disk/Tape Controller Data B B Disk/Tape Controller Default Configurations Note SCSI Common Command Set (CCS) devices are the only ones tested by Motorola Computer Group.
Disk/Tape Controller Default Configurations B MVME328 -- 14 Devices B Controller LUN Address Device LUN Device Type 6 $FFFF9000 7 $FFFF9800 16 $FFFF4800 00 08 10 18 20 28 30 SCSI Common Command Set (CCS), which may be any of these: - Removable ßexible direct access (TEAC style) - CD-ROM - Sequential access 17 $FFFF5800 18 $FFFF7000 Same as above, but these are only available if the daughter card for the second SCSI channel is present.
Disk/Tape Controller Data B B IOT Command Parameters for Supported Floppy Types The following table lists the proper IOT command parameters for floppies used with boards such as the MVME328 and MVME162LX.
IOT Command Parameters for Supported Floppy Types B Floppy Types and Formats IOT Parameter Number of Logical Blocks (100 in size) Number of Bytes in Decimal Media Size/Density B DSDD5 PCXT8 PCXT9 PCXT9_3 PCAT PS2 SHD 09F8 0500 05A0 0B40 12C0 1680 2D00 653312 327680 368460 737280 1228800 1474560 2949120 3.5/DD 5.25/HD 3.5/HD 3.5/ED 5.25/DD 5.25/DD 5.25/DD Notes 1. All numerical parameters are in hexadecimal format unless otherwise noted. 2.
Disk/Tape Controller Data B B B-6
CNetwork Controller Data C Network Controller Modules Supported The following VMEbus network controller modules are supported by the MVME162BUG firmware. The default address for each type and position is showed to indicate where the controller must reside to be supported by MVME162BUG. The controllers are accessed via the specified CLUN and DLUNs listed here.
Network Controller Data C C-2
DTroubleshooting CPU Boards D Solving Startup Problems In the event of difficulty with your CPU board, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment. (The board was tested under those conditions before it left the factory.) The self-tests may not run in all user-customized environments. Table D-1.
Troubleshooting CPU Boards Table D-1. Troubleshooting MVME162LX Boards (Continued) D Condition Possible Problem Try This: II. There is a display on the terminal, but input from the keyboard and/or mouse has no effect. A. The keyboard or mouse may be connected incorrectly. Recheck the keyboard and/or mouse connections and power. B. Board jumpers may be conÞgured incorrectly. Check the board jumpers per this manual. C.
Solving Startup Problems Table D-1. Troubleshooting MVME162LX Boards (Continued) Condition IV. Continued Possible Problem Try This: 2. At the command line prompt, type in: env;d This sets up the default parameters for the debugger environment. 3. When prompted to Update Non-Volatile RAM, type in: y 4. When prompted to Reset Local System, type in: y 5. After clock speed is displayed, immediately (within Þve seconds) press the Return key: or BREAK to exit to the System Menu.
Troubleshooting CPU Boards Table D-1. Troubleshooting MVME162LX Boards (Continued) D Condition Possible Problem Try This: V. The debugger is in system mode and the board autoboots, or the board has passed selftests. A. No apparent problems Ñ troubleshooting is done. No further troubleshooting steps are required. VI. The board has failed one or more of the tests listed above, and cannot be corrected using the steps given. A.
Index Numerics 162Bug 4-1 installation 3-3 162Bug (MVME162Bug) 2-3 162Bug command set 4-20 162Bug default controller and device parameters 3-19 162Bug firmware 3-1 162Bug implementation 3-3 162Bug stack space 3-14 162Bug static variable space 3-14 162Bug vector table and workspace 4-13 172Bug implementation of 3-3 27C040 EPROM 3-3 82596CA 1-23 A Abort function 3-11 ABORT switch 1-14 address (command syntax) 4-3 address formats 4-6, 4-7 address range 1-28 address ranges, EPROM 2-10 address/data configurati
Index Break function 3-12 BREAK key 3-12 bus grant (BG) signal 2-17 byte, definition of 1-13 C C programming language 3-3 cable(s) 2-17 checksum, testing NVRAM contents with A-3 CLUN (controller LUN) B-2, C-1 command identifier, debugger 4-3 command lines, debugger 4-1 command syntax, debugger 4-3 commands Configure Board Information Block (CNFG) A-1 Set Environment (ENV) A-3 configuration, hardware 3-4 configuring IndustryPacks A-14 configuring the board 2-1 configuring VMEbus interface A-10 connections,
elevated-temperature operation 1-10 entering and debugging programs 4-9 entering debugger command lines 4-1 ENV command parameters A-4 EPROM (see 27C040 EPROM) 3-3 EPROM address ranges 2-10 EPROM and Flash memory 1-21 EPROM sockets 2-9 EPROM/Flash mapping 2-11 EPROM/Flash selection 2-12 error codes, disk I/O 3-19 error codes, network I/O 3-22 Ethernet C-1 station address 1-23 Ethernet driver 3-20 Ethernet interface 1-23 exception vectors, 162Bug 4-13 exponent field (floating point support) 4-18 expression (
Index Intel 82596 LAN coprocessor Ethernet driver 3-20 interface Ethernet 1-23 IndustryPack (IP) 1-23 SCSI 1-24 serial 1-22 serial communications 2-19 VMEbus 1-21 interprocessor communication 3-22 interrupt acknowledge (IACK) signal 2-17 Interrupt Stack Pointer (ISP) 3-14 interrupts, hardware 1-26 IOC (I/O control) command 3-17 IOI (input/output inquiry) command 3-16 IOP (physical I/O to disk) command 3-16 IOT (I/O teach) command 3-17 IOT command parameters for supported floppy types B-4 IP (IndustryPack)
microprocessor, description of 1-16 MPCR (Multiprocessor Control Register) method 3-22 MPU clock speed calculation 3-13 Multiprocessor Control Register (MPCR) 3-22 Multiprocessor Control Register (MPCR) method 3-22 multiprocessor support 3-22 MVME162Bug 1-17, 3-1 MVME162Bug (162Bug) 2-3 MVME162LX block diagram 1-15 MVME162LX features 1-6 MVME162LX installation 2-16 MVME162LX specifications 1-9 MVME172 C-1 MVME328 SCSI controller B-1, B-2, B-3 MVME374 C-1 MVME376 C-1 N negation, definition of 1-13 network b
Index I N D E X SCSI termination 1-24 SCSI terminator configuration 1-24, 2-6 SD command 3-25 serial cable connections 2-20 serial communications 2-19 serial communications Controllers (Z85230s) 3-6 serial ports 3-5, 4-13 default baud rate 3-5 serial ports 1-4 4-9 shielded cables 2-17 sign field (floating point support) 4-18 single precision real 4-19 single precision real (floating point format) 4-19 slave address decoders, VMEbus interface A-10 software-programmable hardware interrupts 1-26 source lines
Z Z85230 serial communications controllers (SCCs) 3-6 I N D E X IN-11
