Confidential Hardware Architecture Figure | shows a high level block diagram of the TRAIT X 2G GPS TRACKER system hardware. The core architecture is defined a highly integrated GARS chip set and single chip GPS receiver. The motion detector is optionally populated at assembly time Signal and power interface to the PCB is through a strain relieved 7 lead pigtail shames. Fewer wires may be populated as a cost reduction option af the factory at assembly time.
Confidential Preliminary — Subject to Change Software Architecture The TRAIT X 2G GPS TRACKER does not use an external applications processor. Structure Figure 2 shows a high level block diagram of the basic architecture. The OS is closely knit with a debugger allowing for code development, maintenance and updates over the USB port. The boot loader provides control over all code and configuration memory.
Confidential Preliminary — Subject to Change o GPS power control o Setup and monitor geographic fences e Device initiated UDP reporting Recurring schedule event Low battery condition Change in GPO state Report record queue User defined IP addresses Geographic fence violation Virtual AT command processor over SMS or a UDP/AP connection eo OTA code update using FTP o 100% buffered © Established standard protocol Application specific 1/0 o Readmitted digital o Read battery voltage APN support with optional cre
Confidential Preliminary — Subject to Change Physical Attributes Figures 3A and 3B show various exterior views and dimensions of the TRAIT X 2G GPS TRACKER Tracker and some critical physical features. The top and bottom half shells are conically welded together to provide a water resistant seal around the case perimeter. Through pressure engagement around the cable strain relief the welded enclosure also provides water resistance around the cable shames.
Confidential Preliminary — Subject to Change Figure 3B TRAIT X 2G GPS TRACKER Exterior x Dimensions: = Inches [mm] © 2011 Montage Asia Page 140f 19
Confidential Preliminary — Subject to Change Figure 4 shows a various internal attributes of the TRAIT X 2G GPS TRACKER. The SIM is an embedded QFN package that is mounted during board assembly. Test is accomplished using special carrier provisioning and through probe holes that bypass the SIM and are later covered by the water resistant label.
Confidential Preliminary — Subject to Change Figure 4 TRAIT X 2G GPS TRACKER Interior SIM Test Points, Embedded SIM Embedded SIM GPS Antenna Lap Solder Connections Exploded View © 2011 Montage Asia Page 160f19
Confidential Preliminary — Subject to Change Interfaces Electrical interface to the outside world is accomplished through a 7-lead pigtail wire harness that is retained directly by the conically welded enclosure. Test points required for final test and provisioning are provided by port holes that are covered by the water resistant plastic label when applied.
Confidential Preliminary — Subject to Change NOTE Equivalent Circuit for GP1 and GP2 2.8V SOQ) Lead To Circuit Harness Preparation The length of the harness is a manufacturing option. The shames is comprised of 28 AWG stranded automotive grade wires with solid colors as specified in the table above. Unless otherwise specified. the harness ends are stripped as shown in Figaro 5. Figure 5 Wire End Preparation Retain Insulation ——A 12 Twn 12.
Confidential Preliminary — Subject to Change LED The two status LED directly convey the status of the GPS subsystems as described in the table below. Indirectly, through their absence of a valid indication, they also provide power and operational status. These LED are color coded and located as shown in Figure 6.