Product data

ManualsBrandsMifare ManualsAntenna14443A

1. Introduction

This document describes the functionality and electrical specifications of the contactless

reader/writer IC MFRC631.

2. General description

The MFRC631 is a highly integrated transceiver IC for contactless communication at

13.56 MHz.

The MFRC631 transceiver IC supports the following operating modes

• Read/write mode supporting ISO/IEC 14443A/MIFARE

• Read/write mode supporting ISO/IEC 14443B

The MFRC631’s internal transmitter is able to drive a reader/writer antenna designed to

communicate with ISO/IEC 14443A/MIFARE cards and transponders without additional

active circuitry. The digital module manages the complete ISO/IEC 14443A framing and

error detection functionality (parity and CRC).

The MFRC631 supports MIFARE Classic 1K, MIFARE Classic 4K, MIFARE Ultralight,

MIFARE Ultralight C, MIFARE PLUS and MIFARE DESFire products. The MFRC631

supports MIFARE higher transfer speeds of up to 848 kbit/s in both directions.

The MFRC631 supports layer 2 and 3 of the ISO/IEC 14443B reader/writer

communication scheme except anticollision. The anticollision needs to be implemented in

the firmware of the host controller as well as in the upper layers.

The following host interfaces are supported:

• Serial Peripheral Interface (SPI)

• Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)

• I

C-bus interface (two versions are implemented: I2C and I2CL)

The MFRC631 supports the connection of a secure access module (SAM). A dedicated

separate I2C interface is implemented for a connection of the SAM. The SAM can be used

for high secure key storage and acts as a very performant crypto coprocessor. A

dedicated SAM is available for connection to the MFRC631.

3. Features and benefits

 High RF output power frontend IC for transfer speed up to 848 kbit/s

MFRC631

High performance ISO/IEC 14443 A/B reader solution

Rev. 3.3 — 4 February 2014

227433

Product data sheet

COMPANY PUBLIC

Summary of content (120 pages)

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MFRC631 High performance ISO/IEC 14443 A/B reader solution Rev. 3.3 — 4 February 2014 227433 Product data sheet COMPANY PUBLIC 1. Introduction This document describes the functionality and electrical specifications of the contactless reader/writer IC MFRC631. 2. General description The MFRC631 is a highly integrated transceiver IC for contactless communication at 13.56 MHz.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution              Supports ISO/IEC 14443 A/MIFARE, ISO/IEC 14443 B Supports MIFARE Classic encryption in read/write mode Low-Power Card Detection Compliance to “EMV contactless protocol specification V2.0.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 5. Ordering information Table 2. Ordering information Type number MFRC63102HN/TRAYB[1] MFRC63102HN/TRAYBM[2] MFRC63102HN/T/R[3] [1] Package Name Description Version HVQFN32 plastic thermal enhanced very thin quad flat package; no SOT617-1 leads; MSL1, 32 terminals + 1 central ground; body 5  5  0.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 6. Block diagram The analog interface handles the modulation and demodulation of the antenna signals for the contactless interface. The contactless UART manages the protocol dependency of the contactless interface settings managed by the host. The FIFO buffer ensures fast and convenient data transfer between host and the contactless UART. The register bank contains the settings for the analog and digital functionality.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 7.1 Pin description Table 3. Pin description Pin Symbol Type Description 1 TDO O test data output for boundary scan interface 2 TDI I test data input boundary scan interface 3 TMS I test mode select boundary scan interface 4 TCK I test clock boundary scan interface 5 SIGIN I Contactless communication interface output. 6 SIGOUT O Contactless communication interface input.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.1 Interrupt controller The interrupt controller handles the enabling/disabling of interrupt requests. All of the interrupts can be configured by firmware. Additionally, the firmware has possibilities to trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0 and IRQ1 are implemented, accompanied by two 8-bit interrupt enable registers IRQ0En and IRQ1En.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 4.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.2 Timer module Timer module overview The MFRC631 implements five timers. Four timers -Timer0 to Timer3 - have an input clock that can be configured by register T(x)Control to be 13.56 MHz, 212 kHz, (derived from the 27.12 MHz quartz) or to be the underflow event of the fifth Timer (Timer4). Each timer implements a counter register which is 16 bit wide.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.2.1 Timer modes 8.2.1.1 Time-Out- and Watch-Dog-Counter Having configured the timer by setting register T(x)ReloadValue and starting the counting of Timer(x) by setting bit TControl.T(x)StartStop and TControl.T(x)Running, the timer unit decrements the T(x)CounterValue Register beginning with the configured start event. If the configured stop event occurs before the Timer(x) underflows (e.g.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.3 Contactless interface unit The contactless interface unit of the MFRC631 supports the following read/write operating modes: • ISO/IEC14443A/MIFARE • ISO/IEC14443B BATTERY/POWER SUPPLY READER IC ISO/IEC 14443 A CARD MICROCONTROLLER reader/writer Fig 4.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 5. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer Communication direction Signal type Reader to card (send data from the MFRC631 to a card) fc = 13.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.3.2 ISO/IEC14443B functionality The physical level of the communication is shown in Figure 7. (1) ISO/IEC 14443 B READER ISO/IEC 14443 B CARD (2) 001aal997 (1) Reader to Card NRZ, Miller coded, transfer speed 106 kbit/s to 848 kbit/s (2) Card to reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106 kbit/s to 848 kbit/s Fig 7.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.4 Host interfaces 8.4.1 Host interface configuration The MFRC631 supports direct interfacing of various hosts as the SPI, I2C, I2CL and serial UART interface type. The MFRC631 resets its interface and checks the current host interface type automatically having performed a power-up or resuming from power down.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.4.2.2 Read data To read out data from the MFRC631 by using the SPI compatible interface the following byte order has to be used. The first byte that is sent defines the mode (LSB bit) and the address. Table 8. Byte Order for MOSI and MISO byte 0 byte 1 byte 2 byte 3 to n-1 byte n byte n+1 MOSI address 0 address 1 MISO X data 0 address 2 …….. address n 00h data 1 ……..
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 11.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 12. Settings of BR_T0 and BR_T1 BR_T0 0 1 2 3 4 5 6 7 factor BR_T0 1 1 2 4 8 16 32 64 range BR_T1 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 Table 13. Selectable transfer speeds Transfer speed (kbit/s) Serial SpeedReg Transfer speed accuracy (%) (Hex.) 7.2 FA 0.25 9.6 EB 0.32 14.4 DA 0.25 19.2 CB 0.32 38.4 AB 0.32 57.6 9A 0.25 115.2 7A 0.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution ADDRESS RX Sa A0 A1 A2 A3 A4 A5 A6 RD/ NWR So DATA TX Sa D0 D1 D2 D3 D4 D5 D6 D7 So 001aam298 Fig 11. Timing Diagram for UART Read Data Write data: To write data to the MFRC631 using the UART interface the following sequence has to be used. The first send byte defines both, the mode itself and the address. Table 16.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.4.4 I2C-bus interface 8.4.4.1 General An Inter IC (I2C) bus interface is supported to enable a low cost, low pin count serial bus interface to the host. The implemented I2C interface is mainly implemented according the NXP Semiconductors I2C interface specification, rev. 3.0, June 2007. The MFRC631 can act as a slave receiver or slave transmitter in standard mode, fast mode and fast mode plus.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution SDA SCL data line stable; data valid change of data allowed 001aam300 Fig 14. Bit transfer on the I2C-bus. 8.4.4.3 I2C START and STOP conditions To handle the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions are defined. A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is HIGH.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.4.4.5 I2C Acknowledge An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Alternatively the I2C address can be configured in the EEPROM. Several address numbers are reserved for this purpose. During device configuration, the designer has to ensure, that no collision with these reserved addresses in the system is possible. Check the corresponding I2C specification for a complete list of reserved addresses.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution In order to support a fast FIFO data transfer, the address pointer is not incremented automatically in case the address is pointing to the FIFO. The read/write bit shall be set to logic 1. Write Cycle I2C slave address A7-A0 SA 0 (W) Ack CLRC663 register address A6-A0 0 [0..n] Ack DATA [7..
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution The pull-up resistor is not required for the I2CL interface. Instead, a on chip buskeeper is implemented in the MFRC631 for SDA of the I2CL interface. This protocol is intended to be used for a point to point connection of devices over a short distance and does not support a bus capability.The driver of the pin must force the line to the desired logic voltage.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution T=1 μC SAM AV2.6 I2C READER IC I2C Reader aaa-002963 Fig 20. I2C interface enables convenient MIFARE SAM integration 8.4.5.2 SAM connection The MFRC631 provides an interface to connect a SAM dedicated to the MFRC631. Both interface options of the MFRC631, I2C or I2CL can be used for this purpose. The interface option of the SAM itself is configured by a host command sent from the host to the SAM.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.4.6.1 Interface signals The boundary scan interface implements a four line interface between the chip and the environment. There are three Inputs: Test Clock (TCK); Test Mode Select (TMS); Test Data Input (TDI) and one output Test Data Output (TDO). TCK and TMS are broadcast signals, TDI to TDO generate a serial line called Scan path.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. 8.4.6.6 Data register According to the IEEE1149.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 19. Boundary scan path of the MFRC631 Number (decimal) Cell Port Function 13 BC_1 - Control 12 BC_8 IF0 Bidir 11 BC_1 - Control 10 BC_8 IF1 Bidir 9 BC_1 - Control 8 BC_8 IF2 Bidir 7 BC_1 IF2 Output2 6 BC_4 IF3 Bidir 5 BC_1 - Control 4 BC_8 IRQ Bidir 3 BC_1 - Control 2 BC_8 SIGIN Bidir 1 BC_1 - Control 0 BC_8 SIGOUT Bidir Refer to the MFRC631 BSDL file. 8.4.6.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.4.6.10 Non-IEEE1149.1 commands Interface on/off: With this command the host/SAM interface can be deactivated and the Read and Write command of the boundary scan interface is activated. (Data = 1). With Update-DR the value is taken over. Register Access Read: At Capture-DR the actual address is read and stored in the DR. Shifting the DR is shifting in a new address.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.5 Buffer 8.5.1 Overview An 512  8-bit FIFO buffer is implemented in the MFRC631. It buffers the input and output data stream between the host and the internal state machine of the MFRC631. Thus, it is possible to handle data streams with lengths of up to 512 bytes without taking timing constraints into account. The FIFO can also be limited to a size of 255 byte. In this case all the parameters (FIFO length, Watermark...
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution The bit HiAlert is set to logic 1 if maximum water level bytes (as set in register WaterLevel) or less can be stored in the FIFO-buffer. It is generated according to the following equation: HiAlert =  FiFoSize – FiFoLength   WaterLevel (2) The bit LoAlert is set to logic 1 if water level bytes (as set in register WaterLevel) or less are actually stored in the FIFO-buffer.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.6 Analog interface and contactless UART 8.6.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kbit/s. An external circuit can be connected to the communication interface pins SIGIN and SIGOUT to modulate and demodulate the data.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution The registers Section 9.8 and Section 9.10 control the data rate, the framing during transmission and the setting of the antenna driver to support the requirements at the different specified modes and transfer speeds. Table 20.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 21. Setting residual carrier …continuedand modulation index by set_residual_carrier (decimal) residual carrier [%] modulation index [%] 23 65 21.2 24 60 25.0 25 55 29.0 26 50 33.3 27 45 37.9 28 40 42.9 29 35 48.1 30 30 53.8 31 25 60.0 Note: At VDD(TVDD) <5 V and residual carrier settings <50%, the accuracy of the modulation index may be low in dependency of the antenna tuning impedance 8.6.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 7.0 (V) 5.0 3.0 1.0 -1.0 0 1 2 3 4 5 time (μs) 001aan357 Fig 24. Example 2: overshoot_t1 = 0d; overhoot_t2 = 5d 8.6.2.2 Bit generator The default coding of a data stream is done by using the Bit-Generator. It is activated when the value of TxFrameCon.DCodeType is set to 0000 (bin). The Bit-Generator encodes the data stream byte-wise and can apply the following encoding steps to each data byte. 1.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.6.3.2 Block diagram Figure 25 shows the block diagram of the receiver circuitry. The receiving process includes several steps. First the quadrature demodulation of the carrier signal of 13.56 MHz is done. Several tuning steps in this circuit are possible. fully/quasi-differential rcv_hpcf<1:0> rcv_gain<1:0> rx_p mixer rx_n mix_out_i_p out_i_p mix_out_i_n out_i_n 2-stage BBA I-clks rx_p rx_n clk_27 MHz DATA 13.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution During low power card detection the DC levels at the I- and Q-channel mixer outputs are evaluated. This requires that mixers are directly connected to the ADC. This can be configured by setting the bit Rx_ADCmode in register Rcv (38h). 8.6.4 Active antenna concept Two main blocks are implemented in the MFRC631.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution However, the most important use of SIGIN/SIGOUT pins is the active antenna concept. An external active antenna circuit can be connected to the digital circuit of the MFRC631. SigOutSel has to be configured in that way that the signal of the internal Miller Coder is sent to SIGOUT pin (SigOutSel = 4). SigInSel has to be configured to receive Manchester signal with sub-carrier from SIGIN pin (SigInSel = 1).
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.6.5 Symbol generator The symbol generator is used to create various protocol symbols. These can be e.g. SOF or EOF symbols as they are used by the ISO14443 protocols or proprietary protocol symbols. Symbols are defined by means of the symbol definition registers and the mode registers. Four different symbols can be used.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.7.2 EEPROM memory organization The MFRC631 has implemented a EEPROM non-volatile memory with a size of 8 kB.The EEPROM is organized in pages of 64 bytes. One page of 64 bytes can be programmed at a time. Defined purposes had been assigned to specific memory areas of the EEPROM, which are called Sections. Five sections 0..4 with different purpose do exist. Table 25.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.7.2.1 Product information and configuration - Page 0 The first EEPROM page includes production data as well as configuration information. Table 26. Production area (Page 0) Address (Hex.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 29. Interface byte Bit access rights 7 6 5 4 3 2 I2C_HSP - - I2C_Address Boundary Scan Host r/w RFU RFU r/w r/w Table 30.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.7.3 EEPROM initialization content LoadProtocol The MFRC631 EEPROM is initialized at production with values which are used to reset certain registers of the MFRC631 to default settings by copying the EEprom content to the registers. Only registers or bits with “read/write” or “dynamic” access rights are initialized with this default values copied from the EEProm.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 33. Register reset values (Hex.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.8 Clock generation 8.8.1 Crystal oscillator The clock applied to the MFRC631 acts as time basis for generation of the carrier sent out at TX and for the quadrature mixer I and Q clock generation as well as for the coder and decoder of the synchronous system. Therefore stability of the clock frequency is an important factor for proper performance. To obtain highest performance, clock jitter has to be as small as possible.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution fout = 13.56 MHz  PLLDiv_FB /PLLDiv_Out Table 35. Divider values for selected frequencies using the integerN PLL Frequency [MHz] 4 6 8 10 12 20 24 1.8432 3.6864 PLLDiv_FB 23 27 23 28 23 28 23 28 28 PLLDiv_Out 78 61 39 38 26 19 16 206 103 accuracy [%] 0.04 0.03 0.04 0.08 0.04 0.08 0.04 0.01 0.01 8.8.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.9 Power management 8.9.1 Supply concept The MFRC631 is supplied by VDD (Supply Voltage), PVDD (Pad Supply) and TVDD (Transmitter Power Supply). These three voltages are independent from each other. To connect the MFRC631 to a Microcontroller supplied by 3.3 V, PVDD and VDD shall be at a level of 3.3 V, TVDD can be in a range from 3.3 V to 5.0 V. A higher supply voltage at TVDD will result in a higher field strength.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution To leave the modem off mode clears the ModemOff bit in the register Control. 8.9.3 Low-Power Card Detection (LPCD) The low-power card detection is an energy saving mode in which the MFRC631 is not fully powered permanently. The LPCD works in two phases. First the standby phase is controlled by the wake-up counter (WUC), which defines the duration of the standby of the MFRC631. Second phase is the detection-phase.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.10 Command set 8.10.1 General The behavior is determined by a state machine capable to perform a certain set of commands. By writing the according command-code to register Command the command is executed. Arguments and/or data necessary to process a command, are exchanged via the FIFO buffer. • A data transmission of the TxEncoder can be started by a command.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 36. Command set …continued Command No.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution This command does not terminate automatically, when the card does not answer, therefore the timer should be initialized to automatic mode. In this case, beside the bit IdleIRq the bit TimerIRq can be used as termination criteria. During authentication processing the bits RxIRq and TxIRq are blocked. The Crypto1On shows if the authentication was successful.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution The content of the FIFO is transmitted immediately after starting the command. Before transmitting the FIFO content all relevant register have to be set to transmit data. This command terminates automatically when the FIFO gets empty. It can be terminated by any other command written to the command register. 8.10.3.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Reads out the EEPROM Register Set Protocol Area and overwrites the content of the Rxand Tx- related registers. These registers are important for a Protocol selection. Abort condition: Insufficient parameter in FIFO Table 37.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Stores MIFARE Keys into the EEPROM. The key number parameter indicates the first key (n) in the MKA that will be written. If more than one MIFARE Key is available in the FIFO then the next key (n+1) will be written until the FIFO is empty. If an incomplete key (less than 6 bytes) is written into the FIFO, this key will be ignored and will remain in the FIFO.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9. MFRC631 registers 9.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle, bits with same behavior are grouped in common registers. The access conditions are described in Table 39. Table 39. Behavior of register bits and their designation Abbreviation Behavior Table 40.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 40.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 40.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.2 Command configuration 9.2.1 Command Starts and stops command execution. Table 41. Command register (address 00h) Bit 7 6 5 Symbol Standby Modem Off RFU 4 3 Command 2 Access rights dy r/w - dy 1 0 Table 42. Command bits Bit Symbol Description 7 Standby Set to 1, the IC is entering power-down mode. 6 ModemOff Set to logic 1, the receiver and the transmitter circuit is powering down.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.4 FIFO configuration register 9.4.1 FIFOControl FIFOControl defines the characteristics of the FIFO Table 45. FIFOControl register (address 02h); Bit 7 6 5 4 3 2 Symbol FIFOSize HiAlert LoAlert FIFOFlush RFU WaterLevel 1 FIFOLength 0 Access rights r/w r r w - r/w r Table 46.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 48. WaterLevel bits Bit Symbol Description 7 to 0 WaterLevel Sets a level to indicate a FIFO-buffer state which can be read from bits HighAlert and LowAlert in the FifoControl. In 512-byte FIFO mode, the register is extended by bit WaterLevel in the FIFOControl.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.4.3 FIFOLength Number of bytes in the FIFO buffer. In 512-byte mode this register is extended by FIFOControl.FifoLength. Table 49. FIFOLength register (address 04h); reset value: 00h Bit 7 6 5 4 3 Symbol FIFOLength Access rights dy Table 50. 2 1 0 FIFOLength bits Bit 7 to 0 Symbol Description FIFOLength Indicates the number of bytes in the FIFO buffer.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.5.1 IRQ0 register Interrupt request register 0. Table 53. IRQ0 register (address 06h); reset value: 00h Bit 7 6 5 4 3 2 1 0 Symbol Set Hi AlertIrq Lo AlertIrq IdleIrq TxIrq RxIrq ErrIrq RxSOF Irq Access rights w dy dy dy dy dy dy dy Table 54. IRQ0 bits Bit Symbol 7 Set Description 1: writing a 1 to a bit position 6..0 sets the interrupt request 0: Writing a 1 to a bit position 6..
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 56. IRQ1 bits Bit Symbol 7 Set Description 1: writing a 1 to a bit position 5..0 sets the interrupt request 0: Writing a 1 to a bit position 5..0 clears the interrupt request 6 GlobalIrq Set, if an enabled Irq occurs. 5 LPCD_Irq Set if a card is detected in Low-power card detection sequence. 4 Timer4Irq Set to logic 1 when Timer4 has an underflow. 3 Timer3Irq Set to logic 1 when Timer3 has an underflow.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 59. Bit IRQ1EN register (address 09h); 7 6 5 4 3 2 1 Symbol IrqPushPull IrqPinEn LPCD_IrqEn Timer4IrqEn Timer3IrqEn Timer2IrqE n Access rights r/w r/w r/w r/w r/w r/w Table 60.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 62. Error bits Bit Symbol Description 7 EE_Err An error appeared during the last EEPROM command. For details see the descriptions of the EEPROM commands 6 FIFOWrErr Data was written into the FIFO, during a transmission of a possible CRC, during "RxWait", "Wait for data" or "Receiving" state, or during an authentication command. The Flag is cleared when a new CL command is started.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 63. Status register (address 0Bh) Bit 7 6 5 4 3 Symbol - - Crypto1On - - ComState Access rights RFU RFU dy RFU RFU r Table 64. Bit 2 1 0 Status bits Symbol Description 7 to 6 - RFU 5 Crypto1On Indicates if the MIFARE Crypto is on. Clearing this bit is switching the MIFARE Crypto off. The bit can only be set by the MFAuthent command.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 66. RxBitCtrl bits Bit Symbol Description 6 to 4 RxAlign Used for reception of bit oriented frames: RxAlign defines the bit position length for the first bit received to be stored. Further received bits are stored at the following bit positions. Example: RxAlign = 0h - the LSB of the received bit is stored at bit 0, the second received bit is stored at bit position 1.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.6.4 RxColl Receiver collision register. Table 67. RxColl register (address 0Dh); Bit 7 6 5 4 3 2 Symbol CollPosValid CollPos Access rights r r Table 68. 1 0 RxColl bits Bit Symbol Description 7 CollPos Valid If set to 1, the value of CollPos is valid. Otherwise no collision is detected or the position of the collision is out of the range of bits CollPos.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.7 Timer configuration registers 9.7.1 TControl Control register of the timer section. The TControl implements a special functionality to avoid the not intended modification of bits. Bit 3..0 indicates, which bits in the positions 7..4 are intended to be modified. Example: writing FFh sets all bits 7..4, writing F0h does not change any of the bits 7..4 Table 69.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 72. T0Control bits Bit Symbol Description 7 T0StopRx If set, the timer stops immediately after receiving the first 4 bits. If cleared the timer does not stop automatically. Note: If LFO Trimming is selected by T0Start, this bit has no effect.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.7.2.3 Table 76. T0ReloadLo bits Bit Symbol Description 7 to0 T0ReloadLo Defines the low byte of the reload value of the timer. With the start event the timer loads the value of the T0ReloadValHi, T0ReloadValLo. Changing this register affects the timer only at the next start event. T0CounterValHi High byte of the counter value of Timer0. Table 77.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 82. T1Control bits Bit Symbol Description 7 T1StopRx If set, the timer stops after receiving the first 4 bits. If cleared, the timer is not stopped automatically. Note: If LFO trimming is selected by T1start, this bit has no effect.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.7.2.8 Table 86. T1ReloadValLo bits Bit Symbol Description 7 to 0 T1ReloadLo Defines the low byte of the reload value of the Timer1. Changing this register affects the timer only at the next start event. T1CounterValHi High byte (MSB) of the counter value of byte Timer1. Table 87. T1CounterValHi register (address 17h) Bit 7 6 5 4 3 Symbol T1CounterValHi Access rights dy 9.7.2.9 2 Table 88.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 92. T2Control bits Bit Symbol Description 7 T2StopRx If set the timer stops immediately after receiving the first 4 bits. If cleared indicates, that the timer is not stopped automatically. Note: If LFO Trimming is selected by T2Start, this bit has no effect. 6 - RFU 5 to 4 T2Start 00b: The timer is not started automatically. 01b: The timer starts automatically at the end of the transmission.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.7.2.13 Table 96. T2ReloadLo bits Bit Symbol Description 7 to 0 T2ReloadLo Defines the low byte of the reload value of the Timer2. With the start event the timer load the value of the T2ReloadValHi and T2RelaodVaLo. Changing this register affects the timer only at the next start event. T2CounterValHi High byte of the counter register of Timer2. Table 97.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 102. T3Control bits Bit Symbol Description 7 T3StopRx If set, the timer stops immediately after receiving the first 4 bits. If cleared, indicates that the timer is not stopped automatically. Note: If LFO Trimming is selected by T3Start, this bit has no effect.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 106. T3ReloadLo bits 9.7.2.18 Bit Symbol Description 7 to 0 T3ReloadLo Defines the low byte of the reload value of Timer3. With the start event the timer load the value of the T3ReloadValHi and T3RelaodValLo. Changing this register affects the timer only at the next start event. T3CounterValHi High byte of the current counter value the 16-bit Timer3. Table 107.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 112. T4Control bits 9.7.2.21 Bit Symbol Description 7 T4Running Shows if the timer T4 is running. If the bit T4StartStopNow is set, this bit and the timer T4 can be started/stopped. 6 T4Start StopNow if set, the bit T4Running can be changed. 5 T4AutoTrimm If set to one, the timer activates an LFO trimming procedure when it underflows.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 115. T4ReloadLo register (address 25h) Bit 7 6 5 4 3 Symbol T4ReloadLo Access rights r/w 2 1 0 Table 116. T4ReloadLo bits 9.7.2.23 Bit Symbol Description 7 to 0 T4ReloadLo Defines the low byte of the reload value of the timer 4. With the start event the timer loads the value of the T4ReloadVal. Changing this register affects the timer only at the next start event.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 122. DrvMode bits Bit Symbol Description 7 Tx2Inv Inverts transmitter 2 at TX2 pin 6 Tx1Inv Inverts transmitter 1 at TX1 pin 5 RFU 4 - RFU 3 TxEn If set to 1 both transmitter pins are enabled 2 to 0 TxClkMode Transmitter clock settings (see 8.6.2. Table 27). Codes 011b and 0b110 are not supported.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 126. TxCon bits Bit Symbol Description 7 to 4 OvershootT2 Specifies the length (number of carrier clocks) of the additional modulation for overshoot prevention. Refer to Section 8.6.2.1 “Overshoot protection” 3 Cwmax Set amplitude of continuous wave carrier to the maximum. If set, set_cw_amplitude in Register TxAmp has no influence on the continuous amplitude.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 130. TxCrcPreset bits Bit Symbol Description 7 RFU - 6 to 4 TXPresetVal Specifies the CRC preset value for transmission (see Table 131).
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 133. RxCrcCon bits Bit Symbol Description 3 to 2 RxCRCtype Defines which type of CRC (CRC8/CRC16/CRC5) is calculated: • • • • 00h -- CRC5 01h -- CRC8 02h -- CRC16 03h -- RFU 1 RxCrcInvert If set, the CRC check is done for the inverted CRC. 0 RxCrcEn If set, the CRC is checked and in case of a wrong CRC an error flag is set. Otherwise the CRC is calculated but the error flag is not modified. Table 134.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.10.2 TxDATAModWidth Transmitter data modulation width register Table 137. TxDataModWidth register (address 2Fh) Bit 7 6 5 4 3 Symbol DModWidth Access rights r/w 2 1 0 Table 138. TxDataModWidth bits Bit Symbol Description 7 to 0 DModWidth Specifies the length of a pulse for sending data with enabled pulse modulation. The length is given by the number of carrier clocks + 1.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.10.3 TxSym10BurstLen If a protocol requires a burst (an unmodulated subcarrier) the length can be defined with this TxSymBurstLen, the value high or low can be defined by TxSym10BurstCtrl. Table 139. TxSym10BurstLen register (address 30h) Bit 7 6 5 4 3 2 1 0 Symbol RFU Sym1Burst Len RFU Sym0Burst Len Access rights - r/w - r/w Table 140.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 142. TXWaitCtrl bits Bit Symbol Description 7 TxWaitStart If cleared, the TxWait time is starting at the End of the send data (TX). If set, the TxWait time is starting at the End of the received data (RX). 6 If cleared, the TxWait time is TxWait  16/13.56 MHz. TxWaitEtu If set, the TxWait time is TxWait  0.5 / DBFreq (DBFreq is the frequency of the bit stream as defined by TxDataCon).
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.10.5 TxWaitLo Table 143. TxWaitLo register (address 32h) Bit 7 6 5 4 3 Symbol TxWaitLo Access rights r/w 2 1 0 Table 144. TxWaitLo bits Bit Symbol Description 7 to 0 TxWaitLo Defines the minimum time between receive and send or between two send data streams Note: TxWait is a 11bit register (additional 3 bits are in the TxWaitCtrl register)! See also TxWaitEtu and TxWaitStart. 9.11 FrameCon Table 145.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.12 Receiver configuration registers 9.12.1 RxSofD Table 147. RxSofD register (address 34h) Bit 7 6 5 4 3 2 1 0 Symbol RFU SOF_En SOFDetected RFU SubC_En SubC_Detected SubC_Present Access rights - r/w dy - r/w dy r Table 148. RxSofD bits Bit Symbol Description 7 to 6 RFU - 5 SOF_En If set and a SOF is detected an RxSOFIrq is raised. 4 SOF_Detected Shows that a SOF is or was detected.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 150. RxCtrl bits Bit Symbol Description 4 EGT_Check If set to 1, the EGT is checked and if it is too long a protocol error is set. (This is only valid for ISO/IEC14443 Type B). 3 EMD_Sup Enables the EMD suppression according ISO/IEC14443. If an error occurs within the first three bytes, these three bytes are assumed to be EMD, ignored and the FIFO is reset.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.12.5 Rcv Table 155. Rcv register (address 38h) Bit 7 6 5 4 3 2 1 0 Symbol Rcv_Rx_single Rx_ADCmode SigInSel RFU CollLevel Access rights r/w r/w r/w - r/w Table 156.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 159. Effect of gain and highpass corner register settings rcv_gain (Hex.) rcv_hpcf (Hex.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 162. RS232 speed settings Transfer speed (kbit/s) 7,2 SerialSpeed register content (Hex.) FA 9,6 EB 14,4 DA 19,2 CB 38,4 AB 57,6 9A 115,2 7A 128,0 74 230,4 5A 460,8 3A 921,6 1C 1228,8 15 9.13.2 LFO_Trimm Table 163. LFO_Trim register (address 3Ch) Bit 7 6 5 4 3 Symbol LFO_trimm Access rights r/w 2 1 0 Table 164. LFO_Trim bits Bit Symbol Description 7 to 0 LFO_trimm Trimm value.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 166. PLL_Ctrl register bits Bit Symbol Description 7 to 4 CLkOutSel • • • • • • • • • • • • • 0h - pin CLKOUT is used as I/O 1h - pin CLKOUT shows the output of the analog PLL 2h - pin CLKOUT is hold on 0 3h - pin CLKOUT is hold on 1 4h - pin CLKOUT shows 27.12 MHz from the crystal 5h - pin CLKOUT shows 13.56 MHz derived from the crystal 6h - pin CLKOUT shows 6.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 170. Setting for the output divider ratio PLLDiv_Out [7:0] Value Division 5 RFU 6 RFU 7 RFU 8 8 9 9 10 10 ... ... 253 253 254 254 9.14 Low-power card detection configuration registers The LPCD registers contain the settings for the low-power card detection. The setting for LPCD_IMax (6 bits) is done by the two highest bits (bit 7, bit 6) of the registers LPCD_QMin, LPCD_QMax and LPCD_IMin each. 9.14.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 174. LPCD_QMax bits Bit Symbol Description 7 LPCD_IMax.3 Defines the bit 3 of the high border for the LPCD. If the measurement value of the I channel is higher than LPCD IMax, a LPCD IRQ is raised. 6 LPCD_IMax.2 Defines the bit 2 of the high border for the LPCD. If the measurement value of the I channel is higher than LPCD IMax, a LPCD IRQ is raised. 5 to 0 LPCD_QMax Defines the high border for the LPCD.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 180. LPCD_Q_Result bits Bit Symbol Description 7 RFU - 6 LPCD_Irq_Clr If set no LPCD IRQ is raised any more until the next low-power card detection procedure. Can be used by software to clear the interrupt source. 5 to 0 LPCD_Result_Q Shows the result of the last ow power card detection (Q-Channel). 9.15 Pin configuration 9.15.1 PinEn Table 181.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 184. PinOut bits Bit Symbol Description 7 SIGIN_OUT Output buffer of the SIGIN pin 6 CLKOUT_OUT Output buffer of the CLKOUT pin 5 IFSEL1_OUT Output buffer of the IFSEL1 pin 4 IFSEL0_OUT Output buffer of the IFSEL0 pin 3 TCK_OUT Output buffer of the TCK pin 2 TMS_OUT Output buffer of the TMS pin 1 TDI_OUT Output buffer of the TDI pin 0 TDO_OUT Output buffer of the TDO pin 9.15.3 PinIn Table 185.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 188. SigOut bits Bit Symbol Description 7 PadSpeed If set, the I/O pins are supporting a fast switching mode.The fast mode for the I/O’s will increase the peak current consumption of the device, especially if multiple I/Os are switching at the same time. The power supply needs to be designed to deliver this peak currents.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 10. Limiting values Table 191. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Conditions Min Max Unit 0.5 +5.5 V VDD(PVDD) PVDD supply voltage 0.5 +5.5 V VDD(TVDD) TVDD supply voltage 0.5 +5.5 V Vi(RXP) input voltage on pin RXP -0.5 +2.0 V Vi(RXN) input voltage on pin RXN 0.5 +2.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 194. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit IOL LOW-level output current VOL = 0.4 V; Standard mode, Fast mode 4 - - mA VOL = 0.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 194. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Pin characteristics AUX 1, AUX 2 Vo output voltage 0 - 1.8 V CL load capacitance - - 400 pF Pin characteristics RXP, RXN Vi input voltage 0 - 1.8 V Ci input capacitance 2 3.5 5 pF Vmod(pp) modulation voltage - 2.5 - mV - - 1.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Vmod Vi(p-p)(max) Vi(p-p)(min) VMID 13.56 MHz carrier 0V 001aak012 Fig 31. Pin RX input voltage 13.1 Timing characteristics Table 195.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Table 196.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 14. Application information A typical application diagram using a complementary antenna connection to the MFRC631 is shown in Figure 33. The antenna tuning and RF part matching is described in the application note Ref. 1 and Ref. 2.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution but will also emit power at higher harmonics. The international EMC regulations define the amplitude of the emitted power in a broad frequency range. Thus, an appropriate filtering of the output signal is necessary to fulfil these regulations. Remark: The PCB layout has a major influence on the overall performance of the filter. 14.1.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 14.1.4 Antenna coil The precise calculation of the antenna coils’ inductance is not practicable but the inductance can be estimated using the following formula. We recommend designing an antenna either with a circular or rectangular shape.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 15. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-1 terminal 1 index area A A1 E c detail X C e1 e 1/2 e b 9 y y1 C v M C A B w M C 16 L 17 8 e e2 Eh 1/2 1 terminal 1 index area e 24 32 25 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Detailed package information can be found at http://www.nxp.com/package/SOT617-1.html. 16. Handling information Moisture Sensitivity Level (MSL) evaluation has been performed according to SNW-FQ-225B rev.04/07/07 (JEDEC J-STD-020C). MSL for this package is level 2 which means 260 C convection reflow temperature. For MSL2: • Dry pack is required. • 1 year out-of-pack floor life at maximum ambient temperature 30 C/ 85 % RH.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 18. Abbreviations Table 197.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 19. References MFRC631 Product data sheet COMPANY PUBLIC [1] Application note — MFRC52x Reader IC Family Directly Matched Antenna Design [2] Application note — MIFARE (ISO/IEC 14443 A) 13.56 MHz RFID Proximity Antennas [3] BSDL File — Boundary scan description language file of the MFRC631 All information provided in this document is subject to legal disclaimers. Rev. 3.3 — 4 February 2014 227433 © NXP B.V. 2014.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 20. Revision history Table 198. Revision history Document ID Release date Data sheet status Change notice Supersedes MFRC631 v.3.3 20140204 Product data sheet - MFRC631 v.3.2 Modifications: MFRC631 v.3.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 23. Contents 1 2 3 4 5 6 7 7.1 8 8.1 8.2 8.2.1 8.2.1.1 8.2.1.2 8.2.1.3 8.2.1.4 8.2.1.5 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.2.1 8.4.2.2 8.4.2.3 8.4.2.4 8.4.2.5 8.4.3 8.4.3.1 8.4.3.2 8.4.4 8.4.4.1 8.4.4.2 8.4.4.3 8.4.4.4 8.4.4.5 8.4.4.6 8.4.4.7 8.4.4.8 8.4.4.9 8.4.5 8.4.5.1 8.4.5.2 8.4.6 8.4.6.1 8.4.6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . .
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 8.10.3.3 Load key command . . . . . . . . . . . . . . . . . . . . 8.10.3.4 MFAuthent command . . . . . . . . . . . . . . . . . . . 8.10.3.5 Receive command . . . . . . . . . . . . . . . . . . . . . 8.10.3.6 Transmit command . . . . . . . . . . . . . . . . . . . . . 8.10.3.7 Transceive command . . . . . . . . . . . . . . . . . . . 8.10.3.8 WriteE2 command . . . . . . . . . . . . . . . . . . . . . 8.10.3.9 WriteE2PAGE command . .
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MFRC631 NXP Semiconductors High performance ISO/IEC 14443 A/B reader solution 9.16 9.16.1 10 11 12 13 13.1 14 14.1 14.1.1 14.1.2 14.1.3 14.1.4 15 16 17 18 19 20 21 21.1 21.2 21.3 21.4 21.5 22 23 Version register. . . . . . . . . . . . . . . . . . . . . . . . 99 Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . 100 Recommended operating conditions. . . . . . 100 Thermal characteristics . . . . . . . . . . . . . . . .