Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLogic ICsLogic IC - Transducer Converter, Bidirectional TSSOP 16

General Description

The MAX13000E–MAX13005E 6-channel level transla-

tors provide the level shifting necessary to allow data

transfer in multivoltage systems. Externally applied volt-

ages, V

and V

, set the logic levels on either side of

the device. Logic signals present on the V

side of the

device appear as higher voltage logic signals on the

side of the device, and vice-versa.

The MAX13000E–MAX13005E feature a low V

and V

quiescent supply current less than 4µA. The

MAX13000E–MAX13005E also have ±15kV ESD protec-

tion on the I/O V

side for greater protection in applica-

tions that route signals externally. The ESD protection is

specified using the Human Body Model (HBM). The

MAX13000E/MAX13001E/MAX13002E operate at a guar-

anteed 230kbps data rate. The MAX13003E/

MAX13004E/MAX13005E operate at a guaranteed

20Mbps data rate when V

> +1.65V.

The MAX13000E/MAX13003E are bidirectional level

translators, allowing data translation in either direction

↔ V

) on any single data line without a DIRECTION

input. The MAX13001E/MAX13002E/MAX13004E/

MAX13005E unidirectional level translators level shift

data in one direction (V

→ V

or V

→ V

) on any

single data line. The MAX13001E/MAX13002E/

MAX13004E/MAX13005E unidirectional translators’

inputs have the capability to interface with both CMOS

and open-drain (OD) outputs. For more information see

the Ordering Information, Selector Guide, and the Input-

Driver Requirements sections.

The MAX13000E–MAX13005E operate with +0.9V to

+3.6V V

voltages and +1.5V to +3.6V V

voltages. The

MAX13000E–MAX13005E are available in 16-bump

UCSP™ and 16-pin TSSOP packages, and are specified

over the extended -40°C to +85°C operating tempera-

ture range.

Applications

CMOS Logic-Level Translation

Open-Drain I/O Translation

OD-to-CMOS Signal Conversion

Low-Voltage ASIC Level Translation

Cell Phones

SPI™ and MICROWIRE

Level Translation

Smart-Card Readers

Portable POS Systems

Portable Communication Devices

Low-Cost Serial Interfaces

Telecommunications Equipment

Features

♦ Guaranteed Data-Rate Options

230kbps (MAX13000E/MAX13001E/MAX13002E)

20Mbps (MAX13003E/MAX13004E/MAX13005E)

♦ Bidirectional Level Translation Without a

DIRECTION Input

♦ Operational Down to +0.9V on V

and +1.5V on V

♦ ±15kV ESD Protection on I/O V

Lines per HBM

♦ Low <4µA Quiescent Current

♦ Enable/Shutdown Control

♦ 2mm x 2mm, 16-Bump UCSP and Lead Packaging

Options

♦ CMOS or Open-Drain Outputs Interface Capability

MAX13000E–MAX13005E

Ultra-Low-Voltage Level Translators

________________________________________________________________ Maxim Integrated Products 1

BOTTOM VIEW

MAX13000E/MAX13003E

4 X 4 UCSP

GND

I/OV

234

I/OV

1 I/OV

I/OV

1 I/OV

5 I/OV

I/OV

EN I/OV

Pin Configurations

19-3692; Rev 1; 5/11

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

UCSP is a trademark of Maxim Integrated Products, Inc.

SPI is a trademark of Motorola, Inc.

MICROWIRE is a registered trademark of National

Semiconductor Corp.

Typical Operating Circuits and Selector Guide appear at end

of data sheet.

+Denotes a lead(Pb)-free/RoHS-compliant package.

Ordering Information

PART TEMP RANGE

PIN-

PACKAGE

MAX13000EEUE+ -40°C to +85°C 16 TSSOP

Pin Configurations continued at end of data sheet.

Ordering Information continued at end of data sheet.

Summary of content (25 pages)

PAGE 1
9-3692; Rev 1; 5/11 Ultra-Low-Voltage Level Translators The MAX13000E–MAX13005E 6-channel level translators provide the level shifting necessary to allow data transfer in multivoltage systems. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as higher voltage logic signals on the VCC side of the device, and vice-versa.
PAGE 2
MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators ABSOLUTE MAXIMUM RATINGS Voltages referenced to GND. VCC ...........................................................................-0.3V to +4V VL ..............................................................................-0.3V to +4V I/OVCC_ .......................................................-0.3V to (VCC + 0.3V) I/OVL_ ............................................................-0.3V to (VL + 0.3V) EN ........................................
PAGE 3
Ultra-Low-Voltage Level Translators (VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 4
MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators ELECTRICAL CHARACTERISTICS (continued) (VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4) PARAMETER SYMBOL Output Source Current During Transient (VCC Side) CONDITIONS MIN TYP VCC = +1.65V, MAX13003E/MAX13004E/MAX13005E 22 VCC = +1.65V, MAX13000E/MAX13001E/MAX13002E 1 VL = +1.2V, VCC = +1.
PAGE 5
Ultra-Low-Voltage Level Translators (VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4) PARAMETER I/OVL_ Rise Time SYMBOL tRVL CONDITIONS tFVL MAX 15 CI/OVL = 15pF, MAX13003E/MAX13004E/MAX13005E, VCC = +1.5V, Figures 2a, 2b 15 300 15 CI/OVL = 15pF, MAX13003E/MAX13004E/MAX13005E, VCC = +1.
PAGE 6
TIMING CHARACTERISTICS (continued) (VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.
PAGE 7
Ultra-Low-Voltage Level Translators VL SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V) 0.1 DATA RATE = 230kbps 0.01 MAX13000E toc05 310 DATA RATE = 20Mbps 1.8 2.1 2.4 2.7 3.0 3.3 DATA RATE = 20Mbps 4.00 3.95 3.85 -40 3.6 4.05 3.90 290 1.5 -15 10 35 60 85 -40 -15 10 35 85 60 TEMPERATURE (°C) TEMPERATURE (°C) VL SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VCC (DRIVING I/OVL, VCC = 3.3V, VL = +0.9V) VCC SUPPLY CURRENT vs.
PAGE 8
Typical Operating Characteristics (continued) (VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.) OD RAIL-TO-RAIL DRIVING (MAX13002E) (DRIVING I/OVL, VCC = +3.3V, VL = +0.9V, CI/OVCC = 56pF, DATA RATE = 230kbps, RPULLUP = 15kΩ) I/OVL_ 500mV/div GND RAIL-TO-RAIL DRIVING (DRIVING I/OVL, VCC = +3.3V, VL = +0.
PAGE 9
Ultra-Low-Voltage Level Translators VOLC (V) 0.20 VCC = +3.3V VCC = +1.8V 0.10 VCC = +3.3V 3.0 VOHC (V) VCC = +2.5V 0.15 3.5 MAX13000Etoc22 0.25 MAX13000Etoc23 VOHC vs. IOHC FOR VCC SIDE VOLC vs. IOLC FOR VCC SIDE VCC = +2.5V 2.5 2.0 VCC = +1.8V 1.5 0.05 1.
PAGE 10
MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators Pin Descriptions (continued) MAX13001E/MAX13004E PIN 10 NAME FUNCTION TSSOP 1 UCSP B1 OVL1 CMOS Output 1, Referenced to VL 2 B2 OVL2 CMOS Output 2, Referenced to VL 3 A1 OVL3 CMOS Output 3, Referenced to VL 4 A2 VL Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF capacitor. 5 A3 EN Enable Input. When EN is pulled low, OVCC1 to OVCC6 and IVL1 to IVL6 are tri-stated. Drive EN high (VL) for normal operation.
PAGE 11
Ultra-Low-Voltage Level Translators MAX13002E/MAX13005E PIN NAME FUNCTION TSSOP 1 UCSP B1 IVL1 Open-Drain-Compatible Input 1, Referenced to VL 2 B2 IVL2 Open-Drain-Compatible Input 2, Referenced to VL 3 A1 IVL3 Open-Drain-Compatible Input 3, Referenced to VL 4 A2 VL Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF capacitor. 5 A3 EN Enable Input. When EN is pulled low, OVCC1 to OVCC6 and IVL1 to IVL6 are tri-stated. Drive EN high (VL) for normal operation.
PAGE 12
MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators Test Circuits/Timing Diagrams I/OVL_ 90% VL VCC 50% MAX13000E 10% EN tRISE/FALL I/OVL-VCC I/OVCC I/OVL_ SOURCE I/OVCC_ 90% RS CI/OVCC 50% 10% tFVCC tRVCC I/OVL-VCC UNUSED I/Os ARE GROUNDED. tRISE/FALL < 3ns (MAX13003E/MAX13004E/MAX13005E) tRISE/FALL < 80ns (MAX13000E/MAX13001E/MAX13002E) Figure 1b. Timing for Driving I/OVL Figure 1a.
PAGE 13
Ultra-Low-Voltage Level Translators VL EN EN SOURCE MAX13000E t'EN-VCC 0 VL I/OVCC I/OVL_ I/OVL_ 0 CI/OVCC VL VCC VCC / 2 I/OVCC_ 0 VL t"EN-VCC EN SOURCE MAX13000E 0 EN I/OVL_ VL I/OVCC_ 0 VCC I/OVCC I/OVL_ CI/OVCC VCC / 2 0 tEN-VCC IS WHICH EVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC. Figure 3.
PAGE 14
MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators Detailed Description The MAX13000E–MAX13005E logic-level translators provide the level shifting necessary to allow data transfer in multivoltage systems. Externally applied voltages, VCC and VL, set the logic levels on each side of the device. Logic signals present on the VL side of the device appear as higher voltage logic signals on the VCC side of the device, and vice-versa.
PAGE 15
Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E VL VCC P ONE-SHOT 5kΩ I/OVL I/OVCC INVERTER 2 INVERTER 1 N ONE-SHOT P ONE-SHOT 5kΩ INVERTER 3 INVERTER 4 N ONE-SHOT Figure 5. Architecture of 20Mbps, CMOS-to-CMOS Bidirectional Translators where, CP is the parasitic capacitance of the traces, V is the supply voltage of the driven side (i.e., VL or VCC), and CIN is the input capacitance of the driven side (CIN = 10pF for VL side, CIN = 20pF for VCC side).
PAGE 16
MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators 20Mbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR VCC/VL VL/VCC P ONE-SHOT 5kΩ IVCC/IVL OVL/OVCC INVERTER 2 OPEN-DRAIN COMPATIBLE INPUT INVERTER 1 CMOSCOMPATIBLE INPUT N ONE-SHOT P ONE-SHOT INVERTER 3 5kΩ 75kΩ INVERTER 4 N ONE-SHOT Figure 6.
PAGE 17
Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E 230kbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR VCC/VL VL/VCC 5kΩ IVCC/IVL OVL/OVCC INVERTER 1 OPEN-DRAIN COMPATIBLE INPUT INVERTER 2 CMOSCOMPATIBLE INPUT INVERTER 3 5kΩ 75kΩ INVERTER 4 5kΩ N ONE-SHOT Figure 8. Architecture of 230kbps, OD-to-CMOS Unidirectional Translator structures withstand high ESD in all states: normal operation, tri-state output mode, and power-down.
PAGE 18
MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators RC 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RC 50Ω TO 100Ω RD 1500Ω DISCHARGE RESISTANCE CHARGE-CURRENTLIMIT RESISTOR DEVICE UNDER TEST STORAGE CAPACITOR HIGHVOLTAGE DC SOURCE Cs 150pF RD 330Ω DISCHARGE RESISTANCE DEVICE UNDER TEST STORAGE CAPACITOR Figure 10. Human Body ESD Test Model Figure 12.
PAGE 19
Ultra-Low-Voltage Level Translators VL VCC EN MAX13000E–MAX13005E I/OVL1 I/OVCC1 I/OVL2 I/OVCC2 I/OVL3 I/OVCC3 I/OVL4 I/OVCC4 I/OVL5 I/OVCC5 I/OVL6 I/OVCC6 GND ______________________________________________________________________________________ 19 MAX13000E–MAX13005E Functional Diagram
PAGE 20
Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E Typical Operating Circuits +0.9V +2.8V 0.1μF 1μF VCC VL +0.9V SYSTEM CONTROLLER +2.8V SYSTEM MAX13001E DATA1 DATA2 EN MAX13004E OVL_1 IVCC_1 OVL_2 IVCC_2 DATA3 OVL_3 IVCC_3 DATA3 DATA4 OVL_4 IVCC_4 DATA4 DATA5 OVL_5 IVCC_5 DATA5 DATA6 OVL_6 IVCC_6 DATA6 DATA1 DATA2 GND +0.9V +2.8V 0.1μF 1μF VCC VL +0.9V SYSTEM CONTROLLER +2.
PAGE 21
Ultra-Low-Voltage Level Translators +0.9V +2.8V 0.1μF 1μF VL +0.9V SYSTEM CONTROLLER VCC +2.
PAGE 22
Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E Pin Configurations (continued) BOTTOM VIEW MAX13001E/MAX13004E IVCC3 VCC GND MAX13002E/MAX13005E IVCC4 D OVCC3 VCC GND OVCC4 OVCC1 OVCC2 OVCC5 OVCC6 IVL1 IVL2 IVL5 IVL6 IVL3 VL EN IVL4 2 3 4 D IVCC1 IVCC2 IVCC5 IVCC6 C C OVL1 OVL2 OVL5 OVL6 B B OVL3 VL EN OVL4 A A 1 2 3 4 1 4 X 4 UCSP 4 X 4 UCSP TOP VIEW I/OVL1 1 16 I/OVCC1 OVL1 1 16 IVCC1 IVL1 1 16 OVCC1 I/OVL2 2 15 I/OVCC2 OVL2 2 15 IVCC2 IVL
PAGE 23
Ultra-Low-Voltage Level Translators PART TEMP RANGE PINPACKAGE MAX13000EEBE+T* -40°C to +85°C 16 UCSP (4mm × 4mm) MAX13001EEUE+ -40°C to +85°C 16 TSSOP MAX13001EEBE+T* -40°C to +85°C 16 UCSP (4mm × 4mm) MAX13002EEUE+ -40°C to +85°C 16 TSSOP MAX13002EEBE+T* -40°C to +85°C 16 UCSP (4mm × 4mm) MAX13003EEUE+ -40°C to +85°C 16 TSSOP MAX13003EEBE+T* -40°C to +85°C 16 UCSP (4mm × 4mm) MAX13004EEUE+ -40°C to +85°C 16 TSSOP MAX13004EEBE+T* -40°C to +85°C 16 UCSP (4mm × 4mm) MAX13005EEU
PAGE 24
MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 24 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
PAGE 25
Ultra-Low-Voltage Level Translators REVISION NUMBER REVISION DATE 0 6/05 Initial release 1 5/11 Added lead-free information to the Ordering Information DESCRIPTION PAGES CHANGED — 1, 23 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.