DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS33R11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over a T1/E1/J1 data stream. 10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control The device performs store-and-forward of packets with full wire-speed transport capability.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver TABLE OF CONTENTS 1 DESCRIPTION ................................................................................................................................... 9 2 FEATURE HIGHLIGHTS.................................................................................................................. 11 2.1 GENERAL ...................................................................................................................................
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.14.1 DTE and DCE Mode .............................................................................................................................58 9.15 ETHERNET MAC ........................................................................................................................... 59 9.15.1 MII Mode Options..................................................................................................................................
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.17.4 FIFO Information ...................................................................................................................................96 10.17.5 Receive Packet-Bytes Available ...........................................................................................................96 10.18 LEGACY FDL SUPPORT (T1 MODE) ............................................................................................... 97 10.18.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 12.4 E1 MODE .................................................................................................................................... 308 13 OPERATING PARAMETERS ........................................................................................................ 313 13.1 THERMAL CHARACTERISTICS ....................................................................................................... 314 13.2 MII INTERFACE............
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver LIST OF FIGURES Figure 3-1. Ethernet-to-WAN Extension (With or Without Framing) ......................................................................... 17 Figure 6-1. Main Block Diagram ................................................................................................................................ 20 Figure 6-2. Block Diagram of T1/E1/J1 Transceiver ................................................................................
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 12-19. Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)................................................ 307 Figure 12-20. Receive-Side Timing ......................................................................................................................... 308 Figure 12-21. Receive-Side Boundary Timing (with Elastic Store Disabled) .......................................................... 308 Figure 12-22.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications ...................................................................................... 16 Table 7-1. Detailed Pin Descriptions ......................................................................................................................... 25 Table 9-1. Clocking Options for the Ethernet Interface ........................................................................
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 1 DESCRIPTION The DS33R11 provides interconnection and mapping functionality between Ethernet Packet Systems and T1/E1/J1 WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, Packet Arbiter, Committed Information Rate Controller (CIR), HDLC/X.86 (LAPS) Mapper, SDRAM interface, control ports, Bit Error Rate Tester (BERT), and integrated T1/E1/J1 Transceiver.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver The integrated Ethernet Mapper is software compatible with the DS33Z11 Ethernet mapper. There are a few things to note when porting a DS33Z11 application to this device: • The SPI and hardware modes are not supported. • RSER has been renamed to RSERI. • RCLK has been renamed to RCLKI. • TSER has been renamed to TSERO. • TCLK has been renamed to TCLKE.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2 2.1 FEATURE HIGHLIGHTS General • • • • • • • 2.2 Microprocessor Interface • • • • • • 2.3 Parallel control port with 8-bit data bus Nonmultiplexed Intel and Motorola timing modes Internal software reset and external hardware reset-input pin Supports polled or interrupt-driven environments Software access to device ID and silicon revision Global interrupt-output pin HDLC Ethernet Mapping • • • • • • • • • • 2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2.5 Additional HDLC Controllers in the Integrated T1/E1/J1 Transceiver • • • • • • • • 2.6 Committed Information Rate (CIR) Controller • • • 2.7 CIR Rate controller limits transmission of data from the Ethernet interface to the serial interface CIR granularity at 512kbit/s CIR averaging for smoothing traffic peaks SDRAM Interface • • • • • • 2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2.9 T1/E1/J1 Line Interface • • • • • • • • • • • • • • • • • • • • • • • Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation Fully software configurable Short-haul and long-haul applications Automatic receive sensitivity adjustments Ranges include 0 to 43dB or 0 to 12dB for E1 applications and 0 to 13dB or 0 to 36dB for T1 applications Receive level indication in 2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2.14 Test and Diagnostics • • • • • • • • • • • • • IEEE 1149.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 2.15 Specifications Compliance The DS33R11 meets relevant telecommunications specifications. The following table provides the specifications and relevant sections that are applicable to the DS33R11. Table 2-1. T1-Related Telecommunications Specifications IEEE 802.3-2002—CSMA/CD access method and physical layer specifications. RFC1662—PPP in HDLC-like Framing RFC2615—PPP over SONET/SDH X.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 3 APPLICATIONS The DS33R11 is ideal for application areas such as transparent LAN service, LAN extension, and Ethernet delivery over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4. For an example of a complete LAN-to-WAN design, refer to Application Note 3411: DS33Z11—Ethernet LAN to Unframed T1/E1 WAN Bridge, available on our website at www.maxim-ic.com/telecom. Figure 3-1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 4 ACRONYMS AND GLOSSARY • • • • • • • • • BERT: Bit Error-Rate Tester DCE: Data Communication Interface DTE: Data Terminating Interface FCS: Frame Check Sequence HDLC: High-Level Data Link Control MAC: Media Access Control MII: Media Independent Interface RMII: Reduced Media Independent Interface WAN: Wide Area Network Note 1: Previous versions of this document used the term “Subscriber” to refer to the Ethernet Interface function.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 5 MAJOR OPERATING MODES Microprocessor control is possible through the 8-bit parallel control port and provides configuration for all the features of the device. The Ethernet Link Transport Engine in the device can be configured for HDLC or X.86 encapsulation. The integrated transceiver can be software configured for T1, E1, or J1 operation.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 6 BLOCK DIAGRAMS CST CS A0-A9 D0-D7 WR RD INT TSERO TCLKE TDEN TCHBLK TCHCLK TCLKT TSERI MCLK TDCLKI TDCLKO TPOSI TPOSO TNEGI TNEGO Figure 6-1. Main Block Diagram μP Port JTAG2 (RMII MODE) RXD[0:1] RX_CLK CRS_DV RX_ERR REF_CLK REF_CLKO TX_EN TXD[0:1] PACKET HDLC/X.86 ARBITER SYSCLKI ETHERNET MAC CIR CONTROLLER PACKET HDLC/X.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 6-2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 6-3. Receive and Transmit T1/E1/J1 LIU RPOSI RDCLKI RNEGI RNEGO RDCLKO RPOSO 8XCLK XTALD MCLK RCL VCO / PLL MUX 32.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 6-4.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 6-5.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 7 PIN DESCRIPTIONS 7.1 Pin Functional Description Note that all digital pins are IO pins in JTAG mode. This feature increases the effectiveness of board level ATPG patterns. LEGEND: I = input, O = output, Ipu = input with pullup, Oz = output with tri-state, IO = bidirectional pin, IOz = bidirectional pin with tri-state. Table 7-1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TYPE RD/DS B11 I FUNCTION Read Data Strobe (Intel Mode): The DS33R11 drives the data bus (D0-D7) with the contents of the addressed register while RD and CS are both low. Data Strobe (Motorola Mode): Used to latch data through the microprocessor interface. DS must be low during read and write operations. Chip Select for Protocol Conversion Device: This pin must be taken low for read/write operations.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TYPE FUNCTION MII/RMII PHY PORT COL_DET N18 I RX_CRS/ CRS_DV M19 I RX_CLK M20 RXD[0] L18 RXD[1] L19 IO O RXD[2] L20 RXD[3] M18 RX_DV K19 RX_ERR K18 Collision Detect (MII): Asserted by the MAC PHY to indicate that a collision is occurring. In DCE Mode this signal should be connected to ground. This signal is only valid in half duplex mode, and is ignored in full duplex mode.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TXD[0] F19 TXD[1] F18 TXD[2] E20 TXD[3] E19 TX_EN F20 TYPE O O FUNCTION Transmit Data 0 through 3(MII): TXD [3:0] is presented synchronously with the rising edge of TX_CLK. TXD [0] is the least significant bit of the data. When TX_EN is low the data on TXD should be ignored. Transmit Data 0 through 1(RMII): Two bits of data TXD [1:0] presented synchronously with the rising edge of REF_CLK.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TYPE FUNCTION PHY MANAGEMENT BUS MDC C19 O MDIO C20 IO Management Data Clock (MII): Clocks management data between the PHY and DS33R11. The clock is derived from theSYSCLKI, with a maximum frequency is 1.67MHz. The user must leave this pin unconnected in the DCE Mode. MII Management data IO (MII): Data path for control information between the PHY and DS33R11. When not used, pull to logic high externally through a 10kΩ resistor.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME SDATA[0] SDATA[1] SDATA[2] SDATA[3] SDATA[4] SDATA[5] SDATA[6] SDATA[7] SDATA[8] SDATA[9] SDATA[10] SDATA[11] SDATA[12] SDATA[13] SDATA[14] SDATA[15] SDATA[16] SDATA[17] SDATA[18] SDATA[19] SDATA[20] SDATA[21] SDATA[22] SDATA[23] SDATA[24] SDATA[25] SDATA[26] SDATA[27] SDATA[28] SDATA[29] SDATA[30] SDATA[31] SDA[0] SDA[1] SDA[2] SDA[3] SDA[4] SDA[5] SDA[6] SDA[7] SDA[8] SDA[9] SDA[10] SDA[11] SDMASK[0] SDMASK[1] SDMASK[2] SDMASK[3] PIN W2 Y4
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TYPE FUNCTION T1/E1/J1 ANALOG LINE INTERFACE TTIP R1, R2 O TRING T1,T2 O RTIP K1 I RRING M1 I Transmit Analog Tip Output for the T1/E1/J1 Transceiver: Analog line-driver outputs. Two connections are provided to improve signal quality. These pins connect via a 1:2 step-up transformer to the network. See Section 10.24 for details. Transmit Analog Ring Output for the T1/E1/J1 Transceiver: Analog line-driver outputs.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TYPE TSIG B4 I FUNCTION Transmit Signaling Input for the T1/E1/J1 Transceiver: When enabled, this input will sample signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLKT when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TYPE RSYNC G4 I/O RSYSCLK F4 I RFSYNC A3 O RMSYNC U3 O RSIG L3 O FUNCTION Receive Sync for the T1/E1/J1 Transceiver: An extracted pulse, one RCLKO wide, is output at this pin, which identifies either frame (TR.IOCR1.5 = 0) or multiframe (TR.IOCR1.5 = 1) boundaries. If set to output-frame boundaries then via TR.IOCR1.6, RSYNC can also be set to output double-wide pulses on signaling frames in T1 mode.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME RSERI RCLKI RDEN/ RBSYNC PIN TYPE FUNCTION ETHERNET MAPPER RECEIVE SERIAL INTERFACE Receive Serial Data Input to Ethernet Mapper: Receive Serial H1 I data arrives on the rising edge of RCLKI. Normally connected to RSERO. Serial Interface Receive Clock Input to the Ethernet Mapper: F2 I Reference clock for receive serial data on RSERI. Gapped clocking is supported, up to the maximum RCLKI frequency of 52 MHz.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TYPE TDCLKO C2 O TNEGI C3 I TNEGO D3 O TPOSI B3 I TPOSO E1 O TDATA A4 I TESO D4 O FUNCTION Transmit Clock Output from the T1/E1/J1 Framer: Buffered clock that is used to clock data through the transmit-side formatter (either TCLKT or RDCLKI). This pin is normally tied to TDCLKI. Transmit Negative-Data Input: Sampled on the falling edge of TDCLKI for data to be transmitted out onto the T1 line.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TYPE FUNCTION HARDWARE AND STATUS PINS Line Interface Unit Connect: When a logic low is present on this input pin, the T1/E1/J1 Framer and LIU are not internally connected. The line interface circuitry will be separated from the framer/formatter circuitry and the TPOSI, TNEGI, TDCLKI, RPOSI, RNEGI, and RDCLKI input pins will be active.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TYPE FUNCTION SYSTEM CLOCKS SYSCLKI V8 I MCLK H4 I BPCLK B1 O 8XCLK K4 O XTALD J4 O System Clock In for Ethernet Mapper: 100MHz System Clock input to the DS33R11, used for internal operation. This clock is buffered and provided at SDCLKO for the SDRAM interface. The DS33R11 also provides a divided version output at the REF_CLKO pin. A clock supply with ±100ppm frequency accuracy is suggested.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TYPE FUNCTION JTAG INTERFACE JTCLK1 A7 Ipu JTDI1 C9 Ipu JTDO1 B7 Oz JTMS1 C8 Ipu JTRST1 C7 Ipu JTCLK2 A6 Ipu JTDI2 B6 Ipu JTDO2 C5 Oz JTMS2 B9 Ipu JTRST2 B8 Ipu JTAG Clock 1 for the Ethernet Mapper: This signal is used to shift data into JTDI1 on the rising edge and out of JTDO1 on the falling edge.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver NAME PIN TYPE RVDD K3, L1 J1, J2, K2, L2, M2 U1 P1, R3, T3, U2 D1–D17, E17 N4, P4, R4, T4 B10, B15, C12, F3, J18, J20, P18, P19, R19, R20, V9, Y9, Y13 D20, F17, G17, G18, H17, J17, K17, L17, M17, N17, P17, R17, R18, T17, T18, U17 A15, C10, D8, D9, D10, D18, D19, E18, H20, J19, K20, N19, N20, P20, U4–U16, U18, V20, W8, W18, Y1, Y7 — A9, C6, D6 — RVSS TVDD TVSS DVDD DVSS VDD1.8 VDD3 VSS N.C.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 7-1. 256-Ball BGA Pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A RCHBLK TCHBLK RFSYNC TDATA TSSYNC JTCLK2 JTCLK1 RST N.C. INT CS D6 D3 D0 VSS A6 A3 A0 REF_CLK REF_ CLKO B BPCLK LIUC TPOSI TSIG RCL JTDI2 JTDO1 JTRST2 JTMS2 VDD1.8 RD/DS D7 D4 D1 VDD1.8 A7 A4 A1 MODEC [0] MODEC [1] C TSYNC TDCLKO TNEGI TSTRST JTDO2 N.C. JTRST1 JTMS1 JTDI1 VSS WR/RW VDD1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 8 FUNCTIONAL DESCRIPTION The DS33R11 provides interconnection and mapping functionality between Ethernet packet LANs and T1/E1/J1 WAN Time-Division Multiplexed (TDM) systems. The device is composed of a 10/100 Ethernet MAC, packet arbiter, committed information rate controller (CIR), HDLC/X.86 (LAPS) mapper, SDRAM interface, control ports, bit error-rate tester (BERT), and integrated T1/E1/J1 transceiver.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Both the transmit and receive path of the integrated T1/E1/J1 transceiver also have two HDLC controllers. The HDLC controllers transmit and receive data through the framer block. The HDLC controllers can be assigned to any time slot, group of time slots, portion of a time slot or to FDL (T1) or Sa bits (E1). Each controller has 128-byte FIFOs, thus reducing the amount of processor overhead required to manage the flow of data.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9 ETHERNET MAPPER 9.1 Ethernet Mapper Clocks The DS33R11 clocks sources and functions are as follows: • Serial Transmit Data (TCLKE) and Serial Receive Data (RCLKI) clock inputs are used to transfer data from the serial interface. These clocks can be continuous or gapped. • System Clock (SYSCLKI) input. Used for internal operation. This clock input cannot be a gapped clock. A clock supply with ±100ppm frequency accuracy is suggested.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver TCLKE TDEN TSYSCLK TCHBLK TCHCLK TCLKT TDCLKI TDCLKO MCLK XTALD 8XCLK BPCLK Figure 9-1. Clocking for the DS33R11 μP Port JTAG2 SYSCLKI CIR CONTROLLER REF_CLKO RX_CLK ETHERNET MAC PACKET HDLC/X.86 ARBITER PACKET HDLC/X.86 TRANSMIT SERIAL PORT RECEIVIE FRAMER MUX JTAG1 JTCLK1 SDCLK RCLKI RDEN RSYSCLK RCHBLK RCHCLK RCLKO NOTE THAT THE CLOCKING OPTIONS OF THE INTEGRATED T1/E1/J1 TANSCEIVER ARE DISCUSSED IN SECTION 10.1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.1.1 Ethernet Interface Clock Modes The Ethernet PHY interface has several different clocking requirements, depending on the mode of operation. Table 9-1 outlines the possible clocking modes for the Ethernet Interface. The buffered REF_CLKO output is generated by division of the 100MHz system clock input by the user on SYSCLKI. The frequency of the REF_CLKO pin is automatically determined by the DS33R11 based on the state of the RMIIMIIS pin.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.2 Resets and Low Power Modes The external RST pin and the global reset bit in GL.CR1 create an internal global reset signal. The global reset signal resets the status and control registers on the chip (except the GL.CR1.RST bit) to their default values and resets all the other flops to their reset values. The processor bus output signals are also placed in high-impedance mode when the RST pin is active (low). The global reset bit (GL.CR1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.3 Initialization and Configuration EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Apply 3.3V supplies, then apply 1.8V supplies. STEP 2: Reset the integrated Ethernet Mapper by pulling the RST pin low or by using the software reset bits outlined in Section 9.2. Clear all reset bits. Allow 5ms for the reset recovery.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.6 Device Interrupts Figure 9-2 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global Latched Status registers GL.LIS, GL.SIS, GL.BIS, and GL.TRQIS to initially determine the source of the interrupt. The host can then read the LI.TQCTLS, LI.TPPSRL, LI.RPPSRL, LI.RX86S, SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver SAPI High is not equal to LI.TRX86SAPIH SAPI Low is not equal to LI.TRX86SAPIL Control is not equal to LI.TRX8C Address is not equal to LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.7 Interrupt Information Registers The interrupt information registers provide an indication of which status registers (SR1 through SR9) are generating an interrupt. When an interrupt occurs, the host can read TR.IIR1 and TR.IIR2 to quickly identify which of the nine status registers are causing the interrupt. 9.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.11 Connections and Queues The multi-port devices in this product family provide bidirectional cross-connections between the multiple Ethernet ports and Serial ports when operating in software mode. A single connection is preserved in this single-port device to provide software compatibility with multi-port devices. The connection will have an associated transmit and receive queue.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver It is recommended that the user reset the queue pointers for the connection after disconnection. The pointers must be reset before a connection is made. If this disconnect/connect procedure is not followed, incorrect data may be transmitted. The proper procedure for setting up a connection follows: • Set up the queue sizes for both transmit and receive queue (AR.TQSC1 and AR.RQSC1).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.13 Flow Control Flow control may be required to ensure that data queues do not overflow and packets are not lost. The DS33R11 allows for optional flow control based on the queue high watermark or through host processor intervention. There are 2 basic mechanisms that are used for flow control: • In half duplex mode, a jam sequence is sent that causes collisions at the far end.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.13.1 Full Duplex Flow Control Automatic flow control is enabled by default. The host processor can disable this functionality with SU.GCR.ATFLOW. The flow control mechanism is governed by the high watermarks (SU.RQHT). The SU.RQLT low threshold can be used as indication that the network congestion is clearing up. The value of SU.RQLT does not affect the flow control.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 9-3. Flow Control Using Pause Control Frame 8 Receive Queue Low Water Rx Data Receive Queue Growth Receive Queue High Water Mark Initiate Flow control 9.13.2 Half Duplex Flow Control Half duplex flow control uses a jamming sequence to exert backpressure on the transmitting node. The receiving node jams the first 4 bytes of a packet that are received from the MAC in order to cause collisions at the distant end.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.14 Ethernet Interface Port The Ethernet port interface allows for direct connection to an Ethernet PHY. The interface consists of a 10/100Mbit/s MII/RMII interface and an Ethernet MAC. In RMII operation, the interface contains seven signals with a reference clock of 50 MHz. In MII operation, the interface contains 17 signals and a clock reference of 25MHz. The DS33R11 can be configured to RMII or MII interface by the Hardware pin RMIIMIIS.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver The MAC circuitry generates a frame status for every frame that is received. This real time status can be read by SU.RFSB0 to SU.RFSB3. Note the frame status is the “real time” status and hence the value will change as new frames are received. Hence the real time status reflects the status in time and may not correspond to the current received frame being processed. This is also true for the transmitted frames.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.14.1 DTE and DCE Mode The Ethernet MII/RMII port can be configured for DCE or DTE Mode. When the port is configured for the DTE Mode it can be connected to an Ethernet PHY. In DCE mode, the port can be connected to MII/RMII MAC devices other than an Ethernet PHY. The DTE/DCE connections for the DS33R11 in MII mode are shown in the following two figures.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 9-6. DS33R11 Configured as a DCE in MII Mode DS33Z11 DTE DCE Rx Tx RXD[3:0] MAC Tx TXD[3:0] RXDV RX_CLK TX_EN TX_CLK RX_ERR TX_ERR RX_CRS RX_CRS COL_DET COL_DET TXD[3:0] RXD[3:0] TX_CLK RX_CLK MAC Rx TX_EN MDIO MDC RXDV MDIO MDC 9.15 Ethernet MAC Indirect addressing is required to access the MAC register settings. Writing to the MAC registers requires the SU.MACWD0-3 registers to be written with 4 bytes of data.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Table 9-6. MAC Control Registers ADDRESS REGISTER 0000h-0003h SU.MACCR 0014h-0017h SU.MACMIIA 0018h-001Bh SU.MACMIID 001Ch-001Fh SU.MACFCR 0100h-0103h SU.MMCCTRL DESCRIPTION MAC Control Register. This register is used for programming full duplex, half duplex, promiscuous mode, and back-off limit for half duplex. The transmit and receive enable bits must be set for the MAC to operate. MAC MII Management (MDIO) Address Register.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.15.1 MII Mode Options The Ethernet interface can be configured for MII operation by setting the hardware pin RMIIMIIS low. The MII interface consists of 17 pins. For instructions on clocking the Ethernet Interface while in MII mode, see Section 9.1. Diagrams of system connections for MII operation are shown in Figure 9-5 and Figure 9-6. 9.15.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.15.3 PHY MII Management Block and MDIO Interface The MII Management Block allows for the host to control up to 32 PHYs, each with 32 registers. The MII block communicates with the external PHY using 2-wire serial interface composed of MDC (serial clock) and MDIO for data. The MDIO data is valid on the rising edge of the MDC clock. The Frame format for the MII Management Interface is shown Figure 9-8.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.16.1 Receive Data Interface 9.16.1.1 Receive Pattern Detection The Receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.16.2 Repetitive Pattern Synchronization Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern. The receive pattern generator is synchronized by searching each incoming data stream bit position for the repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.16.4.1 Error Insertion Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time Single bit error insertion can be initiated from the microprocessor interface. If pattern inversion is enabled, the data stream is inverted before the overhead/stuff bits are inserted. Pattern inversion is programmable (on or off). 9.16.4.2 Performance Monitoring Update All counters stop counting at their maximum count.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.18 Receive Packet Processor The Receive Packet Processor accepts data from the Receive Serial Interface performs packet descrambling, packet delineation, inter-frame fill filtering, packet abort detection, destuffing, packet size checking, FCS error monitoring, FCS byte extraction, and bit reordering. The data coming from the Receive Serial Interface is a serial data stream. Packet processing can be disabled (clear channel enable).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Bit reordering changes the bit order of each byte. If bit reordering is disabled, the incoming 8-bit data stream DT[1:8] with DT[1] being the MSB and DT[8] being the LSB is output to the Receive FIFO with the MSB in RFD[7] (or 15, 23, or 31) and the LSB in RFD[0] (or 8, 16, or 24) of the receive FIFO data RFD[7:0] (or 15:8, 23:16, or 31:24).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.19 X.86 Encoding and Decoding X.86 protocol provides a method for encapsulating Ethernet Frame onto LAPS. LAPS provides HDLC type framing structure for encapsulation of Ethernet frames. LAPS encapsulated frames can be used to send data onto a SONET/SDH network. The DS33R11 expects a byte synchronization signal to provide the byte boundary for the X.86 receiver. This is provided by the RBSYNC pin. The functional timing is shown in Figure 12-4.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 9-13. X.86 Encapsulation of the MAC frame Number of Bytes Flag(0x7E) 1 Address(0x04) 1 Control(0x03) 1 1st Octect of SAPI(0xfe) 1 2nd Octect of SAPI(0x01) 1 Destination Adrs(DA) 6 Source Adrs(SA) 6 Length/Type 2 MAC Client Data 46-1500 PAD FCS for MAC 4 FCS for LAPS 4 Flag(0x7E) MSB LSB The DS33R11 will encode the MAC Frame with the LAPS encapsulation on a complete serial stream if configured for X.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver The X86 received frame is aborted if: • • • • • If 7d,7E is detected. This is an abort packet sequence in X.86. Invalid FCS is detected. The received frame has less than 6 octets. Control, SAPI and address field are mismatched to the programmed value. Octet 7d and octet other than 5d,5e,7e or dd is detected. For the transmitter if X.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 9.20 Committed Information Rate Controller The DS33R11 provides a CIR provisioning facility. The CIR can be used restricts the transport of received MAC data to a programmable rate. The CIR location is shown in the Figure 6-1. The CIR will restrict the data flow from the Receive MAC to Transmit HDLC. This can be used for provisioning and billing functions towards the WAN.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10 INTEGRATED T1/E1/J1 TRANSCEIVER 10.1 T1/E1/J1 Clocks Figure 10-1 shows the clock map of the T1/E1 transceiver. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity. Figure 10-1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Table 10-1. T1/E1/J1 Transmit Clock Source TCSS1 TCSS0 0 0 0 1 1 0 1 1 TRANSMIT CLOCK SOURCE The TCLKT pin (C) is always the source of transmit clock. Switch to the recovered clock (B) when the signal at the TCLKT pin fails to transition after one channel time. Use the scaled signal (A) derived from MCLK as the transmit clock. The TCLKT pin is ignored. Use the recovered clock (B) as the transmit clock. The TCLKT pin is ignored. 10.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.4 T1 Framer/Formatter Control and Status The T1 framer portion of the transceiver is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the transceiver has been initialized, the control registers only need to be accessed when there is a change in the system configuration. There are two receive control registers (TR.T1RCR1 and TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (TR.T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt pattern. The digital-milliwatt code is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.5 E1 Framer/Formatter Control and Status The E1 framer portion of the transceiver is configured by a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers need only to be accessed when there is a change in the system configuration. There are two receive control registers (TR.E1RCR1 and TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.5.1 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (TR.E1TCR2.1 = 1), the device monitors the receive-side framer to determine if any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss-of-receive carrier (or signal).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.7 Error Counters The transceiver contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Configuration Register (TR.ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.7.2 Path Code Violation Count Register (TR.PCVCR) In T1 mode, the path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF framing mode, TR.PCVCR records errors in the CRC6 codewords. When set to operate in the T1 D4 framing mode, TR.PCVCR counts errors in the Ft framing bit position. Through the TR.ERCNT.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR) In T1 mode, TR.FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame count (LOFC) and ESF error events as described in AT&T publication TR54016. When TR.FOSCR is operated in this mode, it is not disabled during receive loss-of-synchronization (RLOS = 1) conditions.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.8 DS0 Monitoring Function The transceiver has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TR.TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the TR.RDS0SEL register need to be properly set.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.9 Signaling Operation There are two methods to access receive signaling data and provide transmit signaling data, processor-based (software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers RS1–RS16 and TS1–TS16. Hardware-based refers to the TSIG and RSIG pins. Both methods can be used simultaneously. Figure 10-2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.9.2 Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSERO pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 robbed bit or E1 TS16, is still present in the original data stream at RSERO.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 10-3. Simplified Diagram of Transmit Signaling Path TRANSMIT SIGNALING REGISTERS 1 0 0 T1/E1 DATA STREAM TSER 0 1 1 B7 SIGNALING BUFFERS TSIG TR.T1TCR1.4 PER-CHANNEL CONTROL TR.PCPR.3 PER-CHANNEL CONTROL TR.SSIE1 TR.SSIE4 ONLY APPLIES TO T1 MODE 10.9.3 Processor-Based Transmit Signaling In processor-based mode, signaling data is loaded into the transmit signaling registers (TS1–TS16) by the host interface.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.9.3.2 E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in E1. In “Channel” numbering, TS0–TS31 are labeled channels 1 through 32.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.10 Per-Channel Idle Code Generation Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used by the device, the remaining channels, CH25–CH32, are not used. The device contains a 64-byte idle code array accessed by the idle array address register (TR.IAAR) and the perchannel idle code register (TR.PCICR).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.10.1 Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh. Write TR.IAAR = 02h Write TR.PCICR = 7Eh ;select channel 3 in the array ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, 5, and 6 idle code to 7Eh and enables transmission of idle codes for those channels. Write Write Write Write Write Write TR.IAAR = 02h TR.PCICR = 7Eh TR.PCICR = 7Eh TR.PCICR = 7Eh TR.PCICR = 7Eh TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.11 Channel Blocking Registers The receive channel blocking registers (TR.RCBR1/TR.RCBR2/TR.RCBR3/TR.RCBR4) and the transmit channel blocking registers (TR.TCBR1/TR.TCBR2/TR.TCBR3/TR.TCBR4) control RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual channels.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.12.2 Transmit Elastic Store See the TR.IOCR1 and TR.IOCR2 registers for information about clock and I/O configurations. The operation of the transmit elastic store is very similar to the receive side. If the transmit-side elastic store is enabled, a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. Controlled slips in the transmit elastic store are reported in the TR.SR5.3 bit, and the direction of the slip is reported in the TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.13 G.706 Intermediate CRC-4 Updating (E1 Mode Only) The device can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSERI already has the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions. This change in data content is used to modify the CRC-4 checksum.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.14 T1 Bit-Oriented Code (BOC) Controller The transceiver contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 10.14.1 Transmit BOC Bits 0 to 5 in the TR.TFDL register contain the BOC message to be transmitted. Setting TR.BOCC.0 = 1 causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.15 Additional (Sa) and International (Si) Bit Operation (E1 Only) When operated in the E1 mode, the transceiver provides two methods for accessing the Sa and the Si bits. The first method involves using the internal TR.RAF/TR.RNAF and TR.TAF/TR.TNAF registers (Section 10.15.1). The second method, which is covered in Section 10.15.2, involves an expanded version of the first method. 10.15.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.16 Additional HDLC Controllers in T1/E1/J1 Transceiver This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC controller has 128-byte buffers in the transmit and receive paths.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Table 10-12. HDLC Controller Registers REGISTER FUNCTION CONTROL AND CONFIGURATION General control over the transmit HDLC controllers TR.H1TC, HDLC #1 Transmit Control Register TR.H2TC, HDLC #2 Transmit Control Register General control over the receive HDLC controllers TR.H1RC, HDLC #1 Receive Control Register TR.H2RC, HDLC #2 Receive Control Register Sets high watermark for receiver and low TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.16.2 FIFO Control The FIFO control register (TR.HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register TR.SR6 or TR.SR7 is set.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.16.4 FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer. 10.16.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.17 Legacy FDL Support (T1 Mode) 10.17.1 Overview To provide backward compatibility to the older DS21x52 T1 device, the transceiver maintains the circuitry that existed in the previous generation of the T1 framer. In new applications, it is recommended that the HDLC controllers and BOC controller described in Section 10.14 and 10.16 are used. 10.17.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.17.3 Transmit Section The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TR.TFDL). When a new value is written to TR.TFDL, it is multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.19 Programmable In-Band Loop Code Generation and Detection The transceiver has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. To transmit a pattern, the user loads the pattern into the transmit code-definition registers (TR.TCD1 and TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.20 Line Interface Unit (LIU) The LIU contains three sections: the receiver that handles clock and data recovery, the transmitter that waveshapes and drives the T1 line, and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described in the following sections. The LIU has its own T1/E1 mode-select bit and can operate independently of the framer function.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.20.2.1 Receive Level Indicator and Threshold Interrupt The device reports the signal strength at RTIP and RRING in 2.5dB increments through RL3–RL0 located in Information Register 2 (TR.INFO2). This feature is helpful when trouble-shooting line-performance problems. The device can initiate an interrupt whenever the input falls below a certain level through the input-level under-threshold indicator (TR.SR1.7). Using the RLT0–RLT4 bits of the TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.20.3 Transmitter The transceiver uses a phase-lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the device meet the latest ETSI, ITU-T, ANSI, and AT&T specifications. The user selects which waveform is generated by setting the ETS bit (TR.LIC2.7) for E1 or T1 operation, then programming the L2/L1/L0 bits in register TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.21 MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 interfaces. A prescaler divides the 16MHz, 8MHz, or 4MHz clock down to 2.048MHz. There is an on-board PLL for the jitter attenuator, which converts the 2.048MHz clock to a 1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.24 Recommended Circuits Figure 10-7. Basic Interface VDD DS33R11 2:1 TTIP TRANSMIT LINE C DVDD 0.1μF 0.01μF DVSS TRING 1:1 RTIP RECEIVE LINE TVDD 0.1μF 10μF + TVSS RVDD 0.1μF 10μF + RRING RVSS R R 0.1μF NOTE 1: ALL RESISTOR VALUES ARE ±1%. NOTE 2: RESISTORS R SHOULD BE SET TO 60Ω EACH IF THE INTERNAL RECEIVE-SIDE TERMINATION FEATURE IS ENABLED. WHEN THIS FEATURE IS DISABLED, R = 37.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 10-8. E1 Transmit Pulse Template 1.2 SCALED AMPLITUDE (IN 75Ω SYSTEMS, 1.0 ON THE SCALE = 2.37VPEAK IN 120Ω SYSTEMS, 1.0 ON THE SCALE = 3.00VPEAK) 1.1 269ns 1.0 0.9 0.8 0.7 G.703 TEMPLATE 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (ns) Figure 10-9. T1 Transmit Pulse Template 1.2 MAXIMUM CURVE UI Time Amp. 1.1 1.0 -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 10-10. Jitter Tolerance UNIT INTERVALS (UIP-P) 1k DEVICE TOLERANCE 100 TR 62411 (DEC. 90) 10 ITU-T G.823 1 0.1 10 1 100 1k FREQUENCY (Hz) 10k 100k Figure 10-11. Jitter Tolerance (E1 Mode) UNIT INTERVALS (UIP-P) 1k DEVICE TOLERANCE 100 40 10 1.5 1 MINIMUM TOLERANCE LEVEL AS PER 0.2 ITU G.823 0.1 1 10 20 100 1k FREQUENCY (Hz) 106 of 344 2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 10-12. Jitter Attenuation (T1 Mode) -20dB C ve ur A TR 62411 (Dec. 90) Prohibited Area -40dB rve Cu JITTER ATTENUATION (dB) 0dB B T1 MODE -60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K Figure 10-13. Jitter Attenuation (E1 Mode) JITTER ATTENUATION (dB) 0 TBR12 Prohibited Area ITU G.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 10-14. Optional Crystal Connections XTALD 1.544MHz/2.048MHz MCLK C1 C2 NOTE: C1 AND C2 SHOULD BE 5pF LOWER THAN TWO TIMES THE NOMINAL LOADING CAPACITANCE OF THE CRYSTAL TO ADJUST FOR THE INPUT CAPACITANCE OF THE DEVICE. 10.25 T1/E1/J1 TRANSCEIVER BERT FUNCTION The BERT block can generate and detect pseudorandom and repeating bit patterns.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 10-15. Simplified Diagram of BERT in Network Direction TO RECEIVE SYSTEM BACKPLANE INTERFACE FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO TRANSMIT FRAMER BERT RECEIVER BERT TRANSMITTER 1 FROM TRANSMIT SYSTEM BACKPLANE INTERFACE 0 Figure 10-16.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.25.3 BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is fewer than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.26 Payload Error-Insertion Function (T1 Mode Only) An error-insertion function is available in the transceiver and is used to create errors in the payload portion of the T1 frame in the transmit path. This function is only available in T1 mode. Errors can be inserted over the entire frame or the user can select which channels are to be corrupted. Errors are created by inverting the last bit in the count sequence.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.27 Programmable Backplane Clock Synthesizer The transceiver contains an on-chip clock synthesizer that generates a user-selectable clock output on the BPCLK pin, referenced to the recovered receive clock (RCLKO). The synthesizer uses a phase-locked loop to generate low-jitter clocks. Common applications include generation of port and backplane system clocks. The TR.CCR2 register is used to enable (TR.CCR2.0) and select (TR.CCR2.1 and TR.CCR2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 10.29 T1/E1/J1 Transmit Flow Diagrams Figure 10-17. T1/J1 Transmit Flow Diagram TSIG TSER T1 TRANSMIT FLOW DIAGRAM Hardware Signaling HSIE1-3 through PCPR TX ESTORE KEY - PIN Estore Mux ESCR.4 TESE - SELECTOR TESO Off-Chip Connection RDATA From T1_rcv_logic - REGISTER TDATA LBCR1.1 PLB Payload Loopback HDLC Engine #1 TLINK H1TC.4 THMS1 HDLC FDL #1 THMS1 H1TC.4 H1TCS1-3 H1TTSBS HDLC Mux #1 HDLC Engine #2 H2TC.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver From ESF Yellow Alarm From BOC Mux From F-bit Mux TFPT T1TCR1.5 FDL Mux TFM T1CCR1.2 ESF Yellow TYEL T1TCR1.0 CRC Mux TCPT T1TCR1.5 D4 bit 2 Yellow Alm BERT Engine TFM T1CCR1.2 TD4YM T1TCR2.2 TYEL T1TCR1.0 TFUS BIC.3 F-bit BERT Mux T1TCR2.3 FBCT1 T1TCR2.4 FBCT2 F-bit Corruption BTCS1-3 Payload error insertion NOEL != 0 ERC.4 CE BERTEN BIC.0 PEICS1-3 SSIE1-3 Bit 7 stuffing T1CCR1.1 PDE GB7S T1TCR1.3 B7SE T1TCR2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 10-18. E1 Transmit Flow Diagram TSER E1 TRANSMIT FLOW DIAGRAM TSIG Hardware Signaling HSIE1-4 through PCPR TX ESTORE Estore Mux ESCR.4 TESE TESO Off-Chip Connection TDATA RDATA From E1_rcv_logic Payload Loopback Mux LBCR1.1 PLB HDLC Engine #1 THMS1 H1TC.4 HDLC DS0 Mux #1 H1TCS1-4 H1TTSBS THMS1 H1TC.4 HDLC Sa-bit Mux #1 T1SaBE4T1SaBE8 H1TTSBS.4 - H1TTSBS.0 HDLC Engine #2 THMS2 H2TC.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver From Idle Code Mux RDATA From E1_rcv_logic Per-Channel Loopback E1 TRANSMIT FLOW DIAGRAM PCLR1-4 TNAF THMS1 Sa-bit Mux TS0 Mux E1TCR1.4 TSIS H1TC.4 THMS2 H2TC.4 TAF/TNAF(non Sa) TFPT E1TCR1.7 Si-bit Mux Si = CRC4 MF Align Word (Does not overwrite E-bits) E1TCR1.0 TCRC4 E1TCR2.2 AEBE Sa4S - Sa8S E1TCR2.5 - E1TCR2.7 E1TCR2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11 DEVICE REGISTERS Ten address lines are used to address the register space. Table 11-1 shows the register map for the DS33R11. The addressable range for the device is 0000h to 08FFh. Each Register Section is 64 bytes deep. Global Registers are preserved for software compatibility with multiport devices. The Serial Interface (Line) Registers are used to configure the serial port and the associated transport protocol.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.1 Register Bit Maps Table 11-2, Table 11-3, Table 11-4, Table 11-5, Table 11-6, and Table 11-7 contain the registers of the DS33R11. Bits that are reserved are noted with a single dash “-“. All registers not listed are reserved and should be initialized with a value of 00h for proper operation, unless otherwise noted. 11.1.1 Global Ethernet Mapper Register Bit Map Table 11-2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.1.2 Arbiter Register Bit Map Table 11-3. Arbiter Register Bit Map NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDR 40h AR.RQSC1 RQSC7 RQSC6 RQSC5 RQSC4 RQSC3 RQSC2 RQSC1 RQSC0 41h AR.TQSC1 TQSC7 TQSC6 TQSC5 TQSC4 TQSC3 TQSC2 TQSC1 TQSC0 11.1.3 BERT Register Bit Map Table 11-4.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.1.4 Serial Interface Register Bit Map Table 11-5. Serial Interface Register Bit Map ADDR NAME 0C0h LI.TSLCR 0C1h LI.RSTPD 0C2h LI.LPBK 0C3h Reserved 0C4h LI.TPPCL 0C5h LI.TIFGC 0C6h LI.TEPLC 0C7h LI.TEPHC 0C8h LI.TPPSR 0C9h LI.TPPSRL 0CAh LI.TPPSRIE 0CBh Reserved 0CCh LI.TPCR0 0CDh LI.TPCR1 0CEh LI.TPCR2 0CFh Reserved 0D0h LI.TBCR0 0D1h LI.TBCR1 0D2h LI.TBCR2 0D3h LI.TBCR3 0D4h LI.TMEI 0D5h Reserved 0D6h LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver ADDR NAME 114h LI.RSPCB0 115h LI.RSPCB1 116h LI.RSPCB2 118h LI.RBC0 119h LI.RBC1 11Ah LI.RBC2 11Bh LI.RBC3 11Ch LI.RAC0 11Dh LI.RAC1 11Eh LI.RAC2 11Fh LI.RAC3 120h LI.RHPMUU 121h LI.RHPMUS 122h 123h 124h 125h 126h 127h LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.1.5 Ethernet Interface Register Bit Map Table 11-6. Ethernet Interface Register Bit Map BIT 7 ADDR NAME MACRA7 140h SU.MACRADL MACRA15 SU.MACRADH 141h MACRD7 142h SU.MACRD0 MACRD15 SU.MACRD1 143h MACRD23 144h SU.MACRD2 MACRD31 SU.MACRD3 145h MACWD7 SU.MACWD0 146h MACWD15 SU.MACWD1 147h MACWD23 148h SU.MACWD2 MACD31 SU.MACWD3 149h MACAW 7 SU.MACAWL 14Ah MACAW 15 SU.MACAWH 14Bh 14Ch SU.MACRWC RESERVED 14Eh SU.LPBK 14Fh SU.GCR 150h SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.1.6 MAC Register Bit Map Table 11-7. MAC Indirect Register Bit Map ADDR 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 100h 101h 102h 103h 10Ch 10Dh 10Eh 10Fh 110h 111h NAME SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver ADDR 112h 113h 200h 201h 202h 203h 204h 205h 206h 207h 300h 301h 302h 303h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 334h 335h 336h 337h 338h 339h 33Ah 33Bh NAME RESERVED – initialize to FF RESERVED – initialize to FF SU.RxFrmCtr 31:24 23:16 15:8 7:0 SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Table 11-8.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver ADD NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R h 01A h 01B h 01C h 01D h 01E h 01F h 020 h 021 h 022 h 023 h 024 h 025 h 026 h 027 h 028 h 029 h 02A h 02B h 02C h 02D h 02E h 02F h 030 h 031 h 032 h 033 h 034 TR.SR3 TR.IMR3 TR.SR4 TR.IMR4 TR.SR5 TR.IMR5 TR.SR6 TR.IMR6 TR.SR7 TR.IMR7 TR.SR8 TR.IMR8 TR.SR9 TR.IMR9 TR.PCPR TR.PCDR1 TR.PCDR2 TR.PCDR3 TR.PCDR4 TR.INFO4 TR.INFO5 TR.INFO6 TR.INFO7 TR.H1RC TR.H2RC TR.E1RCR1 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver ADD NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R h 035 h 036 h 037 h 038 h 039 h 03A h 03B h 03C h 03D h 03E h 03F h 040 h 041 h 042 h 043 h 044 h 045 h 046 h 047 h 048 h 049 h 04A h 04B h 04C h 04D h 04E h 04F TR.E1TCR1 TR.E1TCR2 TR.BOCC TR.RSINFO1 TR.RSINFO2 TR.RSINFO3 TR.RSINFO4 TR.RSCSE1 TR.RSCSE2 TR.RSCSE3 TR.RSCSE4 TR.SIGCR TR.ERCNT TR.LCVCR1 TR.LCVCR2 TR.PCVCR1 TR.PCVCR2 TR.FOSCR1 TR.FOSCR2 TR.EBCR1 TR.EBCR2 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver ADD NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R h 050 h 051 h 052 h 053 h 054 h 055 h 056 h 057 h 058 h 059 h 05A h 05B h 05C h 05D h 05E h 05F h 060 h 061 h 062 h 063 h 064 h 065 h 066 h 067 h 068 h 069 h TR.TS1 TR.TS2 TR.TS3 TR.TS4 TR.TS5 TR.TS6 TR.TS7 TR.TS8 TR.TS9 TR.TS10 TR.TS11 TR.TS12 TR.TS13 TR.TS14 TR.TS15 TR.TS16 TR.RS1 TR.RS2 TR.RS3 TR.RS4 TR.RS5 TR.RS6 TR.RS7 TR.RS8 TR.RS9 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver ADD NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R 06A h 06B h 06C h 06D h 06E h 06F h 070 h 071 h 072 h 073 h 074 h 075 h 076 h 077 h 078 h 079 h 07A h 07B h 07C h 07D h 07E h 07F h 080 h 081 h 082 h 083 h 084 h Receive Signaling Bit Format Changes With Operating Mode. See Register Definition. TR.RS11 Receive Signaling Bit Format Changes With Operating Mode. See Register Definition. TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver ADD NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R 085 h 086 h 087 h 088 h 089 h 08A h 08B h 08C h 08D h 08E h 08F h 090 h 091 h 092 h 093 h 094 h 095 h 096 h 097 h 098 h 099 h 09A h 09B h 09C h 09D h 09E h 09F h TR.RCICE2 TR.RCICE3 TR.RCICE4 TR.RCBR1 TR.RCBR2 TR.RCBR3 TR.RCBR4 TR.TCBR1 TR.TCBR2 TR.TCBR3 TR.TCBR4 TR.H1TC TR.H1FC TR.H1RCS1 TR.H1RCS2 TR.H1RCS3 TR.H1RCS4 TR.H1RTSBS TR.H1TCS1 TR.H1TCS2 TR.H1TCS3 TR.H1TCS4 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver ADD NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R 0A0 h 0A1 h 0A2 h 0A3 h 0A4 h 0A5 h 0A6 h 0A7 h 0A8 h 0A9 h 0AA h 0AB h 0AC h 0AD h 0AE h 0AF h 0B6 h 0B7 h 0B8 h 0B9 h 0BA h 0BB h 0BC h 0BD h 0BE h 0BF h 0C0 h TR.H2TC TR.H2FC TR.H2RCS1 TR.H2RCS2 TR.H2RCS3 TR.H2RCS4 TR.H2RTSBS TR.H2TCS1 TR.H2TCS2 TR.H2TCS3 TR.H2TCS4 TR.H2TTSBS TR.H2RPBA TR.H2TF TR.H2RF TR.H2TFBA TR.IBCC TR.TCD1 TR.TCD2 TR.RUPCD1 TR.RUPCD2 TR.RDNCD1 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver ADD NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R 0C1 h 0C2 h 0C3 h 0C3 h 0C5 h 0C6 h 0C7 h 0C8 h 0C9 h 0CA h 0CB h 0CC h 0CD h 0CE h 0CF h 0D0 h 0D1 h 0D2 h 0D3 h 0D4 h 0D5 h 0D6 h 0D7 h 0D8 h 0D9 h 0DA h 0DB h TR.TFDL TR.RFDLM1 TR.RFDLM2 Reserved Reserved TR.RAF TR.RNAF TR.RSiAF TR.RSiNAF TR.RRA TR.RSa4 TR.RSa5 TR.RSa6 TR.RSa7 TR.RSa8 TR.TAF TR.TNAF TR.TSiAF TR.TSiNAF TR.TRA TR.TSa4 TR.TSa5 TR.TSa6 TR.TSa7 TR.TSa8 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver ADD NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R 0DC h 0DD h 0DE h 0DF h 0E0 h 0E1 h 0E2 h 0E3 h 0E4 h 0E5 h 0E6 h 0E7 h 0E8 h 0E9 h 0EA h 0EB h 0EC h 0ED h 0EE h 0EF h TR.BRP1 TR.BRP2 TR.BRP3 TR.BRP4 TR.BC1 TR.BC2 Reserved TR.BBC1 TR.BBC2 TR.BBC3 TR.BBC4 TR.BEC1 TR.BEC2 TR.BEC3 TR.BIC TR.ERC TR.NOE1 TR.NOE2 TR.NOEL1 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.2 Global Register Definitions for Ethernet Mapper Functions contained in the global registers include: framer reset, LIU reset, device ID, and BERT interrupt status. These registers are preserved to provide code compatibility with the multiport devices in this product family. The global registers bit descriptions are presented below. Register Name: Register Description: Register Address: Bit # Name Default 7 ID07 0 GL.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 - GL.CR1 Global Control Register 1 02h 6 - 5 - 4 - 3 - 2 REF_CLKO 0 1 INTM 0 0 RST 0 Bit 2: REF_CLKO OFF (REF_CLKO) This bit determines if the REF_CLKO is turned off 1 = REF_CLKO is disabled and outputs an active low signal.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 - GL.RTCAL Global Receive and Transmit Serial Port Clock Activity Latched Status 04h 6 - 5 - 4 RLCALS1 - 3 - 2 - 1 - 0 TLCALS1 - Bit 4: Receive Serial Interface Clock Activity Latched Status 1 (RLCALS1) This bit is set to 1 if the receive clock for Serial Interface 1 has activity. This bit is cleared upon read.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 GL.LIS Global Serial Interface Interrupt Status 07h 6 0 5 0 4 LIN1TIS 0 3 0 2 0 1 0 0 LIN1RIS 0 Bit 4: Serial Interface 1 TX Interrupt Status (LINE1TIS) This bit is set if Serial Interface 1 Transmit has an enabled interrupt generating event. Serial Interface interrupts consist of HDLC interrupts and X.86 interrupts.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 GL.TRQIE Global Transmit Receive Queue Interrupt Enable 0Ah 6 0 5 0 4 TQ1IE 0 3 0 2 0 1 0 0 RQ1IE 0 Bit 4: Transmit Queue 1 Interrupt Enable (TQ1IE) Setting this bit to 1 enables an interrupt on TQ1IS. Bit 0: Receive Queue 1 Interrupt Enable (RQ1IE) Setting this bit to 1 enables an interrupt on RQ1IS.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default GL.BIS Global BERT Interrupt Status 0Dh 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 BIS 0 Bit 0: BERT Interrupt Status (BIS) This bit is set to 1 if the BERT has an enabled interrupt generating event. Register Name: Register Description: Register Address: Bit # Name Default 7 0 GL.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: GL.C1QPR Connection 1 Queue Pointer Reset 12h Bit # 7 6 5 4 3 2 1 0 Name Default 0 0 0 0 C1MRPR 0 C1HWPR 0 C1MHPR 0 C1HRPR 0 Bit 3: MAC Read Pointer Reset (C1MRPR) Setting this bit to 1 resets the receive queue read pointer for connection 1. This queue pointer must be reset after a disconnect and before a connection.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 GL.BISTPF BIST Pass-Fail 21h 6 0 5 0 4 0 3 0 2 0 1 BISTDN 0 0 BISTPF 0 Bit 1: BIST DONE (BISTDN) If this bit is set to 1, the DS33R11 has completed the BIST Test initiated by BISTE. The pass fail result is available in BISTPF. Bit 0: BIST Pass-Fail (BISTPF) This bit is equal to 0 after the DS33R11 performs BIST testing on the SDRAM and the test passes.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 GL.SDMODE2 Global SDRAM Mode Register 2 3Bh 6 0 5 0 4 0 3 0 2 LTMOD2 0 1 LTMOD1 1 0 LTMOD0 0 Bits 0 - 2: CAS Latency Mode (LTMOD0 - LTMOD2) These bits are used to setup CAS Latency Note: Only CAS Latency of 2 or 3 is allowed Note: This register has a nonzero default value. This should be taken into consideration when initializing the device.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.3 Arbiter Registers The Arbiter manages the transport between the Ethernet port and the Serial Interface. It is responsible for queuing and dequeuing data to an external SDRAM. The arbiter handles requests from the HDLC and MAC to transfer data to/from the SDRAM. The base address of the Arbiter register space is 0040h. 11.3.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.4 BERT Registers Register Name: Register Description: Register Address: Bit # Name Default 7 0 BCR BERT Control Register 80h 6 PMU 0 5 RNPL 0 4 RPIC 0 3 MPR 0 2 APRD 0 1 TNPL 0 0 TPIC 0 Bit 7: This bit must be kept low for proper operation. Bit 6: Performance Monitoring Update (PMU) This bit causes a performance monitoring update to be initiated.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 BPCLR BERT Pattern Configuration Low Register 82h 6 QRSS 0 5 PTS 0 4 PLF4 0 3 PLF3 0 2 PLF2 0 1 PLF1 0 0 PLF0 0 Bit 6: QRSS Enable (QRSS) When 0, the pattern generator configuration is controlled by PTS, PLF[0:4], and PTF[0:4], and BSP[0:31]. When 1, the pattern generator configuration is forced to a QRSS pattern with a generating polynomial of x20 + x17 + 1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BSP7 0 BSPB0R BERT Pattern Byte0 Register 84h 6 BSP6 0 5 BSP5 0 4 BSP4 0 3 BSP3 0 2 BSP2 0 1 BSP1 0 0 BSP0 0 Bits 0 to 7: BERT Pattern (BSP[7:0]) Lower eight bits of 32 bits. Register description follows next register.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 TEICR Transmit Error Insertion Control Register 88h 6 0 5 TIER2 0 4 TIER1 0 3 TIER0 0 2 BEI 0 1 TSEI 0 0 0 Bits 3 to 5: Transmit Error Insertion Rate (TEIR[2:0]) These three bits indicate the rate at which errors are inserted in the output data stream. One out of every 10n bits is inverted. TEIR[2:0] is the value n.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 - BSRL BERT Status Register Latched 8Eh 6 - 5 - 4 - 3 PMSL - 2 BEL - 1 BECL - 0 OOSL - Bit 3: Performance Monitor Update Status Latched (PMSL) This bit is set when the PMS bit transitions from 0 to 1. Bit 2: Bit Error Detected Latched (BEL) This bit is set when a bit error is detected.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BEC7 0 RBECB0R Receive Bit Error Count Byte 0 Register 94h 6 BEC6 0 5 BEC5 0 4 BEC4 0 3 BEC3 0 2 BEC2 0 1 BEC1 0 0 BEC0 0 Bits 0 - 7: Bit Error Count (BEC[0:7]) Lower eight bits of 24 bits. Register description below.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BC15 0 RBCB1 Receive Bit Count Byte 1 Register #1 99h 6 BC14 0 5 BC13 0 4 BC12 0 3 BC11 0 2 BC10 0 1 BC9 0 0 BC8 0 1 BC17 0 0 BC16 0 Bits 0 - 7: Bit Count (BC[8:15]) Eight bits of a 32 bit value. Register description below.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.5 Serial Interface Registers The Serial Interface contains the Serial HDLC transport circuitry and the associated serial port. The Serial Interface register map consists of registers that are common functions, transmit functions, and receive functions. Bits that are underlined are read-only; all other bits can be written.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 LI.LPBK Serial Interface Loopback Control Register 0C2h 6 0 5 0 4 0 3 0 2 0 1 0 0 QLP 0 Bit 0: Queue Loopback Enable (QLP) If this bit set to 1, data received on the Serial Interface is looped back to the Serial Interface transmitter. Received data will not be sent from the Serial Interface to the Ethernet Interface.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TIFG7 0 LI.TIFGC Transmit Inter-Frame Gapping Control Register 0C5h 6 TIFG6 0 5 TIFG5 0 4 TIFG4 0 3 TIFG3 0 2 TIFG2 0 1 TIFG1 0 0 TIFG0 1 Bits 0 - 7: Transmit Inter-Frame Gapping (TIFG[7:0]) – These eight bits indicate the number of additional flags and bytes of inter-frame fill to be inserted between packets.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 MEIMS 0 LI.TEPHC Transmit Errored Packet High Control Register 0C7h 6 TPER6 0 5 TPER5 0 4 TPER4 0 3 TPER3 0 2 TPER2 0 1 TPER1 0 0 TPER0 0 Bit 7: Manual Error Insert Mode Select (MEIMS) – When 0, the transmit manual error insertion signal (TMEI) will not cause errors to be inserted.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 LI.TPPSR Transmit Packet Processor Status Register 0C8h 6 0 5 0 4 0 3 0 2 0 1 0 0 TEPF 0 Bit 0: Transmit Errored Packet Insertion Finished (TEPF) – This bit is set when the number of errored packets indicated by the TPEN[7:0] bits in the TEPC register have been transmitted.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TPC7 0 LI.TPCR0 Transmit Packet Count Byte 0 0CCh 6 TPC6 0 5 TPC5 0 4 TPC4 0 3 TPC3 0 2 TPC2 0 1 TPC1 0 0 TPC0 0 Bits 0 – 7: Transmit Packet Count (TPC[7:0]) – Eight bits of 24 bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 TPC15 0 LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TBC7 0 LI.TBCR0 Transmit Byte Count Byte 0 0D0h 6 TBC6 0 5 TBC5 0 4 TBC4 0 3 TBC3 0 2 TBC2 0 1 TBC1 0 0 TBC0 0 Bits 0 – 7: Transmit Byte Count (TBC[0:7]) – Eight bits of 32 bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 TBC15 0 LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 LI.THPMUU Serial Interface Transmit HDLC PMU Update Register 0D6h 6 0 5 0 4 0 3 0 2 0 1 0 0 TPMUU 0 Bit 0: Transmit PMU Update (TPMUU) This signal causes the transmit cell/packet processor block performance monitoring registers (counters) to be updated.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.5.2 X.86 Registers X.86 transmit and common registers are used to control the operation of the X.86 encoder and decoder. Register Name: Register Description: Register Address: Bit # Name Default 7 0 LI.TX86EDE X.86 Encoding Decoding Enable 0D8h 6 0 5 0 4 0 3 0 2 0 1 0 0 X86ED 0 Bit 0: X.86 Encoding Decoding (X86ED) If this bit is set to 1, X.86 encoding and decoding is enabled for the Transmit and Receive paths.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default LI.TRX86SAPIL Transmit Receive X.86 SAPIL 0DCh 7 6 5 4 3 2 1 0 TRSAPIL7 TRSAPIL6 TRSAPIL5 TRSAPIL4 TRSAPIL3 TRSAPIL2 TRSAPIL1 TRSAPIL0 0 0 0 0 0 0 0 1 Bits 0 – 7: X86 Transmit Receive Control (TRSAPIL0-7) This is the address field for the X.86 transmitter and expected value for the receiver.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.5.3 Receive Serial Interface Serial Receive Registers are used to control the HDLC Receiver associated with each Serial Interface. Note that throughout this document HDLC Processor is also referred to as “Packet Processor”. The receive packet processor block has seventeen registers. 11.5.3.1 Receive Serial Register Bit Descriptions Register Name: LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RMX7 1 LI.RMPSCL Receive Maximum Packet Size Control Low Register 102h 6 RMX6 1 5 RMX5 1 4 RMX4 0 3 RMX3 0 2 RMX2 0 1 RMX1 0 0 RMX0 0 Bits 0 - 7: Receive Maximum Packet Size (RMX[7:0]) Eight bits of a sixteen bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RMX15 0 LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 REPL - LI.RPPSRL Receive Packet Processor Status Register Latched 105h 6 RAPL - 5 RIPDL - 4 RSPDL - 3 RLPDL - 2 REPCL - 1 RAPCL - 0 RSPCL - Bit 7: Receive FCS Errored Packet Latched (REPL) This bit is set when a packet with an errored FCS is detected. Bit 6: Receive Aborted Packet Latched (RAPL) This bit is set when a packet with an abort indication is detected.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 REPIE 0 LI.RPPSRIE Receive Packet Processor Status Register Interrupt Enable 106h 6 RAPIE 0 5 RIPDIE 0 4 RSPDIE 0 3 RLPDIE 0 2 REPCIE 0 1 RAPCIE 0 0 RSPCIE 0 Bit 7: Receive FCS Errored Packet Interrupt Enable (REPIE) This bit enables an interrupt if the REPL bit in the LI.RPPSRL register is set.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RPC7 0 LI.RPCB0 Receive Packet Count Byte 0 Register 108h 6 RPC6 0 5 RPC5 0 4 RPC4 0 3 RPC3 0 2 RPC2 0 1 RPC1 0 0 RPC0 0 Bits 0 - 7: Receive Packet Count (RPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RPC15 0 LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RFPC7 0 LI.RFPCB0 Receive FCS Errored Packet Count Byte 0 Register 10Ch 6 RFPC6 0 5 RFPC5 0 4 RFPC4 0 3 RFPC3 0 2 RFPC2 0 1 RFPC1 0 0 RFPC0 0 Bits 0 – 7: Receive FCS Errored Packet Count (RFPC[7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RFPC15 0 LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RAPC7 0 LI.RAPCB0 Receive Aborted Packet Count Byte 0 Register 110h 6 RAPC6 0 5 RAPC5 0 4 RAPC4 0 3 RAPC3 0 2 RAPC2 0 1 RAPC1 0 0 RAPC0 0 Bits 0 - 7: Receive Aborted Packet Count (RAPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RAPC15 0 LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RSPC7 0 LI.RSPCB0 Receive Size Violation Packet Count Byte 0 Register 114h 6 RSPC6 0 5 RSPC5 0 4 RSPC4 0 3 RSPC3 0 2 RSPC2 0 1 RSPC1 0 0 RSPC0 0 Bits 0 - 7: Receive Size Violation Packet Count (RSPC [7:0]) Eight bits of a 24-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RSPC15 0 LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RBC7 0 LI.RBC0 Receive Byte Count 0 Register 118h 6 RBC6 0 5 RBC5 0 4 RBC4 0 3 RBC3 0 2 RBC2 0 1 RBC1 0 0 RBC0 0 Bits 0 - 7: Receive Byte Count (RBC [7:0]) Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RBC15 0 LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 REBC7 0 LI.RAC0 Receive Aborted Byte Count 0 Register 11Ch 6 REBC6 0 5 REBC5 0 4 REBC4 0 3 REBC3 0 2 REBC2 0 1 REBC1 0 0 REBC0 0 Bits 0 - 7: Receive Aborted Byte Count (RBC [7:0]) Eight bits of a 32-bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 REBC15 0 LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default LI.RHPMUU Serial Interface Receive HDLC PMU Update Register 120h 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 RPMUU 0 Bit 0: Receive PMU Update (RPMUU) This signal causes the receive cell/packet processor block performance monitoring registers (counters) to be updated.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LI.RX86LSIE Receive X.86 Interrupt Enable 123h Bit # Name 7 - 6 - 5 - 4 - 3 SAPINE01IM 2 SAPINEFEIM Default 0 0 0 0 0 0 1 CNE3LI M 0 0 ANE4IM 0 Bit 3: SAPI Octet not equal to LI.TRX86SAPIH Interrupt Enable (SAPINE01IM) If this bit is set to 1, LI.RX86S.SAPIHNE will generate an interrupt. Bit 2: SAPI Octet not equal to LI.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 LI.TQTIE Serial Interface Transmit Queue Cross Threshold Interrupt Enable 126h 6 0 5 0 4 0 3 TFOVFIE 0 2 TQOVFIE 0 1 TQHTIE 0 0 TQLTIE 0 Bit 3: Transmit FIFO Overflow for Connection Interrupt Enable (TFOVFIE) If this bit is set, the watermark interrupt is enabled for TFOVFLS.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.6 Ethernet Interface Registers The Ethernet Interface registers are used to configure RMII/MII bus operation and establish the MAC parameters as required by the user. The MAC Registers cannot be addressed directly from the Processor port. The registers below are used to perform indirect read or write operations to the MAC registers. The MAC Status Registers are shown in Table 11-7. Accessing the MAC Registers is described in the Section 9.15.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default SU.MACRD1 MAC Read Data Byte 1 143h 7 6 5 4 3 2 1 0 MACRD15 MACRD14 MACRD13 MACRD12 MACRD11 MACRD10 MACRD9 MACRD8 0 0 0 0 0 0 0 0 Bits 0 - 7: MAC Read Data 1 (MACRD8-15) One of four bytes of data read from the MAC. Valid after a read command has been issued and the SU.MACRWC.MCS bit is zero.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default SU.MACWD1 MAC Write Data 1 147h 7 6 5 4 3 2 1 0 MACWD15 MACWD14 MACWD13 MACWD12 MACWD11 MACWD10 MACWD09 MACWD08 0 0 0 0 0 0 0 0 Bits 0 – 7: MAC Write Data 1 (MACWD8-15) One of four bytes of data to be written to the MAC. Data has been written after a write command has been issued and the SU.MACRWC.MCS bit is zero.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default SU.MACAWH MAC Address Write High 14Bh 7 6 5 4 3 2 1 0 MACAW 15 MACAW 14 MACAW 13 MACAW12 MACAW11 MACAW10 MACAW9 MACAW8 0 0 0 0 0 0 0 0 Bits 0 – 7: MAC Write Address (MACAW8-15) High byte of the MAC indirect write address. Used only for write operations. Register Name: Register Description: Register Address: Bit # Name Default 7 0 SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 SU.LPBK Ethernet Interface Loopback Control Register 14Fh 6 0 5 0 4 0 3 0 2 0 1 0 0 QLP 0 Bit 0: Queue Loopback Enable (QLP) If this bit is set to 1, data from the Ethernet Interface receive queue is looped back to the transmit queue. Buffered data from the serial interface will remain until the loopback is removed.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 SU.TFRC Transmit Frame Resend Control 151h 6 0 5 0 4 0 3 NCFQ 0 2 TPDFCB 0 1 TPRHBC 0 0 TPRCB 0 Bit 3: No Carrier Queue Flush Bar (NCFQ) If this bit is set to 1, the queue for data passing from Serial Interface to Ethernet Interface will not be flushed when loss of carrier is detected.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 UR 0 SU.TFSL Transmit Frame Status Low 152h 6 EC 0 5 LC 0 4 ED 0 3 LOC 0 2 NOC 0 1 0 0 FABORT 0 Bit 7: Under Run (UR) When this bit is set to 1, the frame was aborted due to a data under run condition of the transmit buffer.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 FL7 0 SU.RFSB0 Receive Frame Status Byte 0 154h 6 FL6 0 5 FL5 0 4 FL4 0 3 FL3 0 2 FL2 0 1 FL1 0 0 FL0 0 Bits 0 - 7: Frame Length (FL[0:7]) These 8 bits are the low byte of the length (in bytes) of the received frame, with FCS and Padding. If Automatic Pad Stripping is enabled, this value is the length of the received packet without PCS or Pad bytes.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 MF 0 SU.RFSB3 Receive Frame Status Byte 3 157h 6 0 5 0 4 BF 0 3 MCF 0 2 UF 0 1 CF 0 0 LE 0 Bit 7: Missed Frame (MF) This bit is set to 1 if the packet is not successfully received from the MAC by the packet Arbiter. Bit 4: Broadcast Frame (BF) This bit is set to 1 if the current frame is a broadcast frame.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RMPS7 1 SU.RMFSRL Receiver Maximum Frame Low Register 158h 6 RMPS6 1 5 RMPS5 1 4 RMPS4 0 3 RMPS3 0 2 RMPS2 0 1 RMPS1 0 0 RMPS0 0 Bits 7- 0: Receiver Maximum Frame (RMPS[0:7]) Eight bits of sixteen bit value. Register description below. Register Name: Register Description: Register Address: Bit # Name Default 7 RMPS15 0 SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default SU.QRIE Receive Queue Cross Threshold enable 15Ch 7 0 6 0 5 0 4 0 3 RFOVFIE 0 2 RQVFIE 0 1 RQLTIE 0 0 RQHTIE 0 Bit 3: Receive FIFO Overflow Interrupt Enable (RFOVFIE) If this bit is set, the interrupt is enabled for RFOVFLS. Bit 2: Receive Queue Overflow Interrupt Enable (RQVFIE) If this bit is set, the interrupt is enabled for RQOVFLS.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 SU.RFRC Receive Frame Rejection Control 15Eh 6 UCFR 0 5 CFRR 0 4 LERR 0 3 CRCERR 0 2 DBR 0 1 MIIER 0 0 BFR 0 Bit 6: Uncontrolled Control Frame Reject (UCFR) When set to 1, Control Frames other than Pause Frames are allowed. When this bit is equal to zero, nonpause control frames are rejected.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.6.2 MAC Registers The control Registers related to the control of the individual Mac’s are shown in the following Table. The DS33R11 keeps statistics for the packet traffic sent and received. The register address map is shown in the following Table. Note that the addresses listed are the indirect addresses that must be provided to SU.MACRADH/SU.MACRADL or SU.MACAWH/SU.MACAWL. Register Name: Register Description: Register Address: SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Bit 12: Late Collision Control (LCC) When set to 1, enables retransmission of a collided packet even after the collision period. When this bit is clear, retransmission of late collisions is disabled. Bit 10: Disable Retry (DRTY) When set to 1, the MAC makes only a single attempt to transmit each frame. If a collision occurs, the MAC ignores the current frame and proceeds to the next frame.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Reserved MAC Reserved Control Register 010Ch (indirect) 010Ch: Bit # Name Default 31 Reserved 0 30 Reserved 0 29 Reserved 0 28 Reserved 0 27 Reserved 0 26 Reserved 0 25 Reserved 0 24 Reserved 0 010Dh: Bit # Name Default 23 Reserved 0 22 Reserved 0 21 Reserved 0 20 Reserved 0 19 Reserved 0 18 Reserved 0 17 Reserved 0 16 Reserved 0 010Eh: Bit # Name Default 15 Reserved 0 1
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Reserved MAC Reserved Control Register 0110h (indirect) 0110h: Bit # Name Default 31 Reserved 0 30 Reserved 0 29 Reserved 0 28 Reserved 0 27 Reserved 0 26 Reserved 0 25 Reserved 0 24 Reserved 0 0111h: Bit # Name Default 23 Reserved 0 22 Reserved 0 21 Reserved 0 20 Reserved 0 19 Reserved 0 18 Reserved 0 17 Reserved 0 16 Reserved 0 0112h: Bit # Name Default 15 Reserved 0 1
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: 0200h: Bit # Name Default 0201h: Bit # Name Default 0202h: Bit # Name Default 0203h: Bit # Name Default SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: 0204h: Bit # Name Default 0205h: Bit # Name Default 0206h: Bit # Name Default 0207h: Bit # Name Default SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: 0300h: Bit # Name Default 0301h: Bit # Name Default 0302h: Bit # Name Default 0303h: Bit # Name Default SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: 0308h: Bit # Name Default 0309h: Bit # Name Default 030Ah: Bit # Name Default 030Bh: Bit # Name Default SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: 030Ch: Bit # Name Default 030Dh: Bit # Name Default 030Eh: Bit # Name Default 030Fh: Bit # Name Default SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: 0334h: Bit # Name Default 0335h: Bit # Name Default 0336h: Bit # Name Default 0337h: Bit # Name Default SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: 0338h: Bit # Name Default 0339h: Bit # Name Default 033Ah: Bit # Name Default 033Bh: Bit # Name Default SU.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.7 T1/E1/J1 Transceiver Registers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.MSTRREG Master Mode Register 00h 6 — 0 5 — 0 4 — 0 3 TEST1 0 2 TEST0 0 1 T1/E1 0 0 SFTRST 0 Bits 2 – 3: Test Mode Bits (TEST0, TEST1) Test modes are used to force the output pins of the transceiver into known states.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.IOCR1 I/O Configuration Register 1 01h Bit # Name Default 6 RSMS2 0 7 RSMS 0 5 RSMS1 0 4 RSIO 0 3 TSDW 0 2 TSM 0 1 TSIO 0 0 ODF 0 Bit 7: RSYNC Multiframe Skip Control (RSMS) Useful in framing format conversions from D4 to ESF. This function is not available when the receive-side elastic store is enabled. RSYNC must be set to output multiframe pulses (TR.IOCR1.5 = 1 and TR.IOCR1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.IOCR2 I/O Configuration Register 2 02h Bit # Name Default 6 TCLKINV 0 7 RCLKINV 0 5 RSYNCINV 0 4 TSYNCINV 0 Bit 7: RCLKO Invert (RCLKINV) 0 = no inversion 1 = inverts signal on RCLKO output. Bit 6: TCLKT Invert (TCLKINV) 0 = no inversion 1 = inverts signal on TCLKT input.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.T1RCR2 T1 Receive Control Register 2 04h 6 RFM 0 5 RB8ZS 0 4 RSLC96 0 3 RZSE 0 2 — 0 1 RJC 0 0 RD4YM 0 Bit 6: Receive Frame Mode Select (RFM) 0 = D4 framing mode 1 = ESF framing mode Bit 5: Receive B8ZS Enable (RB8ZS) 0 = B8ZS disabled 1 = B8ZS enabled Bit 4: Receive SLC-96 Enable (RSLC96). Only set this bit to a 1 in D4/SLC-96 framing applications.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TJC 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.T1TCR2 T1 Transmit Control Register 2 06h Bit # Name Default 6 TSLC96 0 7 TB8ZS 0 5 TZSE 0 4 FBCT2 0 3 FBCT1 0 2 TD4YM 0 1 — 0 0 TB7ZS 0 Bit 7: Transmit B8ZS Enable (TB8ZS) 0 = B8ZS disabled 1 = B8ZS enabled Bit 6: Transmit SLC-96/Fs-Bit Insertion Enable (TSLC96). Only set this bit to a 1 in D4 framing applications. Must be set to 1 to source the Fs pattern from the TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.T1CCR1 T1 Common Control Register 1 07h 6 — 0 5 — 0 4 TRAI-CI 0 3 TAIS-CI 0 2 TFM 0 1 PDE 0 0 TLOOP 0 Bit 4: Transmit RAI-CI Enable (TRAI-CI). Setting this bit causes the ESF RAI-CI code to be transmitted in the FDL bit position. 0 = do not transmit the ESF RAI-CI code 1 = transmit the ESF RAI-CI code Bit 3: Transmit AIS-CI Enable (TAIS-CI).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 CH7 0 TR.SSIE1 (E1 Mode) Software Signaling Insertion Enable 1 08h 6 CH6 0 5 CH5 0 4 CH4 0 3 CH3 0 2 CH2 0 1 CH1 0 0 UCAW 0 Bits 1 – 7: Software Signaling-Insertion Enable for Channels 1 to 7 (CH1 to CH7). These bits determine which channels are to have signaling inserted from the transmit signaling registers. 0 = do not source signaling data from the TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 TR.SSIE3 (T1 Mode) Software Signaling-Insertion Enable 3 0Ah 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 Bits 0 – 7: Software Signaling Insertion Enable for Channels 17 to 24 (CH17 to CH24). These bits determine which channels are to have signaling inserted from the transmit signaling registers.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 ID7 1 TR.IDR Device Identification Register 0Fh 6 ID6 0 5 ID5 1 4 ID4 1 3 ID3 X 2 ID2 X 1 ID1 X 0 ID0 X Bits 4 - 7: Device ID (ID4 to ID7). The upper four bits of TR.IDR are used to display the transceiver ID. Bits 0 – 3: Chip Revision Bits (ID0 to ID3). The lower four bits of TR.IDR are used to display the die revision of the chip.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BSYNC 0 TR.INFO2 Information Register 2 11h 6 BD 0 5 TCLE 0 4 TOCD 0 3 RL3 0 2 RL2 0 1 RL1 0 0 RL0 0 Bit 7: BERT Real-Time Synchronization Status (BSYNC). Real-time status of the synchronizer (this bit is not latched). This bit is set when the incoming pattern matches for 32 consecutive bit positions.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.INFO3 Information Register 3 12h 6 — 0 5 — 0 4 — 0 3 — 0 2 CRCRC 0 1 FASRC 0 0 CASRC 0 Bit 2: CRC Resync Criteria Met Event (CRCRC). Set when 915/1000 codewords are received in error. Bit 1: FAS Resync Criteria Met Event (FASRC). Set when three consecutive FAS words are received in error.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.SR1 Status Register 1 16h Bit # Name Default 6 TIMER 0 7 ILUT 0 5 RSCOS 0 4 JALT 0 3 LRCL 0 2 TCLE 0 1 TOCD 0 0 LOLITC 0 Bit 7: Input Level Under Threshold (ILUT). This bit is set whenever the input level at RTIP and RRING falls below the threshold set by the value in TR.CCR4.4 through TR.CCR4.7.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.SR2 Status Register 2 18h Bit # Name Default 6 RUA1C 0 7 RYELC 0 5 FRCLC 0 4 RLOSC 0 3 RYEL 0 2 RUA1 0 1 FRCL 0 0 RLOS 0 Bit 7: Receive Yellow Alarm Clear Event (RYELC) (T1 Only). Set when the receive Yellow Alarm condition is no longer detected. Bit 6: Receive Unframed All-Ones Clear Event (RUA1C). Set when the unframed all 1s condition is no longer detected.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 LSPARE 0 TR.SR3 Status Register 3 1Ah 6 LDN 0 5 LUP 0 4 LOTC 0 3 LORC 0 2 V52LNK 0 1 RDMA 0 0 RRA 0 Bit 7: Spare Code Detected Condition (LSPARE) (T1 Only). Set when the spare code as defined in the TR.RSCD1/2 registers is being received. See Section 10.19 for details. This is a double interrupt bit. See Section 9.7.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 LSPARE 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RAIS-CI 0 TR.SR4 Status Register 4 1Ch 6 RSAO 0 5 RSAZ 0 4 TMF 0 3 TAF 0 2 RMF 0 1 RCMF 0 0 RAF 0 Bit 7: Receive AIS-CI Event (RAIS-CI) (T1 Only). Set when the receiver detects the AIS-CI pattern as defined in ANSI T1.403. Bit 6: Receive Signaling All-Ones Event (RSAO) (E1 Only).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RAIS-CI 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.SR5 Status Register 5 1Eh 6 — 0 5 TESF 0 4 TESEM 0 3 TSLIP 0 2 RESF 0 1 RESEM 0 0 RSLIP 0 Bit 5: Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is deleted. Bit 4: Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a frame is repeated.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.SR6, TR.SR7 HDLC #1 Status Register 6 HDLC #2 Status Register 7 20h, 22h Bit # Name Default 6 TMEND 0 7 — 0 5 RPE 0 4 RPS 0 3 RHWM 0 2 RNE 0 1 TLWM 0 0 TNF 0 Bit 6: Transmit Message-End Event (TMEND). Set when the transmit HDLC controller has finished sending a message. This is a latched bit and is cleared when read. Bit 5: Receive Packet-End Event (RPE).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.IMR6, TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: TR.INFO5, TR.INFO6 HDLC #1 Information Register HDLC #2 Information Register 2Eh, 2Fh Register Address: Bit # Name Default 7 — 0 6 — 0 5 TEMPTY 0 4 TFULL 0 3 REMPTY 0 2 PS2 0 1 PS1 0 0 PS0 0 Bit 5: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty. Bit 4: Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.SR8 Status Register 8 24h 6 — 0 5 BOCC 0 4 RFDLAD 0 3 RFDLF 0 2 TFDLE 0 1 RMTCH 0 0 RBOC 0 Bit 5: BOC Clear Event (BOCC). Set when 30 FDL bits occur without an abort sequence. Bit 4: RFDL Abort Detect Event (RFDLAD). Set when eight consecutive 1s are received on the FDL. Bit 3: RFDL Register Full Event (RFDLF). Set when the receive FDL buffer (TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.SR9 Status Register 9 26h 6 BBED 0 5 BBCO 0 4 BEC0 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0 Bit 6: BERT Bit-Error Detected (BED) Event (BBED). A latched bit that is set when a bit error is detected. The receive BERT must be in synchronization for it to detect bit errors. Cleared when read. Bit 5: BERT Bit-Counter Overflow Event (BBCO).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — CH8 Register Name: Register Description: Register Address: Bit # Name Default 7 — CH16 Register Name: Register Description: Register Address: Bit # Name Default 7 — CH24 Register Name: Register Description: Register Address: Bit # Name Default 7 — CH32 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 CSC5 0 TR.INFO7 Information Register 7 (Real-Time, Non-Latched Register) 30h 6 CSC4 0 5 CSC3 0 4 CSC2 0 3 CSC0 0 2 FASSA 0 1 CASSA 0 0 CRC4SA 0 Bits 3 – 7: CRC4 Sync Counter Bits (CSC0, CSC2 to CSC4). The CRC4 sync counter increments each time the 8ms CRC4 multiframe search times out.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TFPT 0 TR.E1TCR1 E1 Transmit Control Register 1 35h 6 T16S 0 5 TUA1 0 4 TSiS 0 3 TSA1 0 2 THDB3 0 1 TG802 0 0 TCRC4 0 Bit 7: Transmit Time Slot 0 Pass-Through (TFPT) 0 = FAS bits/Sa bits/remote alarm sourced internally from the TR.TAF and TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH7 CH15 CH23 TR.RSINFO1, TR.RSINFO2, TR.RSINFO3, TR.RSINFO4 Receive Signaling Change-of-State Information 38h, 39h, 3Ah, 3Bh CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 RSINFO1 RSINFO2 RSINFO3 RSINFO4 When a channel’s signaling data changes state, the respective bit in registers TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.SIGCR Signaling Control Register 40h Bit # Name Default 6 — 0 7 GRSRE 0 5 — 0 4 RFE 0 3 RFF 0 2 RCCS 0 1 TCCS 0 0 FRSAO 0 Bit 7: Global Receive Signaling Reinsertion Enable (GRSRE). This bit allows the user to reinsert all signaling channels without programming all channels through the per-channel function.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.ERCNT Error-Counter Configuration Register 41h 6 MECU 0 5 ECUS 0 4 EAMS 0 3 VCRFS 0 2 FSBE 0 1 MOSCRF 0 0 LCVCRF 0 Bit 6: Manual Error-Counter Update (MECU). When enabled by TR.ERCNT.4, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error-counter registers with the latest counts and reset the counters.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.LCVCR1 Line-Code Violation Count Register 1 42h Bit # Name Default 6 LCVC14 0 7 LCVC15 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCVC8 0 Bits 0 – 7: Line-Code Violation Counter Bits 8 to 15 (LCVC8 to LCVC15). LCVC15 is the MSB of the 16-bit code violation count. Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.FOSCR1 Frames Out-of-Sync Count Register 1 46h Bit # Name Default 6 FOS14 0 7 FOS15 0 5 FOS13 0 4 FOS12 0 3 FOS11 0 2 FOS10 0 1 FOS9 0 0 FOS8 0 Bits 0 – 7: Frames Out-of-Sync Counter Bits 8 to 15 (FOS8 to FOS15). FOS15 is the MSB of the 16-bit frames out-of-sync count. Register Name: Register Description: Register Address: Bit # Name Default 7 FOS7 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.LBCR Loopback Control Register 4Ah 6 — 0 5 — 0 4 LIUC 0 3 LLB 0 2 RLB 0 1 PLB 0 0 FLB 0 Bit 4: Line Interface Unit Mux Control (LIUC). This is a software version of the LIUC pin. When the LIUC pin is connected high, the LIUC bit has control. When the LIUC pin is connected low, the framer and LIU are separated and the LIUC bit has no effect.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TESALGN 0 TR.ESCR Elastic Store Control Register 4Fh 6 TESR 0 5 TESMDM 0 4 TESE 0 3 RESALGN 0 2 RESR 0 1 RESMDM 0 0 RESE 0 Bit 7: Transmit Elastic Store Align (TESALGN). Setting this bit from a 0 to a 1 forces the transmit elastic store’s write/read pointers to a minimum separation of half a frame.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: (MSB) 0 CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH26-A CH28-A CH30-A 0 CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B CH26-B CH28-B CH30-B TR.TS1 to TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: (MSB) 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122 TR.TS1 to TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B TR.TS1 to TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B TR.TS1 to TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: (MSB) 0 CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH26-A CH28-A CH30-A 0 CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B CH26-B CH28-B CH30-B Register Name: Register Description: Register Address: (MSB) 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122 TR.RS1 to TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.CCR1 Common Control Register 1 70h Bit # Name Default 6 CRC4R 0 7 MCLKS 0 5 SIE 0 4 ODM 0 3 DICAI 0 2 TCSS1 0 1 TCSS0 0 0 RLOSF 0 Bit 7: MCLK Source (MCLKS).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default TR.CCR2 Common Control Register 2 71h 7 — 0 6 — 0 5 — 0 4 — 0 3 — 0 2 BPCS1 0 1 BPCS0 0 0 BPEN 0 Bits 1 – 2: Backplane Clock Selects (BPCS0, BPCS1) BPCS1 BPCS0 BPCLK Frequency (MHz) 0 0 1 1 0 1 0 1 16.384 8.192 4.096 2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RLT3 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 B1 0 TR.TDS0M Transmit DS0 Monitor Register 75h 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bits 0 – 7: Transmit DS0 Channel Bits (B1 to B8). Transmit channel data that has been selected by the transmit channel monitor select register. B8 is the LSB of the DS0 channel (last bit to be transmitted).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 L2 0 TR.LIC1 Line Interface Control 1 78h 6 L1 0 5 L0 0 4 EGL 0 3 JAS 0 2 JABDS 0 1 DJA 0 0 TPD 0 Bits 5 – 7: Line Build-Out Select (L0 to L2). When using the internal termination, the user needs only to select 000 for 75Ω operation or 001 for 120Ω operation below. This selects the proper voltage levels for 75Ω or 120Ω operation. Using TT0 and TT1 of the TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.TLBC Transmit Line Build-Out Control 7Dh 6 AGCE 0 5 GC5 0 4 GC4 0 3 GC3 0 2 GC2 0 1 GC1 0 0 GC0 0 Bit 6: Automatic Gain Control Enable (AGCE). 0 = use Transmit AGC, TR.TLBC bits 0–5 are “don’t care” 1 = do not use Transmit AGC, TR.TLBC bits 0–5 set nominal level Bits 0–5: Gain Control Bits (GC0–GC5).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 ETS 0 TR.LIC2 Line Interface Control 2 79h 6 LIRST 0 5 IBPV 0 4 TUA1 0 3 JAMUX 0 2 — 0 1 SCLD 0 0 CLDS 0 Bit 7: E1/T1 Select (ETS) 0 = T1 mode selected 1 = E1 mode selected Bit 6: Line Interface Reset (LIRST). Setting this bit from a 0 to a 1 initiates an internal reset that resets the clock recovery state machine and recenters the jitter attenuator.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.LIC3 Line Interface Control 3 7Ah 6 TCES 0 5 RCES 0 4 MM1 0 3 MM0 0 2 RSCLKE 0 1 TSCLKE 0 0 TAOZ 0 Bit 6: Transmit-Clock Edge Select (TCES). Selects which TDCLKI edge to sample TPOSI and TNEGI. 0 = sample TPOSI and TNEGI on falling edge of TDCLKI 1 = sample TPOSI and TNEGI on rising edge of TDCLKI Bit 5: Receive-Clock Edge Select (RCES).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default TR.LIC4 Line Interface Control 4 7Bh 7 CMIE 0 6 CMII 0 5 MPS1 0 4 MPS0 0 3 TT1 0 Bit 7: CMI Enable (CMIE) 0 = disable CMI mode 1 = enable CMI mode Bit 6: CMI Invert (CMII) 0 = CMI normal at TTIP and RTIP 1 = invert CMI signal at TTIP and RTIP Bits 4 – 5: MCLK Prescaler T1 Mode: MCLK (MHz) MPS1 MPS0 1.544 3.088 6.176 12.352 2.048 4.096 8.192 16.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 GRIC 0 TR.IAAR Idle Array Address Register 7Eh 6 GTIC 0 5 IAA5 0 4 IAA4 0 3 IAA3 0 2 IAA2 0 1 IAA1 0 0 IAA0 0 Bit 7: Global Receive-Idle Code (GRIC). Setting this bit causes all receive channels to be set to the idle code written to the TR.PCICR register. This bit must be set = 0 for read operations.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 CH16 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 CH16 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 CH16 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.H1TC, TR.H2TC HDLC #1 Transmit Control HDLC #2 Transmit Control 90h, A0h Bit # Name Default 6 TEOML 0 7 NOFS 0 5 THR 0 4 THMS 0 3 TFS 0 2 TEOM 0 1 TZSD 0 0 TCRCD 0 Bit 7: Number of Flags Select (NOFS) 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages Bit 6: Transmit End of Message and Loop (TEOML).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default TR.H1FC, TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RHCS7 0 TR.H1RCS1, TR.H1RCS2, TR.H1RCS3, TR.H1RCS4 TR.H2RCS1, TR.H2RCS2, TR.H2RCS3, TR.H2RCS4 HDLC # 1 Receive Channel Select HDLC # 2 Receive Channel Select 92h, 93h, 94h, 95h A2h, A3h, A4h, A5h 6 RHCS6 0 5 RHCS5 0 4 RHCS4 0 3 RHCS3 0 2 RHCS2 0 Bit 7: Receive HDLC Channel Select Bit 7 (RHCS7). Select Channel 8, 16, 24, or 32.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.H1RTSBS, TR.H2RTSBS HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6h Bit # Name Default 6 RCB7SE 0 7 RCB8SE 0 5 RCB6SE 0 4 RCB5SE 0 3 RCB4SE 0 2 RCB3SE 0 1 RCB2SE 0 0 RCB1SE 0 Bit 7: Receive Channel Bit 8 Suppress Enable (RCB8SE). MSB of the channel. Set to 1 to stop this bit from being used.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 THCS7 0 TR.H1TCS1, TR.H1TCS2, TR.H1TCS3, TR.H1TCS4 TR.H2TCS1, TR.H2TCS2, TR.H2TCS3, TR.H2TCS4 HDLC # 1 Transmit Channel Select HDLC # 2 Transmit Channel Select 97h, 98h, 99h, 9Ah A7h, A8h, A9h, AAh 6 THCS6 0 5 THCS5 0 4 THCS4 0 3 THCS3 0 2 THCS2 0 Bit 7: Transmit HDLC Channel Select Bit 7 (THCS7). Select Channel 8, 16, 24, or 32.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.H1TTSBS, TR.H2TTSBS HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select 9Bh, ABh Bit # Name Default 6 TCB7SE 0 7 TCB8SE 0 5 TCB6SE 0 4 TCB5SE 0 3 TCB4SE 0 2 TCB3SE 0 1 TCB2SE 0 0 TCB1SE 0 Bit 7: Transmit Channel Bit 8 Suppress Enable (TCB1SE). MSB of the channel. Set to 1 to stop this bit from being used.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 THD7 0 TR.H1TF, TR.H2TF HDLC # 1 Transmit FIFO HDLC # 2 Transmit FIFO 9Dh, ADh 6 THD6 0 5 THD5 0 4 THD4 0 3 THD3 0 2 THD2 0 1 THD1 0 0 THD0 0 2 RHD2 0 1 RHD1 0 0 RHD0 0 Bit 7: Transmit HDLC Data Bit 7 (THD7). MSB of an HDLC packet data byte.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.H1TFBA, TR.H2TFBA HDLC # 1 Transmit FIFO Buffer Available HDLC # 2 Transmit FIFO Buffer Available 9Fh, Afh Bit # Name Default 6 TFBA6 0 7 TFBA7 0 5 TFBA5 0 4 TFBA4 0 3 TFBA3 0 2 TFBA2 0 1 TFBA1 0 0 TFBA0 0 1 RDN1 0 0 RDN0 0 Bits 0 – 7: Transmit FIFO Bytes Available (TFBAO to TFBA7). TFBA0 is the LSB.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 TR.TCD1 Transmit Code-Definition Register 1 B7h 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 1 C1 0 0 C0 0 Bit 7: Transmit Code-Definition Bit 7 (C7). First bit of the repeating pattern. Bits 3 – 6: Transmit Code-Definition Bits 3–6 (C3–C6) Bit 2: Transmit Code-Definition Bit 2 (C2). A don’t care if a 5-bit length is selected.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.RUPCD1 Receive Up-Code Definition Register 1 B9h Bit # 7 6 5 4 3 Name C7 C6 C5 C4 C3 Default 0 0 0 0 0 Note: Writing this register resets the detector’s integration period. 2 C2 0 1 C1 0 0 C0 0 Bit 7: Receive Up-Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Up-Code Definition Bit 6 (C6). A don’t care if a 1-bit length is selected.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.RDNCD1 Receive Down-Code Definition Register 1 BBh Bit # 7 6 5 4 3 Name C7 C6 C5 C4 C3 Default 0 0 0 0 0 Note: Writing this register resets the detector’s integration period. 2 C2 0 1 C1 0 0 C0 0 Bit 7: Receive Down-Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Down-Code Definition Bit 6 (C6). A don’t care if a 1-bit length is selected.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.RSCD1 Receive Spare-Code Definition Register 1 BEh Bit # 7 6 5 4 3 Name C7 C6 C5 C4 C3 Default 0 0 0 0 0 Note: Writing this register resets the detector’s integration period. 2 C2 0 1 C1 0 0 C0 0 Bit 7: Receive Spare-Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Spare-Code Definition Bit 6 (C6). A don’t care if a 1-bit length is selected.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default TR.RFDL (TR.BOCC.4 = 1) Receive FDL Register C0h 7 — 0 6 — 0 5 RBOC5 0 4 RBOC4 0 3 RBOC3 0 2 RBOC2 0 1 RBOC1 0 0 RBOC0 0 3 RFDL3 0 2 RFDL2 0 1 RFDL1 0 0 RFDL0 0 RFDL register bit definitions when TR.BOCC.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.TFDL Transmit FDL Register C1h Bit # 7 6 5 4 3 Name TFDL7 TFDL6 TFDL5 TFDL4 TFDL3 Default 0 0 0 0 0 Note: Also used to insert Fs framing pattern in D4 framing mode. 2 TFDL2 0 1 TFDL1 0 0 TFDL0 0 The transmit FDL register (TR.TFDL) contains the FDL information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 SiF0 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TSiF0 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 SiAF 0 TR.TSACR Transmit Sa Bit Control Register DAh 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 1 ACNT1 0 0 ACNT0 0 Bit 7: International Bit in Align Frame Insertion Control Bit (SiAF) 0 = do not insert data from the TR.TSiAF register into the transmit data stream 1 = insert data from the TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TR.BRP1 BERT Repetitive Pattern Set Register 1 DCh Bit # Name Default 6 RPAT6 0 7 RPAT7 0 5 RPAT5 0 4 RPAT4 0 3 RPAT3 0 2 RPAT2 0 1 RPAT1 0 0 RPAT0 0 Bits 0 – 7: BERT Repetitive Pattern Set Bits 0 to 7 (RPAT0 to RPAT7) RPAT0 is the LSB of the 32-bit repetitive pattern set. Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TC 0 TR.BC1 BERT Control Register 1 E0h 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0 Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 EIB2 0 TR.BC2 BERT Control Register 2 E1h 6 EIB1 0 5 EIB0 0 4 SBE 0 3 RPL3 0 2 RPL2 0 1 RPL1 0 0 RPL0 0 Bits 5 – 7: Error Insert Bits 0 to 2 (EIB0 to EIB2). Automatically inserts bit errors at the prescribed rate into the generated data pattern. Can be used for verifying error-detection features.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BBC7 0 TR.BBC1 BERT Bit Count Register 1 E3h 6 BBC6 0 5 BBC5 0 4 BBC4 0 3 BBC3 0 2 BBC2 0 1 BBC1 0 0 BBC0 0 Bits 0 – 7: BERT Bit Counter Bits 0 to 7 (BBC0 to BBC7). BBC0 is the LSB of the 32-bit counter. Register Name: Register Description: Register Address: TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 EC7 0 TR.BEC1 BERT Error-Count Register 1 E7h 6 EC6 0 5 EC5 0 4 EC4 0 3 EC3 0 2 EC2 0 1 EC1 0 0 EC0 0 Bits 0 – 7: Error Counter Bits 0 to 7 (EC0 to EC7). EC0 is the LSB of the 24-bit counter. Register Name: Register Description: Register Address: Bit # Name Default 7 EC15 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.BIC BERT Interface Control Register EAh 6 RFUS 0 5 — 0 4 TBAT 0 3 TFUS 0 2 — 0 1 BERTDIR 0 0 BERTEN 0 Bit 6: Receive Framed/Unframed Select (RFUS) 0 = BERT is not sent data from the F-bit position (framed) 1 = BERT is sent data from the F-bit position (unframed) Bit 4: Transmit Byte-Align Toggle (TBAT).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 WNOE 0 TR.ERC Error-Rate Control Register EBh 6 — 0 5 — 0 4 CE 0 3 ER3 0 2 ER2 0 1 ER1 0 0 ER0 0 Bit 7: Write NOE Registers (WNOE). If the host wishes to update to the TR.NOEx registers, this bit must be toggled from a 0 to a 1 after the host has already loaded the prescribed error count into the TR.NOEx registers.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 TR.NOE1 Number-of-Errors 1 ECh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bits 0 – 7: Number-of-Errors Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter. Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 11.7.1 Number-of-Errors Left Register The host can read the TR.NOELx registers at any time to determine how many errors are left to be inserted. Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 TR.NOEL1 Number-of-Errors Left 1 EEh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bits 0 – 7: Number-of-Errors Left Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 12 FUNCTIONAL TIMING 12.1 Functional Serial I/O Timing The Serial Interface provides flexible timing to interconnect with a wide variety of serial interfaces. TDEN is an input signal that can be used to enable or block the TSERO data. The “shaded bits” are not clocked by the DS33R11. The TDEN must occur one bit before the effected bit in the TSERO stream. Note that polarity of the TDEN is selectable through LI.TSLCR.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver The DS33R11 provides the TBSYNC signal as a byte boundary indication to an external interface when X.86 (LAPS) functionality is selected. The functional timing of TBSYNC is shown in the following figure.TBSYNC is active high on the last bit of the byte being shifted out, and occurs every 8 bits. For the serial receiver interface, RBSYNC is used to provide byte boundary indication to the DS33R11 when X.86 (LAPS) mode is used.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver In Half-Duplex (DTE) Mode, the DS33R11 supports CRS and COL signals. CRS is active when the PHY detects transmit or receive activity. If there is a collision as indicated by the COL input, the DS33R11 will replace the data nibbles with jam nibbles. After a “random“ time interval, the packet is retransmitted. The MAC will try to send the packet a maximum of 16 times. The jam sequence consists of 55555555h.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver RMII Receive data on RXD[1:0] is expected to be synchronous with the rising edge of the 50 MHz REF_CLK. The data is only valid if CRS_DV is high. The external PHY asynchronously drives CRS_DV low during carrier loss. Figure 12-9. RMII Receive Interface Functional Timing REFCLK RXD[1:0] P R E A M B L E F C S CRS_DV 12.3 Transceiver T1 Mode Functional Timing Figure 12-10.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 12-12. Receive-Side Boundary Timing (Elastic Store Disabled) RCLKO CHANNEL 23 RSERO CHANNEL 24 CHANNEL 1 LSB LSB MSB F MSB RSYNC RFSYNC RSIG CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B CHANNEL 1 A RCHCLK RCHBLK1 NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 12-13. Receive-Side 1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 12-14. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSYSCLK CHANNEL 31 1 CHANNEL 32 RSER O CHANNEL 1 LSB LSB MSB F 5 2 RSYNC RMSYNC 3 RSYNC A RSIG CHANNEL 31 B C/A D/B A CHANNEL 1 CHANNEL 32 B C/A D/B RCHCLK 4 RCHBLK NOTE 1: RSERO DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO 1. NOTE 2: RSYNC IS IN THE OUTPUT MODE (TR.IOCR1.4 = 0). NOTE 3: RSYNC IS IN THE INPUT MODE (TR.IOCR1.4 = 1).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 12-16. Transmit-Side ESF Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 TSYNC1 TSSYNC TSYNC 2 3 TSYNC NOTE 1: TSYNC IN FRAME MODE (TR.IOCR1.2 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TR.IOCR1.3 = 0). NOTE 2: TSYNC IN FRAME MODE (TR.IOCR1.2 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TR.IOCR1.3 = 1). NOTE 3: TSYNC IN MULTIFRAME MODE (TR.IOCR1.2 = 1). Figure 12-17.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 12-18. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) TSYSCLK CHANNEL 23 CHANNEL 24 LSB MSB TSERI CHANNEL 1 LSB F MSB TSSYNC CHANNEL 23 A TSIG B CHANNEL 24 C/A D/B A B CHANNEL 1 C/A D/B A TCHCLK TCHBLK 1 NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24 (IF THE TPCSI BIT IS SET, THEN THE SIGNALING DATA AT TSIG IS IGNORED DURING CHANNEL 24). Figure 12-19. Transmit-Side 2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 12.4 E1 Mode Figure 12-20. Receive-Side Timing 1 FRAME# 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RFSYNC RSYNC 1 RSYNC 2 NOTE 1: RSYNC IN FRAME MODE (TR.IOCR1.5 = 0). NOTE 2: RSYNC IN MULTIFRAME MODE (TR.IOCR1.5 = 1). NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME. Figure 12-21.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 12-22. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (E-Store Enabled) RSYSCLK CHANNEL 23/31 1 RSERO CHANNEL 24/32 CHANNEL 1/2 LSB LSB MSB F MSB RSYNC2 RMSYNC 3 RSYNC RCHCLK RCHBLK 4 NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ON 1). NOTE 2: RSYNC IN THE OUTPUT MODE (TR.IOCR1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 12-24. G.802 Timing, E1 Mode Only TS # 31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK RCLKO / RSYSCLK TCLKT / TSYSCLK CHANNEL 25 NOTE: RCHBLK OR TCHBLK PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 THROUGH 15, 17 THROUGH 25, AND BIT 1 OF TIME SLOT 26. CHANNEL 26 LSB MSB RSERO / TSERI RCHCLK / TCHCLK RCHBLK / TCHBLK Figure 12-25.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 12-26. Transmit-Side Boundary Timing (Elastic Store Disabled) TCLKT CHANNEL 1 TSERI LSB Si 1 A CHANNEL 2 Sa4 Sa5 Sa6 Sa7 Sa8 MSB LSB MSB TSYNC1 TSYNC2 CHANNEL 1 TSIG CHANNEL 2 D A B C D TCHCLK TCHBLK 3 NOTE 1: TSYNC IS IN THE OUTPUT MODE (TR.IOCR1.1 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TR.IOCR1.1 = 0). NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 12-28. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled) TSYSCLK CHANNEL 31 TSERI CHANNEL 32 1 CHANNEL 1 LSB MSB LSB F 4 TSSYNC CHANNEL 31 TSIG A B CHANNEL 32 C D A TCHCLK TCHBLK NOTE 1: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 31.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (except VDD)….………………………………………..-0.5V to +5.5V Supply Voltage (VDD3.3) Range with Respect to VSS……………..……………………………………….-0.3V to +3.6V Supply Voltage (VDD1.8) with Respect to VSS………………………..…….……………………………….-0.3V to +2.0V Ambient Operating Temperature Range………………………………...………………………………......-40°C to +85°C Junction Operating Temperature Range…………………………………...
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.1 Thermal Characteristics Table 13-3. Thermal Characteristics PARAMETER MIN Ambient Temperature (Note 1) TYP -40°C MAX +85°C Junction Temperature (Note 2) +125°C Theta-JA (θJA) in Still Air for 256-Pin 27mm BGA (Notes 2, 3) +20.3°C/W Note 1: The package is mounted on a four-layer JEDEC standard test board. Note 2: Value guaranteed by design (GBD).
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.2 MII Interface Table 13-5. Transmit MII Interface (Note 1, Figure 13-1) PARAMETER SYMBOL MIN 10Mbps TYP MAX MIN 400 100Mbps TYP MAX 40 UNITS TX_CLK Period t1 TX_CLK Low Time t2 140 260 14 26 ns TX_CLK High Time t3 140 260 14 26 ns TX_CLK to TXD, TX_EN Delay t4 0 20 0 20 ns Note 1: Timing parameters in this table are guaranteed by design (GBD). Figure 13-1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Table 13-6. Receive MII Interface (Note 1, Figure 13-2) PARAMETER SYMBOL MIN 10Mbps TYP MAX MIN 40 UNITS RX_CLK Period t5 RX_CLK Low Time t6 140 260 14 26 ns RX_CLK High Time t7 140 260 14 26 ns t8 5 5 ns t9 5 5 ns RXD, RX_DV to RX_CLK Setup Time RX_CLK to RXD, RX_DV Hold Time 400 100Mbps TYP MAX ns Note 1: Timing parameters in this table are guaranteed by design (GBD). Figure 13-2.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.3 RMII Interface Table 13-7. Transmit RMII Interface (Note 1, Figure 13-3) PARAMETER SYMBOL MIN REF_CLK Frequency 10Mbps TYP 50MHz ±50ppm MAX MIN 20 100Mbps TYP 50MHz ±50ppm MAX 20 UNITS REF_CLK Period t1 REF_CLK Low Time t2 7 13 7 13 ns REF_CLK High Time t3 7 13 7 13 ns REF_CLK to TXD, TX_EN Delay t4 5 10 5 10 ns Note 1: Timing parameters in this table are guaranteed by design (GBD). Figure 13-3.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Table 13-8.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.4 MDIO Interface Table 13-9. MDIO Interface (Note 1, Figure 13-5) PARAMETER SYMBOL MIN TYP MDC Frequency MAX 1.67 UNITS MHz MDC Period t1 540 600 660 ns MDC Low Time t2 270 300 330 ns MDC High Time t3 270 300 330 ns MDC to MDIO Output Delay t4 20 10 ns MDIO Setup Time t5 10 ns MDIO Hold Time t6 20 ns Note 1: Timing parameters in this table are guaranteed by design (GBD). Figure 13-5.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.5 Transmit WAN Interface Table 13-10. Transmit WAN Interface (Note 1, Figure 13-6) PARAMETER SYMBOL MIN TYP TCLKE Frequency MAX UNITS 52 MHz TCLKE Period t1 19.2 ns TCLKE Low Time t2 8 ns TCLKE High Time t3 8 ns TCLKE to TSERO Output Delay t4 3 TCLKE to TBSYNC Setup Time t5 3.5 ns TBSYNC Hold Time t6 7 ns TCLKE to TDEN Output Delay t7 3.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.6 Receive WAN Interface Table 13-11. Receive WAN Interface (Note 1, Figure 13-7) PARAMETER RCLKI Frequency SYMBOL MIN TYP RCLKI Period t1 19.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.7 SDRAM Timing Table 13-12. SDRAM Interface Timing (Note 1, Figure 13-8) PARAMETER SYMBOL MIN 100 MHz TYP MAX 10 10.3 ns 6 ns 7 ns SDCLKO Period t1 9.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 13-8.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.8 Microprocessor Bus AC Characteristics Table 13-13. AC Characteristics—Microprocessor Bus Timing (VDD3.3 = 3.3V ±5%, VDD1.8 = 1.8V ±5%, Tj = -40°C to +85°C.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 13-9. Intel Bus Read Timing (MODEC = 00) t9 ADDR[12:0] Address Valid Data Valid DATA[7:0] t5 WR t1 CS t2 t3 t4 RD t10 Figure 13-10.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 13-11. Motorola Bus Read Timing (MODEC = 01) t9 ADDR[12:0] Address Valid Data Valid DATA[7:0] t5 RW t1 CS/CST t2 t3 t4 DS t10 Figure 13-12.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.9 AC Characteristics: Receive-Side Table 13-14. AC Characteristics: Receive Side (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Note 1, Figure 13-3, Figure 13-14, and Figure 13-15) PARAMETER RDCLKO Period RDCLKO Pulse Width RDCLKO Pulse Width SYMBOL CONDITIONS MIN TYP MAX 488 (E1) tLP ns 648 (T1) tLH (Note 2) 200 0.5 tLP tLL (Note 2) 200 0.5 tLP tLH (Note 3) 150 0.5 tLP tLL (Note 3) 150 0.5 tLP 488 (E1) 648 (T1) 0.5 tCP 0.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 13-13. Receive-Side Timing RCLKO t D1 RSERO / RDATA / RSIG 1ST FRAME BIT t D2 RSYNC 1 t D2 RFSYNC / RMSYNC t D2 RCHCLK t D2 RCHBLK NOTE 1: RSYNC IS IN THE OUTPUT MODE. NOTE 2: NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND OTHER SIGNALS IS IMPLIED.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 13-14. Receive-Side Timing, Elastic Store Enabled t SL tF tR RSYSCLK t SP t D3 SEE NOTE 3 RSERO / RSIG t D4 RCHCLK t D4 RCHBLK t D4 RMSYNC RSYNC RSYNC t SH 1 t D4 t HD 2 t SU NOTE 1: RSYNC IS IN THE OUTPUT MODE. NOTE 2: RSYNC IS IN THE INPUT MODE. NOTE 3: F-BIT WHEN MSTRREG.1 = 0, MSB OF TS0 WHEN MSTREG.1 = 1.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 13-15.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.10 AC Characteristics: Backplane Clock Timing Table 13-15. AC Characteristics: Backplane Clock Synthesis (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Note 1, (Figure 13-16) PARAMETER SYMBOL Delay RCLKO to BPCLK CONDITIONS MIN tD1 Note: Timing parameters in this table are guaranteed by design (GBD). Figure 13-16. Receive Timing Delay RCLKO to BPCLK RCLKO t D1 BPCLK NOTE: IF RCLKO IS 1.544 MHZ, BPCLK WILL BE ASYNCHRONOUS.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.11 AC Characteristics: Transmit Side Table 13-16. AC Characteristics: Transmit Side (VDD = 3.3V ±5%, TA = 0°C to +85°C.) (Note 1, Figure 13-17, Figure 13-18, and Figure 13-19) PARAMETER SYMBOL CONDITIONS MIN TYP (E1) MAX 488 (E1) 648 (T1) 0.5 tCP 0.5 tCP 488 (E1) 648 (T1) 0.5 tLP 0.5 tLP 648 448 0.5 tSP 0.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 13-17. Transmit-Side Timing t CP t CL tF tR t CH TCLKT t D1 TESO t SU TSERI / TSIG / TDATA t HD t D2 TCHCLK t D2 TCHBLK t D2 TSYNC1 t HD t SU TSYNC2 5 TLCLK t D2 t HD TLINK t SU NOTE 1: TSYNC IS IN THE OUTPUT MODE (IOCR1.1 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (IOCR1.1 = 0). NOTE 3: TSERI IS SAMPLED ON THE FALLING EDGE OF TCLKT WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 13-18. Transmit-Side Timing, Elastic Store Enabled t SP t SL tF tR t SH TSYSCLK t SU TSERI t D3 t HD TCHCLK t D3 TCHBLK t HD t SU TSSYNC NOTE 1: TSERI IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. NOTE 2: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. Figure 13-19.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 13.12 JTAG Interface Timing Table 13-17. JTAG Interface Timing (VDD3.3 = 3.3V ±5%,VDD1.8 = 1.8V ±5%, Tj = -40°C to +85°C.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 14 JTAG INFORMATION The DS33R11 contains two JTAG ports. Port 1 is for the Ethernet Mapper, and Port 2 is for the T1/E1/J1 Transceiver. Because of this, this device requires special consideration during JTAG test design. For more information on performing JTAG testing using this device, go to www.maxim-ic.com/support. The device supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 14.1 JTAG TAP Controller State Machine Description This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Update-DR A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Figure 14-2. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test/ Idle 1 Select DR-Scan 1 Select IR-Scan 0 1 0 1 Capture DR Capture IR 0 Shift DR 0 Shift IR 0 1 Exit DR Exit IR 1 0 Pause IR 0 1 0 0 1 1 0 Pause DR 1 Exit2 DR 1 0 Exit2 IR 1 1 Update DR Update IR 1 1 0 0 0 14.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver Table 14-1. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SAMPLE:PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification INSTRUCTION CODES 010 111 000 011 100 001 SAMPLE:PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 14.3 JTAG ID Codes Table 14-2. ID Code Structure DEVICE REVISION ID[31:28] DEVICE CODE ID[27:12] MANUFACTURER’S CODE ID[11:1] REQUIRED ID[0] Ethernet Mapper 0000 0000 0000 0110 0001 000 1010 0001 1 T1/E1/J1 Transceiver 0000 0000 0000 0001 0000 000 1010 0001 1 14.4 Test Registers IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 14.5 JTAG Functional Timing This functional timing for the JTAG circuits shows: • The JTAG controller starting from reset state. • Shifting out the first 4 LSB bits of the IDCODE. • Shifting in the BYPASS instruction (111) while shifting out the mandatory X01 pattern. • Shifting the TDI pin to the TDO pin through the bypass shift register. • An asynchronous reset occurs while shifting. Figure 14-3.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 15 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 15.
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver 16 DOCUMENT REVISION HISTORY REVISION 072105 030807 DESCRIPTION New product release. (Page 28) Corrected pin description of REF_CLK. (Page 28) Clarified text regarding use of REF_CLKO in DCE and RMII modes. (Page 29) Corrected pin description of MDC. (Page 43) In Section 9.1, removed from third bullet the sentence “The user can utilize the builtin REF_CLKO output clock to drive this input.