Product Preview DS21Q55 PRODUCT PREVIEW X DS21Q55 Quad T1/E1/J1 Transceiver FEATURES: Complete T1 (DS1)/ISDN–PRI/J1 transceiver functionality § Complete E1 (CEPT) PCM-30/ISDN-PRI transceiver functionality § Short- and long-haul line interface for clock/data recovery and wave shaping § CMI coder/decoder § Crystal- less jitter attenuator § Dual HDLC controllers § On-chip programmable BERT generator and detector § Internal software-selectable receive and transmit side termination resistors § Dual two- frame
Product Preview DS21Q55 1. DESCRIPTION The DS21Q55 is a quad MCM devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21Q55 is software compatible with the DS2155 single transceiver. It is pin compatible with the DS21Qx5y family of products.
Product Preview DS21Q55 The device fully meets all of the latest E1 and T1 specifications, including the following: § § § § § ANSI: AT&T: ITU: ETSI: Japanese: T1.403-1995, T1.231-1993, T1.408 TR54016, TR62411 G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, O.161 ETS 300 011, ETS 300 166, ETS 300 233, CTR4, CTR12 JTG.703, JTI.431, JJ-20.11 (CMI coding only) 3 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 1.1 FEATURE HIGHLIGHTS The DS21Q55 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 transceivers plus many new features. 1.1.1 General § § § § § § § 27mm, 1.27 pitch BGA 3.3V supply with 5V tolerant inputs and output s Pin compatible with DS21x5y family Software compatible with the DS2155 Evaluation kits IEEE 1149.1 JTAG-boundary scan Driver source code available from the factory 1.1.
Product Preview § § § DS21Q55 Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation Can be placed in either the receive or transmit path or disabled Limit trip indication 1.1.
Product Preview § § § § DS21Q55 Hardware-signaling capability − Receive-signaling reinsertion to a backplane, multiframe sync − Availability of signaling in a separate PCM data stream − Signaling freezing Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode Access to the data streams in between the framer/formatter and the elastic stores User-selectable synthesized clock output 1.1.
Product Preview DS21Q55 Note: This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125µs T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. Each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last.
Product Preview DS21Q55 TABLE OF CONTENTS 1.1 FEATURE HIGHLIGHTS ............................................................................................................................4 1.1.1 General .................................................................................................................................................. 4 1.1.2 Line Interface.......................................................................................................................................
Product Preview 12. LOOPBACK CONFIGURATION .............................................................................................................68 12.1 13. DS21Q55 PER-CHANNEL LOOPBACK ...........................................................................................................................70 ERROR COUNT REGISTERS .................................................................................................................72 13.1 13.2 13.3 13.4 14.
Product Preview 22.3.4 Receive Packet Bytes Available ...............................................................................................144 22.3.5 HDLC FIFOS....................................................................................................................................145 22.4 RECEIVE HDLC CODE EXAMPLE............................................................................................................. 146 22.5 LEGACY FDL SUPPORT (T1 M ODE)............................
Product Preview 32.2 E1 M ODE...................................................................................................................................................... 218 33. OPERATING PARAMETERS .................................................................................................................231 34. AC TIMING PARAMETERS AND DIAGRAMS ...............................................................................233 34.1 34.2 34.3 34.4 35.
Product Preview DS21Q55 1.2 DOCUMENT REVISION HISTORY 1) Initial Preliminary Release 12 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 2. BLOCK DIAGRAM A simplified block diagram showing the major components of the DS21Q55 is shown in Figure 4-1. Details are shown in subsequent figures. The block diagram is then divided into three functional blocks: LIU, framer, and backplane interface. BLOCK DIAGRAM Figure 4-1 TRANSCEIVER #4 TRANSCEIVER #3 RPOSI RNEGI RCLKI RPOSO RNEGO RCLKO TRANSCEIVER #2 RCLK RLOS/LOTC 8.
Product Preview DS21Q55 3. PIN FUNCTION DESCRIPTION 3.1 Transmit Side Pins Signal Name: TCLKx Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz or a 2.048MHz primary clock. Used to clock data through the transmit -side formatter. Signal Name: TSERx Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.
Product Preview DS21Q55 Signal Name: TSYNCx Signal Description: Transmit Sync Signal Type: Input/Output A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Can be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set via IOCR1.3 to output double-wide pulses at signaling frames in T1 mode.
Product Preview DS21Q55 Signal Name: TNEGIx Signal Description: Transmit Negative Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the LIUC pin high. TPOSI and TNEGI can be tied together in NRZ applications. Signal Name: TCLKIx Signal Description: Transmit Clock Input Signal Type: Input Line interface transmit clock. Can be internally connected to TCLKO by tying the LIUC pin high. 3.
Product Preview DS21Q55 Signal Name: RSYNCx Signal Description: Receive Sync Signal Type: Input/Output An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (IOCR1.5 = 0) or multiframe (IOCR1.5 = 1) boundaries. If set to output-frame boundaries then via IOCR1.6, RSYNC can also be set to output double-wide pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin can be enabled to be an input via IOCR1.
Product Preview DS21Q55 Signal Name: BPCLKx Signal Description: Back Plane Clock Signal Type: Output A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin. Signal Name: RPOSOx Signal Description: Receive Positive Data Output Signal Type: Output Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI.
Product Preview DS21Q55 Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation. Signal Name: D0/AD0 to D7/AD7 Signal Description: Data Bus [D0 to D7] or Address/Data Bus Signal Type: Input/Output In nonmultiplexed bus operation (MUX = 0), it serves as the data bus. In multiplexed bus operation (MUX = 1), it serves as an 8-bit, multiplexed address/data bus.
Product Preview DS21Q55 Signal Name: A7/ALE(AS) Signal Description: A7 or Address Latch Enable(Address Strobe) Signal Type: Input In nonmultiplexed bus operation (MUX = 0), it serves as the upper address bit. In multiplexed bus operation (MUX = 1), it serves to demultiplex the bus on a positive-going edge. Signal Name: WR*(R/W*) Signal Description: Write Input(Read/Write) Signal Type: Input WR* is an active-low signal. 3.
Product Preview DS21Q55 Signal Name: JTCLK Signal Description: IEEE 1149.1 Test Clock Signal Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. Signal Name: JTDI Signal Description: IEEE 1149.1 Test Data Input Signal Type: Input Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pullup resistor. Signal Name: JTDO Signal Description: IEEE 1149.
Product Preview DS21Q55 Signal Name: TTIP x and TRINGx Signal Description: Transmit Tip and Ring Signal Type: Output Analog line driver outputs. These pins connect via a 1:2 step-up transformer to the network. See Line Interface Unit for details. 3.7 Supply Pins Signal Name: DV DD Signal Description: Digital Positive Supply Signal Type: Supply 3.3V ±5%. Should be tied to the RVDD and TVDD pins. Signal Name: RV DD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3V ±5%.
Product Preview DS21Q55 3.
Product Preview PIN A20 B11 A5 B7 B9 H20 L20 N17 J4 C13 C3 U13 W6 F18 D7 T20 V9 B17 A6 J20 U1 Y15 N1 V19 W13 V18 K2 T1 W20 U10 M2 G17 G4 Y12 J1 D14 F3 U14 N3 B13 E3 M18 M4 A15 A4 R17 M3 C14 B4 T17 N2 K4 DS21Q55 SYMBOL DVSS2 DVSS2 DVSS3 DVSS3 DVSS3 DVSS4 DVSS4 DVSS4 ESIBRD1 ESIBRD2 ESIBRD3 ESIBRD4 ESIBS0_1 ESIBS0_2 ESIBS0_3 ESIBS0_4 ESIBS1_1 ESIBS1_2 ESIBS1_3 ESIBS1_4 INT* JTCLK JTDI JTDO JTMS JTRST* LIUC MCLK1 MCLK2 MUX RCHBLK1 RCHBLK2 RCHBLK3 RCHBLK4 RCHCLK1 RCHCLK2 RCHCLK3 RCHCLK4 RCLK1 RCLK2 RCLK3 RCLK4
Product Preview PIN DS21Q55 SYMBOL TYPE D17 RFSYNC2 O A2 RFSYNC3 O V14 RFSYNC4 O F1 A12 D3 K18 G2 A13 A3 U12 H2 E17 E1 V11 L1 D16 F2 W16 R3 D13 A1 P17 L3 B15 C2 U17 R4 B14 B2 V15 L4 A16 B1 U15 Y11 Y14 Y17 Y20 J2 D15 E2 W17 L2 B16 C1 Y18 K1 C15 RLCLK1 RLCLK2 RLCLK3 RLCLK4 RLINK1 RLINK2 RLINK3 RLINK4 RLOS/LOTC1 RLOS/LOTC2 RLOS/LOTC3 RLOS/LOTC4 RMSYNC1 RMSYNC2 RMSYNC3 RMSYNC4 RNEGI1 RNEGI2 RNEGI3 RNEGI4 RNEGO1 RNEGO2 RNEGO3 RNEGO4 RPOSI1 RPOSI2 RPOSI3 RPOSI4 RPOSO1 RPOSO2 RPOSO3 RPOSO4 RRING1 RRIN
Product Preview PIN D2 V16 G1 D12 D1 V12 H1 F17 G3 W14 Y10 Y13 Y16 Y19 P1 J17 E4 W18 R2 T2 H19 J18 D4 D5 V20 W19 W1 F20 C11 U20 V10 A18 B8 L18 Y9 B19 B10 M19 V6 D19 C8 P20 W7 E18 A7 P19 V3 E20 D6 T18 W5 E19 DS21Q55 SYMBOL RSIGF3 RSIGF4 RSYNC1 RSYNC2 RSYNC3 RSYNC4 RSYSCLK1 RSYSCLK2 RSYSCLK3 RSYSCLK4 RTIP1 RTIP2 RTIP3 RTIP4 RVDD1 RVDD2 RVDD3 RVDD4 RVSS1 RVSS1 RVSS2 RVSS2 RVSS3 RVSS3 RVSS4 RVSS4 TCHBLK1 TCHBLK2 TCHBLK3 TCHBLK4 TCHCLK1 TCHCLK2 TCHCLK3 TCHCLK4 TCLK1 TCLK2 TCLK3 TCLK4 TCLKI1 TCLKI2 TCLKI3 TCLKI4
Product Preview PIN C6 T19 R1 F19 D8 R20 T3 B20 D9 N20 W3 C20 A8 R19 V7 C19 C9 N19 Y2 Y4 Y6 Y8 W9 C17 C10 K20 W10 C18 A10 L19 W12 B18 D10 K19 U16 V1 D20 C7 R18 W11 A19 A11 N18 Y1 Y3 Y5 Y7 W2 G19 D11 U19 W4 DS21Q55 SYMBOL TLINK3 TLINK4 TNEGI1 TNEGI2 TNEGI3 TNEGI4 TNEGO1 TNEGO2 TNEGO3 TNEGO4 TPOSI1 TPOSI2 TPOSI3 TPOSI4 TPOSO1 TPOSO2 TPOSO3 TPOSO4 TRING1 TRING2 TRING3 TRING4 TSER1 TSER2 TSER3 TSER4 TSIG1 TSIG2 TSIG3 TSIG4 TSSYNC1 TSSYNC2 TSSYNC3 TSSYNC4 TSTRST TSYNC1 TSYNC2 TSYNC3 TSYNC4 TSYSCLK1 TSYSCLK2 TSY
Product Preview PIN G18 C5 U18 K3 DS21Q55 SYMBOL TVSS2 TVSS3 TVSS4 WR* (R/W*) TYPE – – – I DESCRIPTION Transmit Analog Signal Ground. Transmit Analog Signal Ground. Transmit Analog Signal Ground. Write Input (Read/Write). 28 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 3.9 Package DS21Q55 Pin DIAGRAM, 27mm BGA Figure 5-1 The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same pattern that would be seen as viewed from the top.
Product Preview DS21Q55 4. PARALLEL PORT The DS21Q55 is controlled via a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The DS21Q55 can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the AC Electrical Characteristics for more details.
Product Preview ADDRESS 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 R/W DS21Q55 REGISTER NAME Status Register 9 Interrupt Mask Register 9 Per-Channel Pointer Register Per-Channel Data Register 1 Per-Channel Data Register 2 Per-Channel Data Register 3 Per-Channel Data Register 4 Information Register 4 Information Register 5 Information Register 6 Information Register 7 HDLC #1 Receive Control HDL
Product Preview ADDRESS 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D R/W DS21Q55 REGISTER NAME Transmit Signaling Register 11 Transmit Signaling Register 12 Transmit Signaling Register 13 Transmit Signaling Register 14 Transmit Signaling Register 15 Transmit Signaling Register 16 Receive Signaling Register 1 Receive Signaling Register 2 Receive Signaling Register 3 Receive Signaling Register 4 Re
Product Preview ADDRESS 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 R/W DS21Q55 REGISTER NAME Transmit Channel Blocking Register 3 Transmit Channel Blocking Register 4 HDLC #1 Transmit Control HDLC #1 FIFO Control HDLC #1 Receive Channel Select 1 HDLC #1 Receive Channel Select 2 HDLC #1 Receive Channel Select 3 HDLC #1 Receive Channel Select 4 HDLC #1 Receive Time Slot Bits/Sa Bits Select HDLC #
Product Preview ADDRESS C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 R/W DS21Q55 REGISTER NAME Receive FDL Match Register 1 Receive FDL Match Register 2 Test Register Interleave Bus Operation Control Register Receive Align Frame Register Receive Nonalign Frame Register Receive Si Align Frame Receive Si Nonalign Frame Receive Remote Alarm Bits Receive Sa4 Bits Receive Sa5 Bits Receive Sa6 Bits Rec
Product Preview ADDRESS R/W DS21Q55 REGISTER NAME F6 Test Register F7 Test Register F8 Test Register F9 Test Register FA Test Register FB Test Register FC Test Register FD Test Register FE Test Register FF Test Register *TEST1 to TEST16 registers are used only by the factory. 35 of 248 REGISTER ABBREVIATION TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST PAGE * * * * * * * * * * 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 5. SPECIAL PER-CHANNEL REGISTER OPERATION Some of the features described in the data sheet that operate on a per-channel basis use a special method for channel selection. The registers involved are the per-channel pointer registers (PCPR) and per-channel data registers 1 to 4 (PCDR1–4). The user selects the function(s) that are to be applied on a per-channel basis by setting the appropriate bit(s) in the PCPR register.
Product Preview DS21Q55 Register Name: Register Description: Register Address: PCDR1 Per-Channel Data Register 1 29h Bit # Name Default 7 6 5 4 3 2 1 0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Register Name: Register Description: Register Address: PCDR2 Per-Channel Data Register 2 2Ah Bit # Name Default 7 6 5 4 3 2 1 0 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Register Name: Register Description: Register Address: PCDR3 Per-Channel Data Register 3 2Bh Bit # Name Default 7 6
Product Preview DS21Q55 6. PROGRAMMING MODEL The DS21Q55 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the device, selecting T1 or E1 operation in the master mode register, enabling T1 or E1 functions, and enabling the common functions. The act of resetting the device automatically clears all configuration and status registers.
Product Preview DS21Q55 6.1 Power-Up Sequence The DS21Q55 contains an on-chip power-up reset function, which automatically clears the writeable register space immediately after power is supplied to the device. The user can issue a chip reset at any time. Issuing a reset will disrupt traffic until the device is reprogrammed. The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST function in the master mode register. The LIRST (LIC2.
Product Preview DS21Q55 6.2 Interrupt Handling Various alarms, conditions, and events in the DS21Q55 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All STATUS registers can be programmed to produce interrupts. Each status register has an associated interrupt mask register. For example, SR1 (Status Register 1) has an interrupt control register called IMR1 (Interrupt Mask Register 1). Status registers are the only sources of interrupts.
Product Preview DS21Q55 marked as “double interrupt bits.” An interrupt will be produced when the condition occurs and when it clears. 6.4 Information Registers Information registers operate the same as status registers except they cannot cause interrupts. They are all latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read only register and it reports the status of the E1 synchronizer in real time.
Product Preview DS21Q55 7. CLOCK MAP Figure 9-1 shows the clock map of the DS21Q55. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity. CLOCK MAP Figure 9-1 MCLK PRE-SCALER LIC4.MPS0 LIC4.MPS1 2.048 TO 1.544 SYNTHESIZER LIC2.
Product Preview DS21Q55 8. T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS21Q55 is configured via a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 T1RCR2 T1 Receive Control Register 2 04h 6 RFM 0 5 RB8ZS 0 4 RSLC96 0 3 RZSE 0 2 RZBTSI 0 1 RJC 0 0 RD4YM 0 Bit 0/Receive Side D4 Yellow Alarm Select (RD4YM). 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode) Bit 1/Receive Japanese CRC6 Enable (RJC).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 TJC 0 DS21Q55 T1TCR1 T1 Transmit Control Register 1 05h 6 TFPT 0 5 TCPT 0 4 TSSE 0 3 GB7S 0 2 TFDLS 0 1 TBL 0 0 TYEL 0 Bit 0/Transmit Yellow Alarm (TYEL). 0 = do not transmit yellow alarm 1 = transmit yellow alarm Bit 1/Transmit Blue Alarm (TBL). 0 = transmit data normally 1 = transmit an unframed all one’s code at TPOS and TNEG Bit 2/TFDL Register Select (TFDLS).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 TB8ZS 0 DS21Q55 T1TCR2 T1 Transmit Control Register 2 06h 6 TSLC96 0 5 TZSE 0 4 FBCT2 0 3 FBCT1 0 2 TD4YM 0 1 TZBTSI 0 0 TB7ZS 0 Bit 0/Transmit Side Bit 7 Zero Suppression Enable (TB7ZS). 0 = no stuffing occurs 1 = Bit 7 force to a one in channels with all zeros Bit 1/Transmit Side ZBTSI Support Enable (TZBTSI). Allows ZBTSI information to be input on TLINK pin.
Product Preview DS21Q55 Register Name: Register Description: Register Address: T1CCR1 T1 Common Control Register 1 07h Bit # Name Default 6 0 7 0 5 0 4 0 3 0 2 TFM 0 1 PDE 0 0 TLOOP 0 Bit 0/Transmit Loop Code Enable (TLOOP). See Programmable In-Band Loop Codes Generation and Detection for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in registers TCD1 and TCD2 Bit 1/Pulse Density Enforcer Enable (PDE).
Product Preview DS21Q55 8.2 T1 Transmit Transparency The software-signaling insertion-enable registers, SSIE1–SSIE4, can be used to select signaling insertion from the transmit-signaling registers, TS1–TS12, on a per-channel basis. Setting a bit in the SSIEx register allows signaling data to be sourced from the signaling registers for that channel. In transparent mode, bit 7 stuffing and/or robbed-bit signaling is prevented from overwriting the data in the channels.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 DS21Q55 T1RDMR1 T1 Receive Digital Milliwatt Enable Register 1 0Ch 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0 Bits 0 to 7/Receive Digital Milliwatt Enable for Channels 1 to 8 (CH1 to CH8).
Product Preview DS21Q55 8.4 T1 Information Register Register Name: Register Description: Register Address: Bit # Name Default 7 RPDV 0 INFO1 Information Register 1 10h 6 TPDV 0 5 COFA 0 4 8ZD 0 3 16ZD 0 2 SEFE 0 1 B8ZS 0 0 FBE 0 Bit 0/Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error. Bit 1/B8ZS Code Word Detect Event (B8ZS). Set when a B8ZS code word is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not via T1TCR2.7.
Product Preview DS21Q55 T1 ALARM CRITERIA Table 10-1 ALARM SET CRITERIA CLEAR CRITERIA Over a 3ms window, five or fewer zeros are received Over a 3ms window, six or more zeros are received D4 Bit-2 Mode (T1RCR2.0 = 0) Bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences Bit 2 of 256 consecutive channels is set to zero for less than 254 occurrences D4 12th F-bit Mode (T1RCR2.
Product Preview DS21Q55 9. E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS21Q55 is configured via a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There are two receive control registers (E1RCR1 and E1RCR2) and two transmit control registers (E1TCR1 and E1TCR2).
Product Preview DS21Q55 E1 SYNC/RESYNC CRITERIA Table 11-1 FRAME OR MULTIFRAME LEVEL FAS CRC4 CAS Register Name: Register Description: Register Address: Bit # Name Default 7 Sa8S 0 SYNC CRITERIA RESYNC CRITERIA FAS present in frame N and N + 2, and FAS not present in frame N + 1 ITU SPEC. Three consecutive incorrect FAS received Alternate: (E1RCR1.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 TFPT 0 DS21Q55 E1TCR1 E1 Transmit Control Register 1 35h 6 T16S 0 5 TUA1 0 4 TSiS 0 3 TSA1 0 2 THDB3 0 1 TG802 0 0 TCRC4 0 Bit 0/Transmit CRC4 Enable (TCRC4). 0 = CRC4 disabled 1 = CRC4 enabled Bit 1/Transmit G.802 Enable (TG802). See Functional Timing Diagrams for details.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 Sa8S 0 DS21Q55 E1TCR2 E1 Transmit Control Register 2 36h 6 Sa7S 0 5 Sa6S 0 4 Sa5S 0 3 Sa4S 0 2 AEBE 0 1 AAIS 0 0 ARA 0 Bit 0/Automatic Remote Alarm Generation (ARA). 0 = disabled 1 = enabled Bit 1/Automatic AIS Generation (AAIS). 0 = disabled 1 = enabled Bit 2/Automatic E-Bit Enable (AEBE).
Product Preview DS21Q55 9.2 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (E1TCR2.1 = 1), the device monitors the receive side framer to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal).
Product Preview DS21Q55 9.3 E1 Information Registers Register Name: Register Description: Register Address: INFO3 Information Register 3 12h Bit # Name Default 6 0 7 0 5 0 4 0 3 0 2 CRCRC 0 1 FASRC 0 0 CASRC 0 Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are received in error. Bit 1/FAS Resync Criteria Me t Event (FASRC. Set when three consecutive FAS words are received in error. Bit 2/CRC Resync Criteria Met Event (CRCRC).
Product Preview DS21Q55 E1 ALARM CRITERIA Table 11-2 ALARM SET CRITERIA RLOS An RLOS condition exists on powerup prior to initial synchronization, when a re-sync criteria has been met, or when a manual re-sync has been initiated via E1RCR1.0 255 or 2048 consecutive zeros received as determined by E1RCR2.
Product Preview DS21Q55 10. COMMON CONTROL AND STATUS REGISTERS Register Name: Register Description: Register Address: Bit # Name Default 7 0 CCR1 Common Control Register 1 70h 6 CRC4R 0 5 SIE 0 4 ODM 0 3 DICAI 0 2 TCSS1 0 1 TCSS0 0 0 RLOSF 0 Bit 0/Function of the RLOS/LOTC Output (RLOSF). 0 = Receive Loss of Sync (RLOS) 1 = Loss of Transmit Clock (LOTC) Bit 1/Transmit Clock Source Select bit 0 (TCSS0). Bit 2/Transmit Clock Source Select bit 1 (TCSS1).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 ID7 1 DS21Q55 IDR Device Identification Register 0Fh 6 ID6 0 5 ID5 1 4 ID4 1 3 ID3 X 2 ID2 X 1 ID1 X 0 ID0 X Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip. IDO is the LSB of a decimal code that represents the chip revision. Bits 4 to 7/Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the device ID.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 RYELC 0 DS21Q55 IMR2 Interrupt Mask Register 2 19h 6 RUA1C 0 5 FRCLC 0 4 RLOSC 0 3 RYEL 0 2 RUA1 0 1 FRCL 0 0 RLOS 0 Bit 0/Receive Loss of Sync Condition (RLOS). 0 = interrupt masked 1 = interrupt enabled–interrupts on rising edge only Bit 1/Framer Receive Carrier Loss Condition (FRCL).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 LSPARE 0 DS21Q55 SR3 Status Register 3 1Ah 6 LDN 0 5 LUP 0 4 LOTC 0 3 LORC 0 2 V52LNK 0 1 RDMA 0 0 RRA 0 Bit 0/Receive Remote Al arm Condition (RRA). (E1 only) Set when a remote alarm is received at RPOSI and RNEGI Bit 1/Receive Distant MF Alarm Condition (RDMA). (E1 only) Set when bit 6 of timeslot 16 in frame 0 has been set for two consecutive multiframes.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 LSPARE 0 DS21Q55 IMR3 Interrupt Mask Register 3 1Bh 6 LDN 0 5 LUP 0 4 LOTC 0 3 LORC 0 2 V52LNK 0 1 RDMA 0 0 RRA 0 Bit 0/Receive Remote Alarm Condition (RRA). 0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges Bit 1/Receive Distant MF Alarm Condition (RDMA). 0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges Bit 2/V5.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 SR4 Status Register 4 1Ch 6 RSA1 0 5 RSA0 0 4 TMF 0 3 TAF 0 2 RMF 0 1 RCMF 0 0 RAF 0 Bit 0/Receive Align Frame Event (RAF). (E1 only) Set every 250µs at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Bit 1/Receive CRC4 Multiframe Event (RCMF).
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 IMR4 Interrupt Mask Register 4 1Dh 6 RSA1 0 5 RSA0 0 4 TMF 0 3 TAF 0 2 RMF 0 1 RCMF 0 0 RAF 0 Bit 0/Receive Align Frame Event (RAF). 0 = interrupt masked 1 = interrupt enabled Bit 1/Receive CRC4 Multiframe Event (RCMF). 0 = interrupt masked 1 = interrupt enabled Bit 2/Receive Multiframe Event (RMF). 0 = interrupt masked 1 = interrupt enabled Bit 3/Transmit Align Frame Event (TAF).
Product Preview DS21Q55 11. I/O PIN CONFIGURATION OPTIONS Register Name: Register Description: Register Address: Bit # Name Default 7 RSMS 0 IOCR1 I/O Configuration Register 1 01h 6 RSMS2 0 5 RSMS1 0 4 RSIO 0 3 TSDW 0 2 TSM 0 1 TSIO 0 0 ODF 0 Bit 0/Output Data Format (ODF). 0 = bipolar data at TPOSO and TNEGO 1 = NRZ data at TPOSO; TNEGO = 0 Bit 1/TSYNC I/O Select (TSIO). 0 = TSYNC is an input 1 = TSYNC is an output Bit 2/TSYNC Mode Select (TSM).
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default IOCR2 I/O Configuration Register 2 02h 7 6 5 4 3 2 1 0 RCLKINV TCLKINV RSYNCINV TSYNCINV TSSYNCINV H100EN TSCLKM RSCLKM 0 0 0 0 0 0 0 0 Bit 0/RSYSCLK Mode Select (RSCLKM). 0 = if RSYSCLK is 1.544MHz 1 = if RSYSCLK is 2.048MHz or IBO enabled (See Interleaved PCM Bus Operation.) Bit 1/TSYSCLK Mode Select (TSCLKM). 0 = if TSYSCLK is 1.544MHz 1 = if TSYSCLK is 2.
Product Preview DS21Q55 12. LOOPBACK CONFIGURATION Register Name: Register Description: Register Address: LBCR Loopback Control Register 4Ah Bit # Name Default 6 0 7 0 5 0 4 LIUC 0 3 LLB 0 2 RLB 0 1 PLB 0 0 FLB 0 Bit 0/Framer Loopback (FLB). 0 = loopback disabled 1 = loopback enabled This loopback is useful in testing and debugging applications. In FLB, the device will loop data from the transmit side back to the receive side.
Product Preview DS21Q55 Bit 3/Local Loopback (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the device. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator. (See Figure 1-1 Line Interface Unit.) 0 = loopback disabled 1 = loopback enabled Bit 4/Line Interface Unit Mux Control (LIUC). This is a software version of the LIUC pin.
Product Preview DS21Q55 12.1 Per-Channel Loopback The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TC LK and RFSYNC to TSYNC.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 DS21Q55 PCLR3 Per-Channel Loopback Enable Register 3 4Dh 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 1 CH26 0 0 CH25 0 Bits 0 to 7/Per-Channel Loopback Enable for Channels 17 to 24 (CH17 to CH24). 0 = loopback disabled 1 = enable loopback.
Product Preview DS21Q55 13. ERROR COUNT REGISTERS The DS21Q55 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode only), 62ms (E1 mode only) or manually. See Error Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers.
Product Preview DS21Q55 13.1 Line Code Violation Count Register (LCVCR) T1 Operation T1 code violations are defined as bipolar violations (BPVs) or excessive zeros. If the B8ZS mode is set for the receive side, then B8ZS code words are not counted. This counter is always enabled; it is not disabled during receive loss of synchronization (RLOS = 1) conditions (Table 15-1). T1 LINE CODE VIOLATION COUNTING OPTIONS Table 15-1 COUNT EXCESSIVE ZEROS? (ERCNT.0) No Yes No Yes B8ZS ENABLED? (T1RCR2.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC15 0 DS21Q55 LCVCR1 Line Code Violation Count Register 1 42h 6 LCVC14 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCCV8 0 Bits 0 to 7/Line Code Violation Counter Bits 8 to 15 (LCVC8 to LCVC15). LCV15 is the MSB of the 16-bit code violation count.
Product Preview DS21Q55 13.2 Path Code Violation Count Register (PCVCR) T1 Operation The path-code violation-count register records either Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR will record errors in the CRC6 code words. When set to operate in the T1 D4 framing mode, PCVCR will count errors in the Ft framing bit position. Via the ERCNT.2 bit, a framer can be programmed to also report errors in the Fs framing bit position.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 PCVC15 0 PCVCR1 Path Code Violation Count Register 1 44h 6 PCVC14 0 5 PCVC13 0 4 PCVC12 0 3 PCVC11 0 2 PCVC10 0 1 PCVC9 0 0 PCVC8 0 Bits 0 to 7/Path Code Violation Counter Bits 8 to 15 (PCVC8 to PCVC15). PCVC15 is the MSB of the 16-bit path code violation count.
Product Preview DS21Q55 The FOSCR1 (FOSCR1) is the most significant word and FOSCR2 is the least significant word of a 16bit counter that records frames out of sync. 77 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 FOS15 0 DS21Q55 FOSCR1 Frames Out Of Sync Count Register 1 46h 6 FOS14 0 5 FOS13 0 4 FOS12 0 3 FOS11 0 2 FOS10 0 1 FOS9 0 0 FOS8 0 Bits 0 to 7/Frames Out of Sync Counter Bits 8 to 15 (FOS8 to FOS15). FOS15 is the MSB of the 16-bit frames out of sync count.
Product Preview DS21Q55 14. DS0 MONITORING FUNCTION The DS21Q55 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set.
Product Preview DS21Q55 14.2 Receive DS0 Monitor Registers Register Name: Register Description: Register Address: RDS0SEL Receive Channel Monitor Select 76h Bit # Name Default 6 0 7 0 5 0 4 RCM4 0 3 RCM3 0 2 RCM2 0 1 RCM1 0 0 RCM0 0 Bits 0 to 4/Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel-select that determines which receive DS0 channel data will appear in the RDS0M register. Bits 5 to 7/Unused, must be set to zero for proper operation.
Product Preview DS21Q55 15. SIGNALING OPERATION There are two methods to access receive signaling data and provide transmit signaling data: processorbased (i.e., software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers, RS1–RS16 and TS1–TS16. Hardware-based refers to the TSIG and RSIG pins. Both methods can be used simultaneously. 15.
Product Preview DS21Q55 15.1.1 Processor-Based Receive Signaling The robbed-bit signaling (T1) or TS16 CAS signaling (E1) is sampled in the receive data stream and copied into the receive signaling registers, RS1 through RS16. In T1 mode, only RS1 through RS12 are used. The signaling information in these registers is always updated on multiframe boundaries. This function is always enabled. 15.1.1.
Product Preview DS21Q55 registers for T1 mode and PCDR1-PCDR4 registers for E1 mode. In E1 mode, the user will generally select all channels when doing reinsertion. 15.1.2.2 Force Receive Signaling All Ones In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling-bit positions to a one. This is done by using the per-channel register, which is described in the Special Per-Channel Operation section. The user sets the BTCS bit in the PCPR register.
Product Preview Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B DS21Q55 RS1 to RS12 Receive Signaling Registers
Product Preview Register Name: Register Description: Register Address: (MSB) 0 CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH26-A CH28-A CH30-A 0 CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B CH26-B CH28-B CH30-B DS21Q55 RS1 to RS16 Receive Signaling Registers (E1 Mode, CAS Format) 60h to 6Fh 0 CH2-C CH4-C CH6-C CH8-C CH10-C CH12-C CH14-C CH16-C CH18-C CH20-C CH22-C CH24-C CH26-C CH28-C CH30-C 0 CH2-D CH4-D CH6-D CH8-D CH10-D CH12-
Product Preview Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH7 CH15 CH23 DS21Q55 RSCSE1 , RSCSE2 , RSCSE3 , RSCSE4 Receive Signaling Change Of State Interrupt Enable 3Ch, 3Dh, 3Eh, 3Fh CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 RSCSE1 RSCSE2 RSCSE3 RSCSE4 Setting any of the CH1 through CH30 bits in the RSCSE1 through RSCSE4 registers will cause an interrupt when that channel’s signaling data
Product Preview DS21Q55 15.2 Transmit Signaling SIMPLIFIED DIAGRAM OF TRANSMIT SIGNALING PATH Figure 17-2 TRANSMIT SIGNALING REGISTERS 1 0 0 T1/E1 DATA STREAM TSER 0 1 1 B7 SIGNALING BUFFERS TSIG T1TCR1.4 PER-CHANNEL CONTROL PER-CHANNEL CONTROL PCPR.3 SSIE1 - SSIE4 ONLY APPLIES TO T1 MODE 15.2.1 Processor-Based Transmit Signaling In processor-based mode, signaling data is loaded into the transmit-signaling registers (TS1–TS16) via the host interface.
Product Preview DS21Q55 15.2.1.1 T1 Mode In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1–TS12 contain a full multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B). In T1 D4 framing mode, the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. In D4 mode, two multiframes of signaling data can be loaded into TS1–TS12.
Product Preview Register Name: Register Description: Register Address: (MSB) 0 CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH26-A CH28-A CH30-A 0 CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B CH26-B CH28-B CH30-B DS21Q55 TS1 to TS16 Transmit Signaling Registers (E1 Mode, CAS Format) 50h to 5Fh 0 CH2-C CH4-C CH6-C CH8-C CH10-C CH12-C CH14-C CH16-C CH18-C CH20-C CH22-C CH24-C CH26-C CH28-C CH30-C 0 CH2-D CH4-D CH6-D CH8-D CH10-D CH12-D
Product Preview Register Name: Register Description: Register Address: (MSB) 1 17 33 49 65 81 97 113 13 29 45 61 77 93 109 125 2 18 34 50 66 82 98 114 14 30 46 62 78 94 110 126 DS21Q55 TS1 to TS16 Transmit Signaling Registers (E1 Mode, CCS Format) 50h to 5Fh 3 19 35 51 67 83 99 115 15 31 47 63 89 95 111 127 4 20 36 52 68 84 100 116 16 32 48 64 80 96 112 128 5 9 25 41 57 73 89 105 121 21 37 53 69 85 101 117 6 10 26 42 58 74 90 106 122 22 38 54 70 86 102 118 90 of 248 7 11 27 43 59 75 91 107 123 23 3
Product Preview Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B DS21Q55 TS1 to TS16 Transmit Signaling Registers (T1 Mode, ESF Format) 50h to 5Bh CH2-C CH4-C CH6-C CH8-C CH10-C CH12-C CH14-C CH16-C CH18-C CH20-C CH22-C CH24-C CH2-D CH4-D CH6-D CH8-D CH10-D CH12-D CH14-D CH16-D CH18-D CH20-D CH22-D CH24-D CH1-A CH3-A CH5-A CH7-A CH9
Product Preview Register Name: Register Description: Register Address: DS21Q55 TS1 to TS16 Transmit Signaling Registers (T1 Mode, D4 Format) 50h to 5Bh (MSB) (LSB) CH2-A CH2-B CH2 -A CH2 -B CH1-A CH1-B CH1 -A CH1 -B TS1 CH4-A CH4-B CH4 -A CH4 -B CH3-A CH3-B CH3 -A CH3 -B TS2 CH6-A CH6-B CH6 -A CH6 -B CH5-A CH5-B CH5 -A CH5 -B TS3 CH8-A CH8-B CH8 -A CH8 -B CH7-A CH7-B CH7 -A CH7 -B TS4 CH10-A CH10-B CH10-A CH10-B CH9-A CH9-B CH9 -A CH9-B TS5 CH12-A CH12-B CH12-A CH12-B CH11-A CH11-B CH11-A CH11-B TS6 CH14-
Product Preview DS21Q55 15.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data. Register Name: Register Description: Register Address: Bit # Name Default 7 CH7 0 SSIE1 Software Signaling Insertion Enable 1 08h 6 CH6 0 5 CH5 0 4 CH4 0 3 CH3 0 2 CH2 0 1 CH1 0 0 UCAW 0 Bit 0/Upper CAS Align/Alarm Word (UCAW).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 CH22 0 DS21Q55 SSIE3 Software Signaling Insertion Enable 3 0Ah 6 CH21 0 5 CH20 0 4 CH19 0 3 CH18 0 2 CH17 0 1 CH16 0 0 LCAW 0 Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx) to be sourced from the lower 4 bits of the TS1 register.
Product Preview DS21Q55 15.2.3 Software Signaling Insertion Enable Registers, T1 Mode In T1 mode, only registers SSIE1 through SSIE3 are used since there are only 24 channels in a T1 frame. Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 SSIE1 Software Signaling Insertion Enable 1 08h 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0 Bits 0 to 7/Software Signaling Insertion Enable for and Channels 1 to 8 (CH1 to CH8 ).
Product Preview DS21Q55 17.2.4 Hardware-Based Transmit Signaling In hardware-based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered and inserted to the data stream being input at the TSER pin. Signaling data can be input on a per-channel basis via the transmit-hardware signaling-channel select (THSCS) function.
Product Preview DS21Q55 16. PER-CHANNEL IDLE CODE GENERATION Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used; the remaining channels, CH25–CH32 are not used. The DS21Q55 contains a 64-byte idle code array accessed by the idle array address register (IAAR) and the per-channel idle code register (PCICR).
Product Preview DS21Q55 16.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 GRIC 0 DS21Q55 IAAR Idle Array Address Register 7Eh 6 GTIC 0 5 IAA5 0 4 IAA4 0 3 IAA3 0 2 IAA2 0 1 IAA1 0 0 IAA0 0 Bits 0 to 5/Channel Pointer Address Bits (IAA0 to IAA5). IAA0 is the LSB of the 5-bit Channel Code. Bit 6/Global Transmit Idle Code (GTIC). Setting this bit will cause all transmit idle codes to be set to the value written to the PCICR register.
Product Preview 1 = insert data from the idle code array into the transmit data stream 100 of 248 DS21Q55 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 DS21Q55 TCICE3 Transmit Channel Idle Code Enable Register 3 82h 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 Bits 0 to 7/Transmit Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 DS21Q55 RCICE3 Receive Channel Idle Code Enable Register 3 86h 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 Bits 0 to 7/Receive Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24).
Product Preview DS21Q55 17. CHANNEL BLOCKING REGISTERS The receive-channel blocking registers (RCBR1 /RCBR2/RCBR3/RCBR4) and the transmit-channel blocking registers (TCBR1 /TCBR2 /TCBR3/TCBR4) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN–PRI applications.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 DS21Q55 RCBR3 Receive Channel Blocking Register 3 8Ah 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 Bits 0 to 7/Receive Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 DS21Q55 TCBR3 Transmit Channel Blocking Register 3 8Eh 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 Bits 0 to 7/Transmit Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24).
Product Preview DS21Q55 18. ELASTIC STORES OPERATION The DS21Q55 contains dual two- frame, fully independent elastic stores, one for the receive direction and one for the transmit direction. The transmit- and receive-side elastic stores can be enabled/disabled independent of each other. Also, each elastic store can interface to either a 1.544MHz or 2.048MHz/4.096MHz/8.192MHz/16.384MHz backplane without regard to the backplane rate the other elastic store is interfacing to.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 TESALGN 0 DS21Q55 ESCR Elastic Store Control Register 4Fh 6 TESR 0 5 TESMDM 0 4 TESE 0 3 RESALGN 0 2 RESR 0 1 RESMDM 0 0 RESE 0 Bit 0/Receive Elastic Store Enable (RESE). 0 = elastic store is bypassed 1 = elastic store is enabled Bit 1/Receive Elastic Store Minimum Delay Mode (RESMDM). See Minimum Delay Mode.
Product Preview DS21Q55 Register Name: Register Description: Register Address: SR5 Status Register 5 1Eh Bit # Name Default 6 0 7 0 5 TESF 0 4 TESEM 0 3 TSLIP 0 2 RESF 0 1 RESEM 0 0 RSLIP 0 Bit 0/Receive Elastic Store Slip Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a frame. Bit 1/Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a frame is repeated. Bit 2/Receive Elastic Store Full Event (RESF).
Product Preview DS21Q55 109 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 18.1 Receive Side See the IOCR1 and IOCR2 registers for information on clock and I/O configurations. If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher rate system-clock applications, see the Interleaved PCM Bus Operation section. The user has the option of either providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on frame/multiframe boundaries.
Product Preview DS21Q55 18.2 Transmit Side See the IOCR1 and IOCR2 registers for information on clock and I/O configurations. The operation of the transmit elastic store is very similar to the receive side. If the transmit-side elastic store is enabled a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. For higher rate system-clock applications, see the Interleaved PCM Bus Operation section. Controlled slips in the transmit elastic store are reported in the SR5.
Product Preview DS21Q55 respective network clock signals, the elastic store reset bits (ESCR.2 and ESCR.6) should be toggled from a zero to a one to ensure proper operation. 112 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 19. G.706 INT ERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS21Q55 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in timeslot 0. The user can modify the Sa bit positions; this change in data content will be used to modify the CRC-4 checksum.
Product Preview DS21Q55 20. T1 BIT ORIENTED CODE (BOC) CONTROLLER The DS21Q55 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 20.1 Transmit BOC Bits 0 through 5 in the TFDL register contain the BOC message to be transmitted. Setting BOCC.0 = 1 causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The transmit BOC controller automatically provides the abort sequence.
Product Preview DS21Q55 Register Name: Register Description: Register Address: BOCC BOC Control Register 37h Bit # Name Default 6 0 7 0 5 0 4 RBOCE 0 3 RBR 0 2 RBF1 0 1 RBF0 0 0 SBOC 0 Bit 0/Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the TFDL register. Bits 1 to 2/Receive BOC Filter Bits (RBF0, RBF1). The BOC filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message.
Product Preview DS21Q55 Register Name: Register Description: Register Address: RFDL (RFDL register bit usage when BOCC.4 = 1) Receive FDL Register C0h Bit # Name Default 6 0 7 0 5 RBOC5 0 4 RBOC4 0 3 RBOC3 0 2 RBOC2 0 1 RBOC1 0 0 RBOC0 0 3 RFDLF 0 2 TFDLE 0 1 RMTCH 0 0 RBOC 0 Bit 0/BOC Bit 0 (RBOC0). Bit 1/BOC Bit 1 (RBOC1). Bit 2/BOC Bit 2 (RBOC2). Bit 3/BOC Bit 3 (RBOC3). Bit 4/BOC Bit 4 (RBOC4). Bit 5/BOC Bit 5 (RBOC5). Bit 6/This bit position is unused when BOCC.4 = 1.
Product Preview DS21Q55 Register Name: Register Description: Register Address: IMR8 Interrupt Mask Register 8 25h Bit # Name Default 6 0 7 0 5 BOCC 0 4 RFDLAD 0 3 RFDLF 0 2 TFDLE 0 1 RMTCH 0 0 RBOC 0 Bit 0/Receive BOC Detector Change of State Event (RBOC). 0 = interrupt masked 1 = interrupt enabled Bit 1/Receive FDL Match Event (RMTCH). 0 = interrupt masked 1 = interrupt enabled Bit 2/TFDL Register Empty Event (TFDLE).
Product Preview DS21Q55 21. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY) The DS21Q55, when operated in the E1 mode, provides for access to both the Sa and the Si bits via three different methods. The first method is via a hardware scheme using the RLINK/RLC LK and TLINK/TLCLK pins. The second method involves using the internal RAF /RNAF and TAF/TNAF registers. The third method involves an expanded version of the second method. 21.
Product Preview DS21Q55 Register Name: Register Description: Register Address: RAF Receive Align Frame Register C6h Bit # Name Default 6 0 0 7 Si 0 5 0 0 4 1 0 3 1 0 2 0 0 1 1 0 0 1 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 0/Frame Alignment Signal Bit (1). Bit 1/Frame Alignment Signal Bit (1). Bit 2/Frame Alignment Signal Bit (0). Bit 3/Frame Alignment Signal Bit (1). Bit 4/Frame Alignment Signal Bit (1). Bit 5/Frame Alignment Signal Bit (0). Bit 6/Frame Alignment Signal Bit (0).
Product Preview DS21Q55 Register Name: Register Description: Register Address: TAF Transmit Align Frame Register D0h Bit # Name Default 6 0 0 7 Si 0 5 0 0 4 1 1 3 1 1 2 0 0 1 1 1 0 1 1 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 0/Frame Alignment Signal Bit (1). Bit 1/Frame Alignment Signal Bit (1). Bit 2/Frame Alignment Signal Bit (0). Bit 3/Frame Alignment Signal Bit (1). Bit 4/Frame Alignment Signal Bit (1). Bit 5/Frame Alignment Signal Bit (0). Bit 6/Frame Alignment Signal Bit (0).
Product Preview DS21Q55 21.3 Internal Register Scheme Based On CRC4 Multiframe (Method 3) On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC4 multiframe bit in status register 2 (SR4.1). The host can use the SR4.1 bit to know when to read these registers. The user has 2ms to retrieve the data before it is lost.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 SiF1 0 DS21Q55 RSiNAF Receive Si Bits of the Nonalign Frame C9h 6 SiF3 0 5 SiF5 0 4 SiF7 0 3 SiF9 0 2 SiF11 0 1 SiF13 0 0 SiF15 0 3 RRAF9 0 2 RRAF11 0 1 RRAF13 0 0 RRAF15 0 Bit 0/Si Bit of Frame 15(SiF15). Bit 1/Si Bit of Frame 13(SiF13). Bit 2/Si Bit of Frame 11(SiF11). Bit 3/Si Bit of Frame 9(SiF9). Bit 4/Si Bit of Frame 7(SiF7). Bit 5/Si Bit of Frame 5(SiF5). Bit 6/Si Bit of Frame 3(SiF3).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 RSa4F1 0 DS21Q55 RSa4 Receive Sa4 Bits CBh 6 RSa4F3 0 5 RSa4F5 0 4 RSa4F7 0 3 RSa4F9 0 2 RSa4F11 0 1 RSa4F13 0 0 RSa4F15 0 4 RSa5F7 0 3 RSa5F9 0 2 RSa5F11 0 1 RSa5F13 0 0 RSa5F15 0 Bit 0/Sa4 Bit of Frame 15(RSa4F15). Bit 1/Sa4 Bit of Frame 13(RSa4F13). Bit 2/Sa4 Bit of Frame 11(RSa4F11). Bit 3/Sa4 Bit of Frame 9(RSa4F9 ). Bit 4/Sa4 Bit of Frame 7(RSa4F7). Bit 5/Sa4 Bit of Frame 5(RSa4F5).
Product Preview Register Name: Register Description: Register Address: Bit # Na me Default 7 RSa6F1 0 DS21Q55 RSa6 Receive Sa6 Bits CDh 6 RSa6F3 0 5 RSa6F5 0 4 RSa6F7 0 3 RSa6F9 0 2 RSa6F11 0 1 RSa6F13 0 0 RSa6F15 0 4 RSa7F7 0 3 RSa7F9 0 2 RSa7F11 0 1 RSa7F13 0 0 RSa7F15 0 Bit 0/Sa6 Bit of Frame 15(RSa6F15). Bit 1/Sa6 Bit of Frame 13(RSa6F13). Bit 2/Sa6 Bit of Frame 11(RSa6F11). Bit 3/Sa6 Bit of Frame 9(RSa6F9). Bit 4/Sa6 Bit of Frame 7(RSa6F7). Bit 5/Sa6 Bit of Frame 5(RSa6F5).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 RSa8F1 0 DS21Q55 RSa8 Receive Sa8 Bits CFh 6 RSa8F3 0 5 RSa8F5 0 4 RSa8F7 0 3 RSa8F9 0 2 RSa8F11 0 1 RSa8F13 0 0 RSa8F15 0 Bit 0/Sa8 Bit of Frame 15(RSa8F15). Bit 1/Sa8 Bit of Frame 13(RSa8F13). Bit 2/Sa8 Bit of Frame 11(RSa8F11). Bit 3/Sa8 Bit of Frame 9(RSa8F9). Bit 4/Sa8 Bit of Frame 7(RSa8F7). Bit 5/Sa8 Bit of Frame 5(RSa8F5). Bit 6/Sa8 Bit of Frame 3(RSa8F3). Bit 7/Sa8 Bit of Frame 1(RSa8F1).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 TsiF0 0 DS21Q55 TSiAF Transmit Si Bits of the Align Frame D2h 6 TsiF2 0 5 TsiF4 0 4 TsiF6 0 3 TsiF8 0 2 TsiF10 0 1 TsiF12 0 0 TsiF14 0 Bit 0/Si Bit of Frame 14(TsiF14). Bit 1/Si Bit of Frame 12(TsiF12). Bit 2/Si Bit of Frame 10(TsiF10). Bit 3/Si Bit of Frame 8(TsiF8). Bit 4/Si Bit of Frame 6(TsiF6). Bit 5/Si Bit of Frame 4(TsiF4). Bit 6/Si Bit of Frame 2(TsiF2). Bit 7/Si Bit of Frame 0(TsiF0).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 TsiF1 0 DS21Q55 TSiNAF Transmit Si Bits of the Nonalign Frame D3h 6 TsiF3 0 5 TsiF5 0 4 TsiF7 0 3 TsiF9 0 2 TsiF11 0 1 TsiF13 0 0 TSiF15 0 3 TRAF9 0 2 TRAF11 0 1 TRAF13 0 0 TRAF15 0 Bit 0/Si Bit of Frame 15(TSiF15). Bit 1/Si Bit of Frame 13(TsiF13). Bit 2/Si Bit of Frame 11(TsiF11). Bit 3/Si Bit of Frame 9(TsiF9). Bit 4/Si Bit of Frame 7(TsiF7). Bit 5/Si Bit of Frame 5(TsiF5).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 TSa4F1 0 DS21Q55 TSa4 Transmit Sa4 Bits D5h 6 TSa4F3 0 5 TSa4F5 0 4 TSa4F7 0 3 TSa4F9 0 2 TSa4F11 0 1 TSa4F13 0 0 TSa4F15 0 4 TSa5F7 0 3 TSa5F9 0 2 TSa5F11 0 1 TSa5F13 0 0 TSa5F15 0 Bit 0/Sa4 Bit of Frame 15(TSa4F15). Bit 1/Sa4 Bit of Frame 13(TSa4F13). Bit 2/Sa4 Bit of Frame 11(TSa4F11). Bit 3/Sa4 Bit of Frame 9(TSa4F9). Bit 4/Sa4 Bit of Frame 7(TSa4F7). Bit 5/Sa4 Bit of Frame 5(TSa4F5).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 TSa6F1 0 DS21Q55 TSa6 Transmit Sa6 Bits D7h 6 TSa6F3 0 5 TSa6F5 0 4 TSa6F7 0 3 TSa6F9 0 2 TSa6F11 0 1 TSa6F13 0 0 TSa6F15 0 4 TSa7F7 0 3 TSa7F9 0 2 TSa7F11 0 1 TSa7F13 0 0 TSa7F15 0 Bit 0/Sa6 Bit of Frame 15(TSa6F15). Bit 1/Sa6 Bit of Frame 13(TSa6F13). Bit 2/Sa6 Bit of Frame 11(TSa6F11). Bit 3/Sa6 Bit of Frame 9(TSa6F9). Bit 4/Sa6 Bit of Frame 7(TSa6F7). Bit 5/Sa6 Bit of Frame 5(TSa6F5).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 TSa8F1 0 DS21Q55 TSa8 Transmit Sa8 Bits D9h 6 TSa8F3 0 5 TSa8F5 0 4 TSa8F7 0 3 TSa8F9 0 2 TSa8F11 0 1 TSa8F13 0 0 TSa8F15 0 Bit 0/Sa8 Bit of Frame 15(TSa8F15). Bit 1/Sa8 Bit of Frame 13(TSa8F13). Bit 2/Sa8 Bit of Frame 11(TSa8F11). Bit 3/Sa8 Bit of Frame 9(TSa8F9). Bit 4/Sa8 Bit of Frame 7(TSa8F7). Bit 5/Sa8 Bit of Frame 5(TSa8F5). Bit 6/Sa8 Bit of Frame 3(TSa8F3). Bit 7/Sa8 Bit of Frame 1(TSa8F1).
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 SiAF 0 DS21Q55 TSACR Transmit Sa Bit Control Register DAh 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 0/Additional Bit 8 Insertion Control Bit (Sa8). 0 = do not insert data from the TSa8 register into the transmit data stream 1 = insert data from the TSa8 register into the transmit data stream Bit 1/Additional Bit 7 Insertion Control Bit (Sa7).
Product Preview DS21Q55 22. HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode). Each HDLC controller has 128 byte buffers in both the transmit and receive paths. When used with time slots, the user can select any time slot or multiple time slots, contiguous or noncontiguous, as well as any specific bits within the time slot(s) to assign to the HDLC controllers.
Product Preview DS21Q55 HDLC CONTROLLER REGISTERS Table 24-1 NAME FUNCTION CONTROL/CONFIGURATION H1TC, HDLC #1 Transmit Control Register General control over the transmit HDLC controllers H2TC, HDLC #2 Transmit Control Register H1RC, HDLC #1 Receive Control Register General control over the receive HDLC controllers H2RC, HDLC #2 Receive Control Register H1FC, HDLC #1 FIFO Control Register Sets high watermark for receiver and low watermark for H2FC, HDLC #2 FIFO Control Register transmitter STATUS/INFORMA
Product Preview DS21Q55 22.2 HDLC Configuration Basic configuration of the HDLC controllers is accomplished via the HxTC and HxRC registers. Operating features such as CRC generation, zero stuffer, transmit and receive HDLC mapping options, and idle flags are selected here. Also, the HDLC controllers are reset via these registers.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 RHR 0 DS21Q55 H1RC, H2RC HDLC #1 Receive Control, HDLC #2 Receive Control 31h, 32h 6 RHMS 0 5 0 4 0 3 0 2 0 1 0 0 RSFD 0 Bit 0/Receive SS7 Fill In Signal Unit Delete (RSFD). 0 = normal operation. All FISUs are stored in the receive FIFO and reported to the host. 1 = When a consecutive FISU having the same BSN the previous FISU is detected, it is deleted without host intervention.
Product Preview DS21Q55 22.2.1 FIFO Control Control of the transmit and receive FIFOs is accomplished via the FIFO control (HxFC). The FIFO control register sets the watermarks for both the transmit and receive FIFO. Bits 3–5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register SR6 or SR7 will be set.
Product Preview DS21Q55 22.3 HDLC Mapping 22.3.1 Receive The HDLC controllers need to be assigned a space in the T1/E1 bandwidth in which they will transmit and receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1), or to channels. If mapped to channels, then any channel or combination of channels, contiguous or not, can be assigned to an HDLC controller. When assigned to a channel(s) any combination of bits within the channel(s) can be avoided.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 RCB8SE 0 DS21Q55 H1RTSBS, H2RTSBS HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6h 6 RCB7SE 0 5 RCB6SE 0 4 RCB5SE 0 3 RCB4SE 0 2 RCB3SE 0 1 RCB2SE 0 0 RCB1SE 0 Bit 0/Receive Channel Bit 1 Suppress Enable/Sa8 Bit Enable (RCB1SE ). LSB of the channel. Set to one to stop this bit from being used when the HDLC is mapped to time slots.
Product Preview DS21Q55 22.3.2 Transmit The HxTCS1–HxTCS4 registers are used to assign the transmit controllers to channels 1–24 (T1) or 1–32 (E1), according to the following table.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 TCB8SE 0 DS21Q55 H1TTSBS, H2TTSBS HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select 9Bh, Abh 6 TCB7SE 0 5 TCB6SE 0 4 TCB5SE 0 3 TCB4SE 0 2 TCB3SE 0 1 TCB2SE 0 0 TCB1SE 0 Bit 0/Transmit Channel Bit 1 Suppress Enable / Sa8 Bit Enable (TCB1SE). LSB of the channel. Set to one to stop this bit from being used.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 SR6, SR7 HDLC #1 Status Register 6 HDLC #2 Status Register 7 20h, 22h 6 TMEND 0 5 RPE 0 4 RPS 0 3 RHWM 0 2 RNE 0 1 TLWM 0 0 TNF 0 Bit 0/Transmit FIFO Not Full Condition (TNF). Set when the transmit 128-byte FIFO has at least one byte available. Bit 1/Transmit FIFO Below Low Watermark Condition (TLWM).
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 IMR6, IMR7 HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 21h, 23h 6 TMEND 0 5 RPE 0 4 RPS 0 3 RHWM 0 2 RNE 0 1 TLWM 0 0 TNF 0 Bit 0/Transmit FIFO Not Full Condition (TNF). 0 = interrupt masked 1 = interrupt enabled–interrupts on rising edge only Bit 1/Transmit FIFO Below Low Watermark Condition (TLWM).
Product Preview DS21Q55 Register Name: Register Description: INFO5, INFO6 HDLC #1 Information Register HDLC #2 Information Register 2Eh, 2Fh Register Address: Bit # Name Default 7 0 6 0 5 TEMPTY 0 4 TFULL 0 3 REMPTY 0 2 PS2 0 1 PS1 0 0 PS0 0 Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of the receive FIFO.
Product Preview DS21Q55 22.3.3 FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer.
Product Preview DS21Q55 22.3.5 HDLC FIFOS Register Name: Register Description: Register Address: Bit # Name Default 7 THD7 0 H1TF, H2TF HDLC # 1 Transmit FIFO, HDLC # 2 Transmit FIFO 9Dh, Adh 6 THD6 0 5 THD5 0 4 THD4 0 3 THD3 0 2 THD2 0 1 THD1 0 0 THD0 0 1 RHD1 0 0 RHD0 0 Bit 0/Transmit HDLC Data Bit 0 (THD0). LSB of a HDLC packet data byte. Bit 1/Transmit HDLC Data Bit 1 (THD1). Bit 2/Transmit HDLC Data Bit 2 (THD2). Bit 3/Transmit HDLC Data Bit 3 (THD3). Bit 4/Transmit HDLC Data Bit 4 (THD4).
Product Preview DS21Q55 22.4 Receive HDLC Code Example Below is an example of a receive HDLC routine for controller #1. 1) Reset receive HDLC controller 2) Set HDLC mode, mapping, and high watermark 3) Start new message buffer 4) Enable RPE and RHWM interrupts 5) Wait for interrupt 6) Disable RPE and RHWM interrupts 7) Read HxRPBA register.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 RFDL7 0 DS21Q55 RFDL Receive FDL Register C0h 6 RFDL6 0 5 RFDL5 0 4 RFDL4 0 3 RFDL3 0 2 RFDL2 0 1 RFDL1 0 0 RFDL0 0 Bit 0/Receive FDL Bit 0 (RFDL0). LSB of the Received FDL Code. Bit 1/Receive FDL Bit 1 (RFDL1). Bit 2/Receive FDL Bit 2 (RFDL2). Bit 3/Receive FDL Bit 3 (RFDL3). Bit 4/Receive FDL Bit 4 (RFDL4). Bit 5/Receive FDL Bit 5 (RFDL5). Bit 6/Receive FDL Bit 6 (RFDL6). Bit 7/Receive FDL Bit 7 (RFDL7).
Product Preview DS21Q55 22.5.2 Transmit Section The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TFDL). When a new value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream.
Product Preview DS21Q55 23. LINE INTERFACE UNIT (LIU) The LIU in the DS21Q55 contains three sections: the receiver, which handles clock and data recovery; the transmitter, whic h wave-shapes and drives the network line; and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described below. The LIU has its own T1/E1 mode select bit and can operate independently of the framer function.
Product Preview DS21Q55 23.1 LIU Operation The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is transformer coupled into the RTIP and RRING pins of the DS21Q55. The user has the option to use internal termination, software selectable for 75O/100O/120O applications, or external termination.
Product Preview DS21Q55 23.2.1 Receive Level Indicator and Threshold Interrupt The DS21Q55 reports the signal strength at RTIP and RRING in 2.5dB increments through RL3–RL0 located in Information Register 2 (INFO2). This feature is helpful when trouble-shooting lineperformance problems. The DS2155 can initiate an interrupt whenever the input falls below a certain level through the input- level under-threshold indicator (SR1.7).
Product Preview DS21Q55 23.3 LIU Transmitter The DS21Q55 uses a phase- lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the transmitter meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user will select which waveform is to be generated by setting the ETS bit (LIC2.7) for E1 or T1 operation, then programming the L2/L1/L0 bits in register LIC1 for the appropriate application. A 2.
Product Preview DS21Q55 23.4 MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. A prescaler will divide the 16MHz, 8MHz, or 4MHz clock down to 2.048MHz. There is an onboard PLL for the jitter attenuator that will convert the 2.048MHz clock to a 1.544MHz rate for T1 applications. Setting JAMUX (LIC2.
Product Preview DS21Q55 23.7 LIU Control Registers Register Name: Register Description: Register Address: LIC1 Line Interface Control 1 78h Bit # Name Default 6 L1 0 7 L2 0 5 L0 0 4 EGL 0 3 JAS 0 2 JABDS 0 1 DJA 0 0 TPD 0 Bit 0/Transmit Power-Down (TPD). 0 = powers down the transmitter and tristates the TTIP and TRING pins 1 = normal transmitter operation Bit 1/Disable Jitter Attenuator (DJA).
Product Preview DS21Q55 E1 Mode L2 L1 L0 0 0 0 0 0 1 1 0 0 1 0 1 *TT0 and TT1 of LIC4 APPLICATION N (1) RETURN LOSS 75O normal 1:2 NM 120O normal 1:2 NM 75O with high return loss* 1:2 21dB 120O with high return loss* 1:2 21dB register must be set to zero in this configuration. Rt (1) 0 0 6.2O 11.6O APPLICATION DSX-1 (0 to 133 feet)/0dB CSU DSX-1 (133 to 266 feet) DSX-1 (266 to 399 feet) DSX-1 (399 to 533 feet) DSX-1 (533 to 655 feet) -7.5dB CSU -15dB CSU -22.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 TLBC Transmit Line Build-Out Control 7Dh 6 AGCE 0 5 GC5 0 4 GC4 0 3 GC3 0 2 GC2 0 1 GC1 0 0 GC0 0 Bit 0–5 Gain Control Bits 0–5 (GC0– GC5). The GC0 through GC5 bits control the gain setting for the nonautomatic gain mode. Use the tables below for setting the recommended values. The LB (line build-out) column refers to the value in the L0– L2 bits in LIC1 (Line Interface Control 1) register.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 ETS 0 DS21Q55 LIC2 Line Interface Control 2 79h 6 LIRST 0 5 IBPV 0 4 TUA1 0 3 JAMUX 0 2 0 1 SCLD 0 0 CLDS 0 Bit 0 Custom Line Driver Select (CLDS). Setting this bit to a one will redefine the operation of the transmit line driver. When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.7 = 0, then the device will generate a square wave at the TTIP and TRING outputs instead of a normal waveform.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 LIC3 Line Interface Control 3 7Ah 6 TCES 0 5 RCES 0 4 MM1 0 3 MM0 0 2 RSCLKE 0 1 TSCLKE 0 0 TAOZ 0 Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (Customer Disconnect Indication Signal) at TTIP and TRING. The transmission of this data pattern is always timed off of TCLK. 0 = disabled 1 = enabled Bit 1/Transmit Synchronization G.703 Clock Enable (TSCLKE).
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 CMIE 0 LIC4 Line Interface Control 4 7Bh 6 CMII 0 5 MPS1 0 4 MPS0 0 3 TT1 0 2 TT0 0 1 RT1 0 0 RT0 0 Bits 0 to 1/Receive Termination Select (RT0 to RT1).
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 BSYNC 0 INFO2 Information Register 2 11h 6 0 5 TCLE 0 4 TOCD 0 3 RL3 0 2 RL2 0 1 RL1 0 0 RL0 0 Bits 0 to 3/Receive Level Bits (RL0 to RL3). Real-time bits RL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RECEIVE LEVEL (dB) Greater than -2.5 -2.5 to -5.0 -5.0 to -7.5 -7.5 to -10.0 -10.0 to -12.5 -12.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 RLT3 0 CCR4 Common Control Register 4 73h 6 RLT2 0 5 RLT1 0 4 RLT0 0 3 — 0 2 — 0 1 — 0 0 — 0 Bit 0/Unused, must be set to zero for proper operation. Bit 1/Unused, must be set to zero for proper operation. Bit 2/Unused, must be set to zero for proper operation. Bit 3/Unused, must be set to zero for proper operation.
Product Preview Register Name: Register Description: Register Address: Bit # Name Default 7 ILUT 0 DS21Q55 SR1 Status Register 1 16h 6 TIMER 0 5 RSCOS 0 4 JALT 0 3 LRCL 0 2 TCLE 0 1 TOCD 0 0 LOLITC 0 Bit 0/Loss of Line Interface Transmit Clock Condition (LOLITC). Set when TCLKI has not transitioned for one channel time. Bit 1/Transmit Open Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING outputs are open-circuited.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 IMR1 Interrupt Mask Register 1 17h 6 TIMER 0 5 RSCOS 0 4 JALT 0 3 LRCL 0 2 TCLE 0 1 TOCD 0 0 LOLITC 0 Bit 0/Loss of Transmit Clock Condition (LOLITC). 0 = interrupt masked 1 = interrupt enabled–generates interrupts on rising and falling edges Bit 1/Transmit Open Circuit Detect Condition (TOCD).
Product Preview DS21Q55 23.8 Recommended Circuits BASIC INTERFACE Figure 25-4 VDD DS21Q55 2:1 TTIP TRANSMIT LINE C DV DD 0.1µF .01µF DV SS TRING TVDD 0.1µF 10µF + TVSS RV DD 1:1 RTIP 0.1µF 10µF + RV SS RECEIVE LINE RRING R R 0.1µF NOTES: 1) All resistor values are ±1%. 2) Resistors R should be set to 60O each if the internal receive-side termination feature is enabled. When this feature is disabled, R = 37.
Product Preview DS21Q55 PROTECTED INTERFACE USING INTERNAL RECEIVE TERMINATION Figure 25-5 VDD D1 VDD D2 DS21Q55 2:1 0.1µF .01µF TTIP F1 TRANSMIT LINE S1 C1 DV SS 0.1µF F2 DV DD X2 D4 TRING D3 0.1µF TVDD 68µF + 10µF + TVS S VDD D5 D6 1:1 F3 + RV SS 0.1µF D8 F4 10µF RTIP S2 RECEIV E LINE 0.1µF RV DD X1 RRING D7 60 60 0.1µF NOTES: 1) 2) 3) 4) 5) 6) All resistor values are ±1%. X1 and X2 are very low DCR transformers C1 = 1µF ceramic.
Product Preview DS21Q55 23.9 Component Specifications TRANSFORMER SPECIFICATIONS Table 25-1 SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) ±2% 600µH minimum 1.0µH maximum 40pF maximum 1.0O maximum 2.0O maximum 1.2O maximum 1.
Product Preview DS21Q55 E1 TRANSMIT PULSE TEMPLATE Figure 25-6 1.2 1.1 269ns SCALED AMPLITUDE (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (ns) T1 TRANSMIT PULSE TEMPLATE Figure 25-7 1.2 MAXIMUM CURVE UI Time Amp. 1.1 1.0 -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 0.9 0.
Product Preview DS21Q55 JITTER TOLERANCE (T1 MODE) Figure 25-8 UNIT INTERVALS (UIpp) 1K DS21Q55 Tolerance 100 TR 62411 (Dec. 90) 10 ITU-T G.823 1 0.1 1 10 100 1K FREQUENCY (Hz) 10K 100K JITTER TOLERANCE (E1 MODE) Figure 25-9 UNIT INTERVALS (UIpp) 1k DS21Q55 Tolerance 100 40 10 1.5 1 0.1 Minimum Tolerance Level as per ITU G.823 1 10 20 100 1k FREQUENCY (Hz) 168 of 248 0.2 2.4k 10k 18k 100k 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.
Product Preview DS21Q55 JITTER ATTENUATION (T1 MODE) Figure 25-10 -20dB A rve Cu TR 62411 (Dec. 90) Prohibited Area -40dB B rve Cu JITTER ATTENUATION (dB) 0dB DS21Q55 T1 MODE -60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K JITTER ATTENUATION (E1 MODE) Figure 25-11 JITTER ATTENUATION (dB) 0dB ITU G.7XX Prohibited Area TBR12 Prohibited Area -20dB DS21Q55 E1 MODE -40dB -60dB 1 10 100 1K FREQUENCY (Hz) 169 of 248 10K 100K 012103 Please contact telecom.support@dalsemi.
Product Preview DS21Q55 24. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION The DS21Q55 has the ability to generate and detect a repeating bit pattern from 1 bit to 8 bits or 16 bits in length. This function is available only in T1 mode . To transmit a pattern, the user will load the pattern to be sent into the transmit code definition registers (TCD1 and TCD2) and select the proper length of the pattern by setting the TC0 and TC1 bits in the in-band code-control (IBCC) register.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default IBCC In-Band Code Control Register B6h 7 TC1 0 6 TC0 0 5 RUP2 0 4 RUP1 0 3 RUP0 0 2 RDN2 0 1 RDN1 0 0 RDN0 0 Bits 0 to 2/Receive -Down Code Length Definition Bits (RDN0 to RDN2). RDN2 0 0 0 0 1 1 1 1 RDN1 0 0 1 1 0 0 1 1 RDN0 0 1 0 1 0 1 0 1 LENGTH SELECTED (Bits) 1 2 3 4 5 6 7 8/16 Bits 3 to 5/Receive -Up Code Length Definition Bits (RUP0 to RUP2).
Product Preview DS21Q55 Register Name: Register Description: Register Address: TCD1 Transmit Code Definition Register 1 B7h Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit 0/Transmit Code Definition Bit 0 (C0). A “don’t care” if a 5-, 6-, or 7-bit length is selected. Bit 1/Transmit Code Definition Bit 1 (C1). A “don’t care” if a 5-bit or 6-bit length is selected. Bit 2/Transmit Code Definition Bit 2 (C2). A “don’t care” if a 5-bit length is selected.
Product Preview DS21Q55 Register Name: Register Description: Register Address: RUPCD1 Receive -Up Code Definition Register 1 B9h Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive -Up Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 1/Receive -Up Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 6-bit length is selected.
Product Preview DS21Q55 Register Name: Register Description: Register Address: RDNCD1 Receive -Down Code Definition Register 1 BBh Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive -Down Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 1/Receive -Down Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 6-bit length is selected.
Product Preview DS21Q55 Register Name: Register Description: Register Address: RDNCD2 Receive -Down Code Definition Register 2 BCh Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit 0/Receive -Down Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 1/Receive -Down Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 2/Receive -Down Code Definition Bit 2 (C2).
Product Preview DS21Q55 Register Name: Register Description: Register Address: RSCD1 Receive -Spare Code Definition Register 1 BEh Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive -Spare Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 1/Receive -Spare Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 6-bit length is selected.
Product Preview DS21Q55 25. BERT FUNCTION The BERT (Bit Error Rate Tester) block can generate and detect both pseudorandom and repeating-bit patterns. It is used to test and stress data-communication links.
Product Preview DS21Q55 25.1 BERT Register Description Register Name: Register Description: Register Address: Bit # Name Default 7 TC 0 BC1 BERT Control Register 1 E0h 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0 Bit 0/Force Resynchronization (RESYNC). A low-to-high transition will force the receive BERT synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 EIB2 0 BC2 BERT Control Register 2 E1h 6 EIB1 0 5 EIB0 0 4 SBE 0 3 RPL3 0 2 RPL2 0 1 RPL1 0 0 RPL0 0 Bits 0 to 3/Repetitive Pattern Length Bit 3 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is the MSB of a nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive BERT is programmed for a pseudorandom pattern.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 BIC BER T Interface Control Register EAh 6 RFUS 0 5 0 4 TBAT 0 3 TFUS 0 2 0 1 BERTDIR 0 0 BERTEN 0 Bit 0/BERT Enable (BERTEN). 0 = BERT disabled 1 = BERT enabled Bit 1/BERT Direction (BERTDIR). 0 = network 1 = system Bit 2/Unused, must be set to zero for proper operation. Bit 3/Transmit Framed/Unframed Select (TFUS). For T1 mode only.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 SR9 Status Register 9 26h 6 BBED 0 5 BBCO 0 4 BEC0 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0 Bit 0/BERT in Synchronization Condition (BSYNC). Will be set when the incoming pattern matches for 32 consecutive bit positions. Refer to BSYNC in INFO2 register for a real-time version of this bit. Bit 1/BERT Receive Loss Of Synchronization Condition (BRLOS).
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 IMR9 Interrupt Mask Register 9 27h 6 BBED 0 5 BBCO 0 4 BEC0 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0 Bit 0/BERT in Synchronization Condition (BSYNC). 0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges Bit 1/Receive Loss Of Synchronization Condition (BRLOS).
Product Preview DS21Q55 25.2 BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is less than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern.
Product Preview DS21Q55 25.3 BERT Bit Counter Once BERT has achieved synchronization, this 32-bit counter will increment for each data bit (i.e., clock) received. Toggling the LC control bit in BC1 can clear this counter, which saturates when full and will set the BBCO status bit.
Product Preview DS21Q55 25.4 BERT Error Counter Once BERT has achieved synchronization, this 24-bit counter will increment for each data bit received in error. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and will set the BECO status bit.
Product Preview DS21Q55 26. PAYLOAD ERROR INSERTION FUNCTION An error- insertion function is available in the DS21Q55 and is used to create errors in the payload portion of the T1 frame in the transmit path. Errors can be inserted over the entire frame or on a per-channel basis. The user can select all DS0s or any combination of DS0s. See Special Per-Channel Registration Operation for information on using the per-channel function. Errors are created by inverting the last bit in the count sequence.
Product Preview DS21Q55 Register Name: Register Description: Register Address: ERC Error Rate Control Register EBh Bit # Name Default 6 0 7 WNOE 0 5 0 4 CE 0 3 ER3 0 2 ER2 0 1 ER1 0 0 ER0 0 Bits 0 to 3/Error Insertion Rate Select Bits (ER0 to ER3).
Product Preview DS21Q55 26.1 Number Of Error Registers The number of error registers determine how many errors will be generated. Up to 1023 errors can be generated. The host will load the number of errors to be generated into the NOE1 and NOE2 registers. The host can also update the number of errors to be created by first loading the prescribed value into the NOE registers and then toggling the WNOE bit in the error rate control registers.
Product Preview DS21Q55 26.1.1 Number Of Errors Left Register The host can read the NOELx registers at any time to determine how many errors are left to be inserted. Register Name: Register Description: Register Address: NOEL1 Number Of Errors Left 1 EEh Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bits 0 to 7/Number of Errors Left Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter.
Product Preview DS21Q55 27. INTERLEAVED PCM BUS OPERATION In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS21Q55 can be configured to allow PCM data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. The DS21Q55 can be configured for channel or frame interleave. The interleaved PCM bus option (IBO) supports three bus speeds. The 4.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 IBOC Interleave Bus Operation Control Register C5h 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 0 DA0 0 Bits 0 to 2/Device Assignment bits (DA0 to DA2).
Product Preview DS21Q55 IBO EXAMPLE Figure 29-1 RSYSCLK TSYSCLK RSYSCLK TSYSCLK RSYNC TSSYNC RSYNC TSSYNC RSIG TSIG RSIG TSIG TSER DS21Q55 #1 RSER TSER DS21Q55 #3 RSER 8.192MHz System Clock In System 8kHz Frame Sync In PCM Signaling Out PCM Signaling In PCM Data In PCM Data Out RSYSCLK TSYSCLK RSYSCLK TSYSCLK RSYNC TSSYNC RSYNC TSSYNC RSIG TSIG RSIG TSIG TSER DS21Q55 #2 RSER TSER DS21Q55 #4 RSER 192 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.
Product Preview DS21Q55 28. EXTENDED SYSTEM INFORMATION BUS (ESIB) The ESIB allows two DS21Q55s to share an 8-bit CPU bus for the purpose of reporting alarms and interrupt status as a group. With a single bus read, the host can be updated with alarm or interrupt status from all members of the group. There are two control registers, ESIBCR1 and ESIBCR2, and four information registers, ESIB1, ESIB2, ESIB3, and ESIB4. As an example, eight DS21Q55s can be grouped into an ESIB group.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default 7 0 ESIBCR1 Extended System Information Bus Control Register 1 B0h 6 0 5 0 4 0 3 ESIBSEL2 0 2 ESIBSEL1 0 1 ESIBSEL0 0 0 ESIEN 0 Bit 0/Extended System Information Bus Enable (ESIEN). 0 = disabled 1 = enabled Bits 1 to 3/Output Data Bus Line Select (ESIBSEL0 to ESIBSEL2). These bits tell the device which data bus bit to output the ESIB data on when one of the ESIB information registers is accessed.
Product Preview DS21Q55 Register Name: Register Description: Register Address: Bit # Name Default ESIBCR2 Extended System Information Bus Control Register 2 B1h 7 0 6 ESI4SEL2 0 5 ESI4SEL1 0 4 ESI4SEL0 0 3 0 2 ESI3SEL2 0 1 ESI3SEL1 0 0 ESI3SEL0 0 Bits 0 to 2/Address ESI3 Data Output Select (ESI3SEL0 to ESI3SEL2). These bits select what status is to be output when the device decodes an ESI3 address during a bus read operation.
Product Preview DS21Q55 Register Name: Register Description: Register Address: ESIB1 Extended System Information Bus Register 1 B2h Bit # Name Default 6 DISn 0 7 DISn 0 5 DISn 0 4 DISn 0 3 DISn 0 2 DISn 0 1 DISn 0 0 DISn 0 Bits 0 to 7/Device Interrupt Status (DISn). Causes all devices participating in the ESIB group to output their interrupt status on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR1 register.
Product Preview DS21Q55 29. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER The DS21Q55 contains an on-chip clock synthesizer that generates a user-selectable clock referenced to the recovered receive clock (RCLK). The synthesizer uses a phase- locked loop to generate low-jitter clocks. Common applications include generation of port and back plane system clocks.
Product Preview DS21Q55 30. FRACTIONAL T1/E1 SUPPORT The DS21Q55 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDNPRI applications. This is accomplished by assigning an alternate function to the RCHCLK and TCHCLK pins. When the gapped clock feature is enabled, a gated clock is output on the RCHCLK and/or TCHCLK pins.
Product Preview DS21Q55 31. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT The DS21Q55 is an MCM consisting of 4 DS2155s. Each device has its on JTAG state machine and therefore is treated as 4 separate devices when testing. The following description refers to the DS2155 JTAG function. The DS2155 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGH-Z, CLAMP, and IDCODE (Figure 21).
Product Preview DS21Q55 TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK (Figure 34-2). Test-Logic-Reset Upon power-up, the TAP controller will be in the test-logic-reset state. The instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. Run-Test-Idle The run-test- idle is used between scan operations or during specific tests.
Product Preview DS21Q55 Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the test- logic-reset state.
Product Preview DS21Q55 TAP CONTROLLER STATE DIAGRAM Figure 34-2 1 0 Test Logic Reset 0 Run Test/ Idle 1 1 Select DR-Scan Select IR-Scan 0 0 1 1 Capture DR Capture IR 0 0 Shift DR Shift IR 0 1 0 1 1 Exit DR Exit IR 0 1 0 Pause DR Pause IR 0 1 0 1 0 1 0 Exit2 DR Exit2 IR 1 1 Update DR Update IR 1 1 0 202 of 248 0 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 31.1 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO.
Product Preview DS21Q55 SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan register via JTDI using the shift- DR state.
Product Preview DS21552 DS21Q55 0002h 31.2 Test Registers IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An optional test register has been included with the DS2155 design. This test register is the identification register and is used with the IDCODE instruction and the test- logic-reset state of the TAP controller. 31.
Product Preview DS21Q55 BOUNDARY SCAN CONTROL BITS Table 34-4 NXA = Not Externally Available BIT 2 1 0 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 – 37 38 39 40 41 42 43 44 45 46 47 SYMBOL RCHBLK JTMS BPCLK JTCLK JTRST RCL (NXA) JTDI UOP0 (NXA) UOP1 (NXA) JTDO BTS LIUC 8XCLK (NXA) TSTRST UOP2 (NXA) RTIP RRING RVDD RVSS RVSS MCLK XTALD (NXA) UOP3 (NXA) RVSS INT N/C N/C N/
Product Preview BIT 53 52 51 50 49 48 47 46 45 44 DS21Q55 PIN 48 49 50 51 52 53 54 55 – 43 42 41 40 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 SYMBOL TSIG TESO (NXA) TDATA (NXA) TSYSCLK TSSYNC TCHCLK ESIBS1.cntl ESIBS1 MUX BUS.
Product Preview BIT DS21Q55 PIN SYMBOL TYPE 97 RFSYNC – RSYNC.cntl 98 RSYNC 99 RLOS/LOTC 100 RSYSCLK 7 6 5 4 3 CONTROL BIT DESCRIPTION O – I/O O I 0 = RSYNC is an input; 1 = RSYNC is an output 32. FUNCTIONAL TIMING DIAGRAMS 32.1 T1 Mode RECEIVE SIDE D4 TIMING Figure 35-1 FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 RFSYNC RSYNC 1 RSYNC 2 3 RSYNC RLCLK RLINK 4 NOTES: 1) 2) 3) 4) RSYNC in the frame mode (IOCR1.5 = 0) and double-wide frame sync is not enabled (IOCR1.6 = 0).
Product Preview DS21Q55 RECEIVE SIDE ESF TIMING Figure 35-2 FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 1 RSYNC RFSYNC 2 RSYNC RSYNC RLCLK 3 4 5 RLINK TLCLK 6 TLINK 7 NOTES: 1) 2) 3) 4) 5) 6) 7) RSYNC in frame mode (IOCR1.4 = 0) and double wide frame sync is not enabled (IOCR1.6 = 0). RSYNC in frame mode (IOCR1.4 = 0) and double wide frame sync is enabled (IOCR1.6 = 1). RSYNC in multiframe mode (IOCR1.4 = 1). ZBTSI mode disabled (T1RCR2.2 = 0).
Product Preview DS21Q55 RECEIVE SIDE BOUNDARY TIMING (With Elastic Store Disabled) Figure 35-3 RCLK CHANNEL 23 RSER CHANNEL 24 CHANNEL 1 LSB LSB MSB F MSB RSYNC RFSYNC RSIG CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B CHANNEL 1 A RCHCLK RCHBLK 1 RLCLK RLINK 2 NOTES: 1) RCHBLK is programmed to block channel 24. 2) Shown is RLINK/RLCLK in the ESF framing mode. 210 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 RECEIVE SIDE 1.544MHz BOUNDARY TIMING (With Elastic Store Enabled) Figure 35-4 RSYSCLK CHANNEL 23 RSER CHANNEL 24 CHANNEL 1 LSB LSB MSB F MSB RSYNC1 RMSYNC 2 RSYNC RSIG CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B CHANNEL 1 A RCHCLK RCHBLK 3 NOTES: 1) RSYNC is in the output mode (IOCR1.4 = 0). 2) RSYNC is in the input mode (IOCR1.4 = 1). 3) RCHBLK is programmed to block channel 24. 211 of 248 012103 Please contact telecom.support@dalsemi.
Product Preview DS21Q55 RECEIVE SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled) Figure 35-5 RSYSCLK RSER RSYNC 1 CHANNEL 31 CHANNEL 32 CHANNEL 1 LSB LSB MSB 2 RMSYNC RSYNC 3 RSIG A CHANNEL 31 B C/A D/B A CHANNEL 32 B C/A D/B CHANNEL 1 RCHCLK RCHBLK 4 NOTES: 1) 2) 3) 4) 5) RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one. RSYNC is in the output mode (IOCR1.4 = 0). RSYNC is in the input mode (IOCR1.4 = 1).
Product Preview DS21Q55 TRANSMIT SIDE D4 TIMING Figure 35-6 FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 1 TSYNC TSSYNC TSYNC TSYNC 2 3 TLCLK TLINK 4 NOTES: 1) 2) 3) 4) TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.1 = 0). TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.1 = 1). TSYNC in the multiframe mode (IOCR1.2 = 1).
Product Preview DS21Q55 TRANSMIT SIDE ESF TIMING Figure 35-7 FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 TSYNC1 TSSYNC TSYNC 2 3 TSYNC TLCLK 4 TLINK TLCLK 5 TLINK 6 NOTES: 1) 2) 3) 4) TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.3 = 0). TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.3 = 1). TSYNC in multiframe mode (IOCR1.2 = 1).
Product Preview DS21Q55 TRANSMIT SIDE BOUNDARY TIMING (With Elastic Store Disabled) Figure 35-8 TCLK CHANNEL 1 LSB TSER F CHANNEL 2 MSB LSB MSB LSB MSB TSYNC1 TSYNC2 CHANNEL 1 TSIG D/B A B CHANNEL 2 C/A D/B A B C/A D/B TCHCLK TCHBLK 3 TLCLK TLINK 4 DON'T CARE NOTES: 1) 2) 3) 4) TSYNC is in the output mode (IOCR1.1 = 1). TSYNC is in the input mode (IOCR1.1 = 0). TCHBLK is programmed to block channel 2. Shown is TLINK/TLCLK in the ESF framing mode.
Product Preview DS21Q55 TRANSMIT SIDE 1.544MHz BOUNDARY TIMING (With Elastic Store Enabled) Figure 35-9 TSYSCLK CHANNEL 23 CHANNEL 24 CHANNEL 1 LSB MSB TSER LSB F MSB TSSYNC CHANNEL 23 TSIG A B CHANNEL 24 C/A D/B A B CHANNEL 1 C/A D/B A TCHCLK TCHBLK 1 NOTE: 1) TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored during channel 24). 216 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.
Product Preview DS21Q55 TRANSMIT SIDE 2.048MHz BOUNDARY TIMING (With Elastic Store Enabled) Figure 35-11 TSYSCLK CHANNEL 31 TSER1 CHANNEL 32 LSB MSB CHANNEL 1 LSB F 4 TSSYNC CHANNEL 31 TSIG A B CHANNEL 32 C/A D/B A B CHANNEL 1 C/A D/B A TCHCLK TCHBLK 2,3 NOTES: 1) TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored. 2) TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored).
Product Preview DS21Q55 32.2 E1 Mode RECEIVE SIDE TIMING Figure 35-11 FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 RFSYNC RSYNC 1 RSYNC 2 RLCLK RLINK 3 4 NOTES: 1) 2) 3) 4) 5) RSYNC in frame mode (IOCR1.5 = 0). RSYNC in multiframe mode (IOCR1.5 = 1). RLCLK is programmed to output just the Sa bits. RLINK will always output all five Sa bits as well as the rest of the receive data stream. This diagram assumes the CAS MF begins in the RAF frame.
Product Preview DS21Q55 RECEIVE SIDE BOUNDARY TIMING (With Elastic Store Disabled) Figure 35-12 RCLK CHANNEL 32 LSB RSER Si 1 A CHANNEL 1 Sa4 Sa5 Sa6 Sa7 Sa8 MSB CHANNEL 2 RSYNC RFSYNC CHANNEL 32 RSIG A B CHANNEL 1 C D CHANNEL 2 A B Note 4 RCHCLK RCHBLK 1 RLCLK RLINK 2 Sa4 Sa5 Sa6 Sa7 Sa8 NOTES: 1) 2) 3) 4) RCHBLK is programmed to block channel 1. RLCLK is programmed to mark the Sa4 bit in RLINK. Shown is a RNAF frame boundary.
Product Preview DS21Q55 RECEIVE SIDE BOUNDARY TIMING, RSYSCLK = 1.544MHz (With Elastic Store Enabled) Figure 35-13 RSYSCLK CHANNEL 23/31 RSER 1 CHANNEL 24/32 CHANNEL 1/2 LSB LSB MSB F MSB RSYNC2 RMSYNC 3 RSYNC RCHCLK RCHBLK 4 NOTES: 1) Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to one). 2) RSYNC in the output mode (IOCR1.4 = 0).
Product Preview DS21Q55 RECEIVE SIDE BOUNDARY TIMING, RSYSCLK = 2.048MHz (With Elastic Store Enabled) Figure 35-14 RSYSCLK CHANNEL 31 CHANNEL 32 LSB MSB RSER CHANNEL 1 LSB MSB 1 RSYNC RMSYNC RSYNC 2 RSIG A CHANNEL 31 C B D A CHANNEL 32 C B D CHANNEL 1 Note 4 RCHCLK RCHBLK 3 NOTES: 1) 2) 3) 4) RSYNC is in the output mode (IOCR1.4 = 0). RSYNC is in the input mode (IOCR1.4 = 1). RCHBLK is programmed to block channel 1.
Product Preview DS21Q55 RECEIVE IBO CHANNEL INTERLEAVE MODE TIMING Figure 35-15 FRAMER #1, CHANNEL #1 RSYNC 1 RSER F2 C32 F1 C1 F2 C1 F1 C2 F2 C2 RSIG1 F2 C32 F1 C1 F2 C1 F1 C2 F2 C2 RSER2 F3 32 F4 32 F1 C1 F2 C1 F3 C1 F4 C1 F1 C2 F2 C2 F3 C2 F4 C2 RSIG2 F3 C32 F4 C32 F1 C1 F2 C1 F3 C1 F4 C1 F1 C2 F2 C2 F3 C2 F4 C2 RSER3 RSIG3 F5 C32 F5 C32 F6 C32 F7 C32 F6 C32 F8 C32 F7 C32 F8 C32 F1 C1 F1 C1 F2 C1 F2 C1 F3 C1 F3 C1 F4 C1 F4 C1 F5 C1 F5 C1 F6 C1 F6 C1 F7 C
Product Preview DS21Q55 RECEIVE IBO FRAME INTERLEAVE MODE TIMING Figure 35-16 FRAMER #1, CHANNELS 1 through 32 RSYNC 1 RSER F2 F1 F2 F1 F2 RSIG1 F2 F1 F2 F1 F2 RSER2 F3 RSIG2 F4 F3 RSER3 F5 RSIG3 F5 F4 F6 F7 F6 F8 F7 F1 F8 F1 F1 F2 F3 F4 F1 F2 F3 F4 F1 F2 F3 F4 F1 F2 F3 F4 F2 F2 F3 F3 F4 F4 F5 F5 F6 F6 F7 F8 F7 F8 F1 F1 F2 F2 F3 F3 F4 F4 F5 F6 F5 F7 F6 F8 F7 F8 BIT LEVEL DETAIL (4.
Product Preview DS21Q55 G.802 TIMING, E1 MODE ONLY Figure 35-17 TS # 31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK RCLK / RSYSCLK TCLK / TSYSCLK CHANNEL 25 RSER / TSER CHANNEL 26 LSB MSB RCHCLK / TCHCLK RCHBLK / TCHBLK NOTE: 1) RCHBLK or TCHBLK programmed to pulse high during timeslots 1 through 15, 17 through 25, and bit 1 of timeslot 26. 224 of 248 012103 Please contact telecom.support@dalsemi.
Product Preview DS21Q55 TRANSMIT SIDE TIMING Figure 35-18 FRAME# TSYNC 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 1 TSSYNC TSYNC 2 TLCLK 3 3 TLINK NOTES: 1) 2) 3) 4) 5) TSYNC in frame mode (IOCR1.2 = 0). TSYNC in multiframe mode (IOCR1.2 = 1). TLINK is programmed to source just the Sa4 bit. This diagram assumes both the CAS MF and the CRC4 MF begin with the TAF frame. TLINK and TLCLK are not synchronous with TSSYNC.
Product Preview DS21Q55 TRANSMIT SIDE BOUNDARY TIMING (With Elastic Store Disabled) Figure 35-19 TCLK CHANNEL 1 LSB TSER Si 1 A CHANNEL 2 Sa4 Sa5 Sa6 Sa7 Sa8 MSB LSB MSB TSYNC1 TSYNC2 CHANNEL 1 TSIG CHANNEL 2 D A B C D TCHCLK TCHBLK 3 TLCLK TLINK 4 4 DON'T CARE DON'T CARE NOTES: 1) 2) 3) 4) 5) TSYNC is in the output mode (IOCR1.1 = 1.) TSYNC is in the input mode (IOCR1.1 = 0). TCHBLK is programmed to block channel 2. TLINK is programmed to source the Sa4 bit.
Product Preview DS21Q55 TRANSMIT SIDE BOUNDARY TIMING, TSYSCLK = 1.544MHz (With Elastic Store Enabled) Figure 35-20 TSYSCLK CHANNEL 23 1 TSER CHANNEL 24 LSB MSB CHANNEL 1 LSB F MSB TSSYNC TCHCLK TCHBLK 2 NOTES: 1) The F-bit position in the TSER data is ignored. 2) TCHBLK is programmed to block channel 24. 227 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 TRANSMIT SIDE BOUNDARY TIMING, TSYSCLK = 2.048MHz (With Elastic Store Enabled) Figure 35-21 TSYSCLK CHANNEL 31 CHANNEL 32 TSER1 CHANNEL 1 LSB MSB LSB F 4 TSSYNC CHANNEL 31 TSIG A B CHANNEL 32 C D A B CHANNEL 1 C D A TCHCLK TCHBLK 2,3 NOTE: 1) TCHBLK is programmed to block channel 31. 228 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 TRANSMIT IBO CHANNEL INTERLEAVE MODE TIMING Figure 35-22 FRAMER #1, CHANNEL #1 TSSYNC 1 TSER F2 C32 F1 C1 F2 C1 F1 C2 F2 C2 TRSIG 1 F2 C32 F1 C1 F2 C1 F1 C2 F2 C2 TSER2 F3 32 F4 32 F1 C1 F2 C1 F3 C1 F4 C1 F1 C2 F2 C2 F3 C2 F4 C2 TSIG2 F3 C32 F4 C32 F1 C1 F2 C1 F3 C1 F4 C1 F1 C2 F2 C2 F3 C2 F4 C2 TSER3 F5 C32 TSIG3 F5 C32 F6 C32 F7 C32 F6 C32 F8 C32 F7 C32 F8 C32 F1 C1 F1 C1 F2 C1 F2 C1 F3 C1 F3 C1 F4 C1 F4 C1 F5 C1 F5 C1 F6 C1 F6 C1
Product Preview DS21Q55 TRANSMIT IBO FRAME INTERLEAVE MODE TIMING Figure 35-23 FRAMER #1, CHANNELS 1 through 32 TSSYNC 1 TSER F2 F1 F2 F1 F2 TSIG1 F2 F1 F2 F1 F2 TSER2 F3 TSIG2 F4 F3 TSER3 F5 TSIG3 F5 F4 F6 F7 F6 F8 F7 F1 F8 F1 F1 F2 F3 F4 F1 F2 F3 F4 F1 F2 F3 F4 F1 F2 F3 F4 F2 F2 F3 F3 F4 F5 F4 F5 F6 F6 F7 F8 F7 F8 F1 F1 F2 F2 F3 F3 F4 F4 F5 F6 F5 F7 F6 F8 F7 F8 BIT LEVEL DETAIL (4.
Product Preview DS21Q55 33. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground Operating Temperature Range for DS21Q55 Operating Temperature Range for DS21Q55N Storage Temperature Range Soldering Temperature -1.0V to +6.
Product Preview DS21Q55 RECOMMENDED DC OPERATING CONDITIONS (0°C to +70°C for DS21Q55; -40°C to +85°C for DS21Q55N) PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD MIN 2.0 -0.3 3.135 TYP 3.3 MAX 5.5 +0.8 3.465 UNITS V V V CAPACITANCE PARAMETER Input Capacitance Output Capacitance NOTES 1 (TA = +25°C) SYMBOL CIN COUT MIN TYP 5 7 MAX UNITS pF pF NOTES MAX UNITS mA µA µA mA mA NOTES 2 3 4 DC CHARACTERISTICS (0°C to +70°C; V DD = 3.3V ± 5% for DS21Q55; -40°C to +85°C; V DD = 3.
Product Preview DS21Q55 34. AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals, 20pF for all others. 34.1 Multipexed Bus AC Characteristics AC CHARACTERISTICS–MULTIPLEXED PARALLEL PORT (MUX = 1) (0°C to +70°C; V DD = 3.3V ± 5% for DS21Q55; -40°C to +85°C; V DD = 3.
Product Preview DS21Q55 INTEL BUS READ TIMING (BTS = 0 / MUX = 1) Figure 37-1 t CYC ALE PWASH t ASD WR* t ASD t ASED PWEH RD* t CH t CS PWEL CS* t ASL t DHR t DDR AD0-AD7 t AHL INTEL BUS WRITE TIMING (BTS = 0 / MUX = 1) Figure 37-2 t CYC ALE PWASH t ASD RD* t ASED t ASD PWEH WR* PWEL t CH t CS CS* t ASL t DHW AD0-AD7 t AHL t DSW 234 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 MOTOROLA BUS TIMING (BTS = 1 / MUX = 1) Figure 37-3 PWASH AS DS PWEH t ASED t ASD PWEL t CYC t RWS t RWH R/W* AD0-AD7 (read) t DDR t ASL t AHL t DHR t CH t CS CS* AD0-AD7 (write) t ASL t DSW t DHW t AHL 235 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 34.2 Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS–NONMULTIPLEXED PARALLEL PORT (MUX = 0) (0°C to +70°C; V DD = 3.3V ± 5% for DS21Q55; -40°C to +85°C; V DD = 3.
Product Preview DS21Q55 INTEL BUS READ TIMING (BTS = 0 / MUX = 0) Figure 37-4 A0 to A7 Address Valid D0 to D7 Data Valid 5ns min. / 20ns max. t5 WR* t1 0ns min. CS* 0ns min. t2 RD* t3 75ns max. t4 0ns min. INTEL BUS WRITE TIMING (BTS = 0 / MUX = 0) Figure 37-5 A0 to A7 Address Valid D0 to D7 t7 10ns min. RD* t1 t8 10ns min. 0ns min. CS* 0ns min. WR* t2 t6 75ns min. 237 of 248 t4 0ns min. 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.
Product Preview DS21Q55 MOTOROLA BUS READ TIMING (BTS = 1 / MUX = 0) Figure 37-6 A0 to A7 Address Valid D0 to D7 Data Valid 5ns min. / 20ns max. t5 R/W* t1 0ns min. CS* 0ns min. t2 t3 t4 0ns min. 75ns max. DS* MOTOROLA BUS WRITE TIMING (BTS = 1 / MUX = 0) Figure 37-7 A0 to A7 Address Valid D0 to D7 10ns min. R/W* t1 t7 t8 10ns min. 0ns min. CS* 0ns min. DS* t2 t6 t4 0ns min. 75ns min. 238 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.
Product Preview DS21Q55 34.3 Receive Side AC Characteristics AC CHARACTERISTICS–RECEIVE SIDE (0°C to +70°C; V DD = 3.3V ± 5% for DS21Q55; -40°C to +85°C; V DD = 3.
Product Preview DS21Q55 NOTES: 1) 2) 3) 4) 5) 6) 7) Jitter attenuator enabled in the receive path. Jitter attenuator disabled or enabled in the transmit path. RSYSCLK = 1.544MHz. RSYSCLK = 2.048MHz. RSYSCLK = 4.096MHz. RSYSCLK = 8.192MHz. RSYSCLK = 16.384MHz. RECEIVE SIDE TIMING (T1 MODE) Figure 37-8 RCLK tD1 F Bit RSER / RDATA / RSIG t D2 RCHCLK t D2 RCHBLK t D2 RFSYNC / RMSYNC t D2 RSYN 1 C RLCLK t 2 D2 tD1 RLINK NOTES: 1) RSYNC is in the output mode.
Product Preview DS21Q55 RECEIVE SIDE TIMING, ELASTIC STORE ENABLED (T1 MODE) Figure 37-9 t SL tF tR RSYSCLK t SH t SP t D3 SEE NOTE 3 RSER / RSIG t D4 RCHCLK t D4 RCHBLK t D4 RMSYNC t RSYNC RSYNC 1 D4 t HD 2 t SU NOTES: 1) RSYNC is in the output mode. 2) RSYNC is in the input mode. 3) F-bit when CCR1.3 = 0, MSB of TS0 when CCR1.3 = 1. 241 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 RECEIVE LINE INTERFACE TIMING Figure 37-10 t LL t LH RCLKO t LP t DD RPOSO, RNEGO tR t CL tF t CH RCLKI t CP t SU RPOSI, RNEGI t HD 242 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 34.4 Transmit AC Characteristics AC CHARACTERISTICS–TRANSMIT SIDE (0°C to +70°C; V DD = 3.3V ± 5% for DS21Q55; -40°C to +85°C; V DD = 3.
Product Preview DS21Q55 4) TSYSCLK = 8.192MHz. 5) TSYSCLK = 16.384MHz TRANSMIT SIDE TIMING Figure 37-11 t CP t CL tF tR t CH TCLK t D1 TESO t SU TSER / TSIG / TDATA t HD t D2 TCHCLK t D2 TCHBLK t D2 1 TSYNC t SU t HD 2 TSYNC t 5 TLCLK D2 t HD TLINK t SU NOTES: 1) TSYNC is in the output mode (TCR2.2 = 1). 2) TSYNC is in the input mode (TCR2.2 = 0). 3) TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.
Product Preview DS21Q55 TRANSMIT SIDE TIMING, ELASTIC STORE ENABLED Figure 37-12 t SP t SL tF tR t SH TSYSCLK t SU TSER t D3 t HD TCHCLK t D3 TCHBLK t SU t HD TSSYNC NOTES: 1) TSER is only sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. 2) TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit-side elastic store is enabled. 245 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 TRANSMIT LINE INTERFACE TIMING Figure 37-13 TCLKO TPOSO, TNEGO t DD tR t LP t LL tF t LH TCLKI t SU TPOSI, TNEGI t HD 246 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 35. MECHANICAL DESCRIPTIONS 247 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.
Product Preview DS21Q55 248 of 248 012103 Please contact telecom.support@dalsemi.com or search http://www.maxim-ic.com for updated information.