Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsDS1878T+

General Description

The DS1878 controls and monitors all functions for SFF,

SFP, and SFP+ modules including all SFF-8472 func-

tionality. The combination of the DS1878 with Maxim

laser driver/limiting amplifier solutions supports VCSEL,

DFB, and EML-based solutions. The device provides

APC loop, modulation current control, and eye safety

functionality. It continuously monitors for high output

current, high bias current, and low and high transmit

power to ensure that laser shutdown for eye safety

requirements are met without adding external compo-

nents. Six ADC channels monitor V

, temperature,

and four external monitor inputs (MON1–MON4) that

can be used to meet all monitoring requirements.

MON3 is differential with support for common mode to

. Two digital-to-analog (DAC) outputs with tempera-

ture-indexed lookup tables (LUTs) are available for

additional control functionality.

Applications

SFF, SFP, and SFP+ Transceiver Modules

Features

♦ Meets All SFF-8472 Control and Monitoring

Requirements

♦ Laser Bias Controlled by APC Loop and

Temperature LUT to Compensate for Tracking

Error

♦ Laser Modulation Controlled by Temperature LUT

♦ Six Analog Monitor Channels: Temperature, V

MON1–MON4

MON1–MON4 Support Internal and External

Calibration

Scalable Dynamic Range

Internal Direct-to-Digital Temperature Sensor

Alarm and Warning Flags for All Monitored

Channels

♦ Two 9-Bit Delta-Sigma Outputs with 36 Entry

Temperature LUTs

♦ Digital I/O Pins: Five Inputs, Four Outputs

♦ Comprehensive Fault-Measurement System with

Maskable Laser Shutdown Capability

♦ Flexible, Two-Level Password Scheme Provides

Three Levels of Security

♦ 256 Additional Bytes Located at A0h Slave

Address

♦ I

C-Compatible Interface

♦ 3-Wire Master to Communicate with a Maxim

Laser Driver/Limiting Amplifier

♦ +2.85V to +5.5V Operating Voltage Range

♦ -40°C to +95°C Operating Temperature Range

♦ 28-Pin TQFN (5mm x 5mm x 0.75mm) Package

DS1878

________________________________________________________________

Maxim Integrated Products

Ordering Information

19-5537; Rev 1; 8/11

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

DS1878T+ -40°C to +95°C 28 TQFN-EP*

DS1878T+T&R -40°C to +95°C 28 TQFN-EP*

SFP+ Controller with Digital LDD Interface

Summary of content (101 pages)

PAGE 1
9-5537; Rev 1; 8/11 SFP+ Controller with Digital LDD Interface The DS1878 controls and monitors all functions for SFF, SFP, and SFP+ modules including all SFF-8472 functionality. The combination of the DS1878 with Maxim laser driver/limiting amplifier solutions supports VCSEL, DFB, and EML-based solutions. The device provides APC loop, modulation current control, and eye safety functionality.
PAGE 2
DS1878 SFP+ Controller with Digital LDD Interface TABLE OF CONTENTS Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SFP+ Controller with Digital LDD Interface Transmit Fault (TXFOUT) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Die Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3-Wire Master for Controlling the Maxim Laser Driver and Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
DS1878 SFP+ Controller with Digital LDD Interface LIST OF FIGURES Figure 1. Modulation LUT Loading to a Maxim Laser Driver MOD DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 2. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Figure 3. TXD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
SFP+ Controller with Digital LDD Interface Continuous Power Dissipation (TA = +70°C) 28 Pin TQFN (derate 34.5mW/°C above +70°C) .....2758.6mW Operating Temperature Range ...........................-40°C to +95°C Programming Temperature Range .........................0°C to +95°C Storage Temperature Range .............................-55°C to +125°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................
PAGE 6
DS1878 SFP+ Controller with Digital LDD Interface DAC1, DAC2 ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER Main Oscillator Frequency Delta-Sigma Input-Clock Frequency Reference Voltage Input (REFIN) SYMBOL CONDITIONS TYP MAX UNITS f OSC 5 MHz fDS 1.25 MHz VREFIN Minimum 0.
PAGE 7
SFP+ Controller with Digital LDD Interface DS1878 DIGITAL THERMOMETER CHARACTERISTICS (VCC = +2.85V to +5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER Thermometer Error SYMBOL TERR CONDITIONS -40°C to +95°C MIN TYP -3 MAX UNITS +3 °C AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +5.5V, TA = -40°C to +95°C, unless otherwise noted.
PAGE 8
DS1878 SFP+ Controller with Digital LDD Interface I2C AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +5.5V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.
PAGE 9
SFP+ Controller with Digital LDD Interface SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE 2.3 +25°C -40°C 1.9 VCC = 3.3V 2.4 2.3 VCC = 2.85V 2.2 2.1 1.7 SDA = SCL = VCC SDA = SCL = VCC 1.5 2.0 2.85 3.10 3.35 3.60 3.85 -40 -20 0 VCC (V) DS1878 toc03 1.0 60 80 0.4 0.2 0 -0.2 -0.4 VCC = 3.3V 0.8 0.6 MON1–MON4 DNL (LSB) MON1–MON4 INL (LSB) 0.6 USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V -0.6 40 MON1–MON4 DNL VCC = 3.3V 0.
PAGE 10
SFP+ Controller with Digital LDD Interface DAC2 DAC1 REFIN GND MON2 VCC TOP VIEW GND DS1878 Pin Configuration 21 20 19 18 17 16 15 CSEL2OUT 22 14 MON1 VCC 23 13 MON3N CSEL1OUT 24 12 MON3P 11 MON4 10 TXDOUT 9 RSEL 8 GND SCLOUT 25 DS1878 SDAOUT 26 4 5 LOS SCL 3 SDA 2 TXFOUT 1 RSELOUT TXF 28 6 7 IN1 EP + TXD LOSOUT 27 THIN QFN (5mm × 5mm × 0.
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SFP+ Controller with Digital LDD Interface VCC REFIN MAIN MEMORY EEPROM/SRAM VCC I2C INTERFACE SDA SCL EEPROM 256 BYTES AT A0h ADC CONFIGURATION/RESULTS, SYSTEM STATUS/CONTROL BITS, ALARMS/WARNINGS, LOOKUP TABLES, USER MEMORY 9-BIT DELTA-SIGMA DAC1 9-BIT DELTA-SIGMA DAC2 SDAOUT VCC 3-WIRE INTERFACE MON1 VCC SCLOUT CSEL1OUT CSEL2OUT MON2 ANALOG MUX 13-BIT ADC MON3P APC INTEGRATOR 8-BIT QTs TXFOUT POWER-ON ANALOG INTERRUPT MON3N MON4 TEMPERATURE SENSOR VCC TXD CONFIGURABLE LOGIC TXDOUT
PAGE 12
SFP+ Controller with Digital LDD Interface DS1878 Typical Operating Circuit +3.3V 680Ω PIN-ROSA MAX3945 LA LOS 3W CS2 MAX3946 3W CS1 MODE DAC FAULT DISABLE BIAS DAC DFB TOSA LDD BMON 3W DS1878 EEPROM MON1 MON2 MON3 RBD QUICK TRIP I2C LOS The DS1878 integrates the control and monitoring functionality required to implement a VCSEL-based or DFBbased SFP or SFP+ system using Maxim’s limiting amplifiers and laser drivers.
PAGE 13
SFP+ Controller with Digital LDD Interface ACRONYM ADC AGC APC APD ATB BM DAC DFB LDD LOS LUT NV QT TE TIA ROSA SEE SFF A Maxim laser driver controls its laser bias current DAC using the APC loop within the device. The APC loop’s feedback to the device is the monitor diode (MON2) current, which is converted to a voltage using an external resistor. The feedback is sampled by a comparator and compared to a digital set-point value. The output of the comparator has three states: up, down, or no-operation.
PAGE 14
DS1878 SFP+ Controller with Digital LDD Interface (MODTC, Table 02h, Register C6h) and a temperature index register (MODTI, Table 02h, Register C2h). The TXP HI, TXP LO, and BIAS MAX QT alarms are masked until the binary search is completed. However, the BIAS MAX alarm is monitored during this time to prevent the BIAS register from exceeding IBIASMAX. During the bias current initialization, the BIAS register is not allowed to exceed IBIASMAX.
PAGE 15
SFP+ Controller with Digital LDD Interface BIAS and MODULATION Registers as a Function of Transmit Disable (TXD) If TXD is asserted (logic 1) during normal operation, the 3-wire master writes the laser driver bias and MODULATION DACs to 0. When TXD is deasserted (logic 0), the device sets the MODULATION register with the value associated with the present temperature, and initializes the BIAS register using the same search algorithm as done at startup.
PAGE 16
DS1878 SFP+ Controller with Digital LDD Interface An APC sample that requires an update of the BIAS register causes subsequent APC samples to be ignored until the end of the 3-wire communication that updates the laser driver’s BIAS DAC, plus an additional 16 sample periods (tREP). Monitors and Fault Detection Monitors Monitoring functions on the device include five quick-trip comparators and six ADC channels.
PAGE 17
SFP+ Controller with Digital LDD Interface DS1878 ONE ROUND-ROBIN ADC CYCLE TEMP VCC MON1 MON2 MON3 MON4 TEMP tRR NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC IS ABOVE THE VCC ALARM LOW THRESHOLD. Figure 5. ADC Round-Robin Timing VCC VCC VCC VCC 1kΩ BMD MON2 ADC MON2 ADC BMD 1kΩ Figure 6.
PAGE 18
DS1878 SFP+ Controller with Digital LDD Interface Enhanced RSSI Monitoring (Dual-Range Functionality) The device offers a feature to improve the accuracy and range of MON3, which is most commonly used for monitoring RSSI. Using a traditional input, the accuracy of the RSSI measurements is increased at the cost of Table 4.
PAGE 19
SFP+ Controller with Digital LDD Interface DS1878 L-SC ALE RES PON SE RSSI RESULT SE FUL AR FINE FT SHI LUL F =3 ER FIN ALE SC CO TIGH SE ON P RES HYSTERESIS MON3 INPUT FINE COARSE Figure 9. RSSI with Crossover Disabled SEE RECALL SEE RECALL VPOA VCC VPOD SEE PRECHARGED TO 0 RECALLED VALUE PRECHARGED TO 0 RECALLED VALUE PRECHARGED TO 0 Figure 10. Low-Voltage Hysteresis Example Low-Voltage Operation The device contains two power-on reset (POR) levels.
PAGE 20
DS1878 SFP+ Controller with Digital LDD Interface is timed (within 500µs) to go to 0, at which point the part is fully functional. For all device addresses sourced from EEPROM (Table 02h, Register 8Ch), the default device address is A2h until VCC exceeds POA, allowing the device address to be recalled from the EEPROM.
PAGE 21
SFP+ Controller with Digital LDD Interface DAC[1/2]TI 8 8 DAC[1/2]TC = 1 7 6 5 LUT LOADED TO [8:1] (DAC BIT 0 = 0) 4 LUT LOADED TO [7:0] 3 2 1 DELTA-SIGMA DACA OR DACB DAC[1/2]TC = 0 DELTA-SIGMA DACA OR DACB DS1878 DAC[1/2]TI 7 6 5 LUT LOADED TO [8:1] (DAC BIT 0 = 0) 4 LUT LOADED TO [7:0] 3 2 1 0 0 -40 +102 TEMPERATURE (°C) -40 +102 TEMPERATURE (°C) Figure 13.
PAGE 22
DS1878 SFP+ Controller with Digital LDD Interface IN1, RSEL, RSELOUT The digital input IN1 and RSEL pins primarily serve to meet the rate-select requirements of SFP and SFP+. They also serve as general-purpose inputs. RSELOUT is driven by a combination of the RSEL and logic dictated by control registers in the EEPROM (Figure 16). The levels of IN1 and RSEL can be read using the STATUS register (Lower Memory, Register 6Eh).
PAGE 23
SFP+ Controller with Digital LDD Interface DS1878 VCC SET BIAS REGISTER AND MODULATION REGISTER TO 0 TXDS RPU TXD C TXDC R Q TXDFG C TXDOUT FETG Q D TXD TXDIO S TXDFLT TXP HI FLAG TXP HI ENABLE TXFOUTS BIAS MAX TXFOUT BIAS MAX ENABLE HBAL FLAG TXFINT HBAL ENABLE TXP LO FLAG INVTXF TXP LO ENABLE TXF tINITR1 TXFS FAULT RESET TIMER (130ms) OUT IN POWER-ON RESET IN PINS OUT Figure 15.
PAGE 24
DS1878 SFP+ Controller with Digital LDD Interface DETECTION OF TXF FAULT TXFOUT Figure 17a. TXFOUT Nonlatched Operation DETECTION OF TXF FAULT tINITR1/2 TXD OR TXF RESET TXFOUT (ONLY ALARM FAULTS PRESENT) TXFOUT (QT ALARMS PRESENT) Figure 17b. TXFOUT Latched Operation and TXD_TXFEN = 1 By default, TXD does not impact TXFOUT (TXD_TXFEN = 0). This is shown in the Figure 17c. When TXD_TXFEN = 1, TXD affects TXFOUT. The particular behavior is described in Figure 17a and 17b.
PAGE 25
SFP+ Controller with Digital LDD Interface DS1878 VCC VCC LO (ASSUMES VCC LO > VPOA) < 13ms TXD OR SOFT TXD TXFOUT (1) TXFOUT (2) VCC LO ALARM CONDITION 1: VCCTXF = 0, ANY STATE OF VCC LO ALARM OR WARNING FLAG. CONDITION 2: VCCTXF = 1, ANY STATE OF VCC LO ALARM OR WARNING FLAG. VCC VCC LO (ASSUMES VCC LO > VPOA) < 13ms TXD OR SOFT TXD TXFOUT (1) TXFOUT (2) VCC LO ALARM CONDITION 1: VCCTXF = 0, ANY STATE OF VCC LO ALARM OR WARNING FLAG.
PAGE 26
DS1878 SFP+ Controller with Digital LDD Interface VCC-LO VPOA < tRR VCC 13ms TXD OR SOFT TXD* TXFOUT (1) TXFOUT (2) CONDITION 1: VCCTXF = 0, VCC LO ALARM OR WARNING FLAG ENABLED TO CREATE TXFOUT. CONDITION 2: VCCTXF = 1 and (VCC LO ALARM OR WARNING FLAG IS ENABLED). *DON'T CARE ABOUT TXD STATE. Figure 17d. TXFOUT When TXD_TXFEN = 0 on Slow Power-On Die Identification Protocol The DS1878 has an ID hardcoded in its die. Two registers (Table 02h, Registers CEh–CFh) are assigned for this feature.
PAGE 27
SFP+ Controller with Digital LDD Interface DS1878 WRITE MODE CSEL_OUT tL tT tCH tCL 0 SCLOUT 1 2 3 4 5 6 7 8 9 A4 A3 A2 A1 A0 RWN D7 D6 10 11 12 13 14 15 tDS SDAOUT A6 A5 D5 D4 D3 D2 D1 D0 tDH READ MODE CSEL_OUT tL tT tCH tCL SCLOUT 0 1 2 3 4 5 6 7 A4 A3 A2 A1 A0 RWN 8 9 10 tRS tDS SDAOUT A6 A5 D7 D6 11 D5 12 D4 13 D3 14 D2 15 D1 D0 tDH NOTE: SEE THE 3-WIRE DIGITAL INTERFACE SPECIFICATION TABLE FOR DETAILS.
PAGE 28
DS1878 SFP+ Controller with Digital LDD Interface The control registers are first written once VCC exceeds POA. They are also written after every temperature conversion and on a rising edge of TXD. Any time one of these events occurs, the device reads and updates TXSTAT1 and TXSTAT2, and writes SET_IBIAS and SET_IMOD to 0.
PAGE 29
SFP+ Controller with Digital LDD Interface DS1878 3-WIRE STATE MACHINE POR OR TXD DIS3W = 1? OR BIAS_MANUAL = 1? READ TXPOR YES TXPOR = = 1? MANMODE = = 1? YES READ/WRITE MANMODE YES INCREMENT MODULATION WAIT FOR BIAS TXD_FLAG = = 1? OR MOD_FLAG = 1? OR DIS3W = 1? CONTROL/STATUS INITIALIZATION BIASINC = = 1? YES MODINC = = 1? TXD_STANDBY (SET TXD_FLAG) TXD_ext = = 0? YES YES YES READ TXPOR TXD = = 0? INCREMENT BIAS YES BIASINC = = 1? YES TXPOR = = 1? APC_BINARY = = 0? TEMP_CONV = = 1?
PAGE 30
DS1878 SFP+ Controller with Digital LDD Interface I2C Communication I2C Definitions The following terminology is commonly used to describe I2C data transfers. Master device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave devices: Slave devices send and receive data at the master’s request. Bus idle or not busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states.
PAGE 31
SFP+ Controller with Digital LDD Interface Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgement is read using the bit-read definition.
PAGE 32
DS1878 SFP+ Controller with Digital LDD Interface TYPICAL I2C WRITE TRANSACTION MSB START 1 MSB LSB 0 1 0 0 0 SLAVE ADDRESS* 1 R/W SLAVE ACK b7 LSB b6 READ/ WRITE b5 b4 b3 b2 b1 b0 MSB SLAVE ACK b7 LSB b6 b5 b4 REGISTER ADDRESS b3 b2 b1 b0 SLAVE ACK STOP DATA *IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h FOR THE MAIN MEMORY. IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Ch FOR THE MAIN MEMORY.
PAGE 33
SFP+ Controller with Digital LDD Interface Many NV memory locations (listed within the Register Descriptions section) are actually shadowed EEPROM that are controlled by the SEEB bit in Table 02h, Register 80h. The device incorporates shadowed-EEPROM memory locations for key memory addresses that can be written many times. By default the shadowed-EEPROM bit, SEEB, is not set and these locations act as ordinary EEPROM.
PAGE 34
DS1878 SFP+ Controller with Digital LDD Interface Register Descriptions The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is one/two memory locations beyond the previous byte/word’s address. A total of 8 bytes are present on each row. For more information about each of these bytes see the corresponding register description.
PAGE 35
SFP+ Controller with Digital LDD Interface TABLE 01h WORD 0 WORD 1 WORD 2 WORD 3 ROW (HEX) ROW NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F 80–BF <7>EEPROM EE EE EE EE EE EE EE EE C0–F7 <8>EEPROM EE EE EE EE EE EE EE EE <8>ALARM ALARM EN3 ALARM EN2 ALARM EN1 ALARM EN0 WARN EN3 WARN EN2 RESERVED RESERVED F8 ENABLE The ALARM ENABLE bytes (Registers F8h–FFh) can be configured to exist in Table 05h instead of here at Table 01h with the
PAGE 36
DS1878 SFP+ Controller with Digital LDD Interface Table 02h Register Map TABLE 02h (PW2) ROW (HEX) ROW NAME WORD 0 BYTE 0/8 WORD 1 BYTE 1/9 BYTE 2/A WORD 2 BYTE 3/B BYTE 4/C <4>MODULATION WORD 3 BYTE 5/D BYTE 6/E 80 <0>CONFIG0 <8>MODE <4>TINDEX 88 <8>CONFIG1 SAMPLE RATE CNFGA 90 <8>SCALE0 XOVER COARSE VCC SCALE MON1 SCALE MON2 SCALE 98 <8>SCALE1 MON3 FINE SCALE MON4 SCALE MON3 COARSE SCALE RESERVED A0 <8>OFFSET0 XOVER FINE VCC OFFSET MON1 OFFSET MON2 OFFSET A8 <8>OFF
PAGE 37
SFP+ Controller with Digital LDD Interface TABLE 04h (MODULATION LUT) WORD 0 WORD 1 WORD 2 WORD 3 ROW (HEX) ROW NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F 80–C7 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD Table 05h Register Map TABLE 05h ROW (HEX) 80–F7 F8 WORD 0 ROW NAME BYTE 0/8 WORD 1 BYTE 1/9 BYTE 2/A WORD 2 WORD 3 BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY <8>ALARM ALARM
PAGE 38
DS1878 SFP+ Controller with Digital LDD Interface Table 07h Register Map TABLE 07h (DAC1 LUT) WORD 0 WORD 1 WORD 2 WORD 3 ROW (HEX) ROW NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E 80–9F <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 A0 <8>LUT7 DAC1 DAC1 DAC1 DAC1 RESERVED RESERVED RESERVED RESERVED BYTE 7/F Table 08h Register Map TABLE 08h (DAC2 LUT) WORD 0 WORD 1 WORD 2 WORD 3 ROW (HEX) ROW NAME 80–9F <8>LUT8 DAC2 DAC2 DAC2 DAC2 DAC2
PAGE 39
SFP+ Controller with Digital LDD Interface Lower Memory, Register 00h–01h: TEMP ALARM HI Lower Memory, Register 04h–05h: TEMP WARN HI FACTORY DEFAULT 7FFFh READ ACCESS All WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE) 00h, 04h S 26 25 24 23 22 21 20 01h, 05h 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 BIT 7 BIT 0 Temperature measurement updates above this two’s complement threshold set corresponding alarm or warning bits.
PAGE 40
DS1878 SFP+ Controller with Digital LDD Interface Lower Memory, Register 08h–09h: VCC ALARM HI Lower Memory, Register 0Ch–0Dh: VCC WARN HI Lower Memory, Register 10h–11h: MON1 ALARM HI Lower Memory, Register 14h–15h: MON1 WARN HI Lower Memory, Register 18h–19h: MON2 ALARM HI Lower Memory, Register 1Ch–1Dh: MON2 WARN HI Lower Memory, Register 20h–21h: MON3 ALARM HI Lower Memory, Register 24h–25h: MON3 WARN HI Lower Memory, Register 28h–29h: MON4 ALARM HI Lower Memory, Register 2Ch–2Dh: MON4 WARN HI 08h, 0C
PAGE 41
SFP+ Controller with Digital LDD Interface 0Ah, 0Eh, 12h, 16h, 1Ah, 1Eh, 22h, 26h, 2Ah, 2Eh 0Bh, 0Fh, 13h, 17h, 1Bh, 1Fh, 23h, 27h, 2Bh, 2Fh FACTORY DEFAULT 0000h READ ACCESS All WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE) DS1878 Lower Memory, Register 0Ah–0Bh: VCC ALARM LO Lower Memory, Register 0Eh–0Fh: VCC WARN LO Lower Memory, Register 12h–13h: MON1 ALARM LO Lower Memory, Register 16h–17h: MON1 WARN LO Lower Memory, Register 1Ah–1Bh: MON2 ALARM LO Lower Memory, Register 1Eh–1Fh: MON2 WARN
PAGE 42
DS1878 SFP+ Controller with Digital LDD Interface Lower Memory, Register 30h–5Fh: EE 30h–5Fh FACTORY DEFAULT 00h READ ACCESS All WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (EE) EE EE EE EE EE EE EE BIT 7 EE BIT 0 PW2 level access-controlled EEPROM.
PAGE 43
SFP+ Controller with Digital LDD Interface DS1878 Lower Memory, Register 62h–63h: VCC VALUE Lower Memory, Register 64h–65h: MON1 VALUE Lower Memory, Register 66h–67h: MON2 VALUE Lower Memory, Register 68h–69h: MON3 VALUE Lower Memory, Register 6Ah–6Bh: MON4 VALUE 62h, 64h, 66h, 68h, 6Ah 63h, 65h, 67h, 69h, 6Bh POWER-ON VALUE 0000h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile 215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20 BIT 7 BIT 0 Left-justified unsigned voltag
PAGE 44
DS1878 SFP+ Controller with Digital LDD Interface Lower Memory, Register 6Eh: STATUS POWER-ON VALUE Write Access 6Eh X0XX 0XXXb READ ACCESS All WRITE ACCESS See below MEMORY TYPE Volatile N/A All N/A All All N/A N/A N/A TXDS TXDC IN1S RSELS RSELC TXFOUTS RXL RDYB BIT 7 44 BIT 0 BIT 7 TXDS: TXD Status Bit. Reflects the logic state of the TXD pin (read only). 0 = TXD pin is logic-low. 1 = TXD pin is logic-high. BIT 6 TXDC: TXD Software Control Bit.
PAGE 45
SFP+ Controller with Digital LDD Interface 6Fh POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS All and device hardware MEMORY TYPE Volatile TEMP RDY VCC RDY MON1 RDY MON2 RDY DS1878 Lower Memory, Register 6Fh: UPDATE MON3 RDY MON4 RDY BIT 7 BITS 7:2 RESERVED RSSIR BIT 0 Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is completed. These bits can be cleared so that a completion of a new conversion is verified.
PAGE 46
DS1878 SFP+ Controller with Digital LDD Interface Lower Memory, Register 70h: ALARM3 70h POWER-ON VALUE 10h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI BIT 7 46 MON2 LO BIT 0 BIT 7 TEMP HI: High-alarm status for temperature measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 6 TEMP LO: Low-alarm status for temperature measurement.
PAGE 47
SFP+ Controller with Digital LDD Interface 71h POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile MON3 HI MON3 LO MON4 HI DS1878 Lower Memory, Register 71h: ALARM2 MON4 LO RESERVED TXFS FETG BIT 7 TXFINT BIT 0 BIT 7 MON3 HI: High-alarm status for MON3 measurement. A TXD event does not clear this alarm. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting.
PAGE 48
DS1878 SFP+ Controller with Digital LDD Interface Lower Memory, Register 72h: ALARM1 72h POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI BIT 7 BITS 7:4 48 TXP LO BIT 0 RESERVED BIT 3 HBAL: High-Bias Alarm Status; Fast Comparison. A TXD event clears this alarm. 0 = (Default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting.
PAGE 49
SFP+ Controller with Digital LDD Interface DS1878 Lower Memory, Register 73h: ALARM0 73h POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile LOS HI LOS LO RESERVED RESERVED BIAS MAX RESERVED RESERVED BIT 7 RESERVED BIT 0 BIT 7 LOS HI: High-Alarm Status for MON3; Fast Comparison. A TXD event does not clear this alarm. 0 = (Default) At POR, this is the state if the last comparison was below the HLOS threshold setting.
PAGE 50
DS1878 SFP+ Controller with Digital LDD Interface Lower Memory, Register 74h: WARN3 74h POWER-ON VALUE 10h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI BIT 7 50 MON2 LO BIT 0 BIT 7 TEMP HI: High-warning status for temperature measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 6 TEMP LO: Low-warning status for temperature measurement.
PAGE 51
SFP+ Controller with Digital LDD Interface 75h POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile MON3 HI MON3 LO MON4 HI DS1878 Lower Memory, Register 75h: WARN2 MON4 LO RESERVED RESERVED BIT 7 RESERVED RESERVED BIT 0 BIT 7 MON3 HI: High-warning status for MON3 measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 6 MON3 LO: Low-warning status for MON3 measurement.
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DS1878 SFP+ Controller with Digital LDD Interface Lower Memory, Register 7Bh–7Eh: PASSWORD ENTRY (PWE) POWER-ON VALUE FFFF FFFFh READ ACCESS N/A WRITE ACCESS All MEMORY TYPE Volatile 7Bh 231 230 229 228 227 226 225 224 7Ch 223 222 221 220 219 218 217 216 7Dh 215 214 213 212 211 210 29 28 7Eh 27 26 25 24 23 22 21 20 BIT 7 BIT 0 There are two passwords for the device. Each password is 4 bytes long.
PAGE 53
SFP+ Controller with Digital LDD Interface Table 01h, Register 80h–BFh: EEPROM 80h–BFh POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A) WRITE ACCESS PW2 or (PW1 and RWTBL1A) MEMORY TYPE Nonvolatile (EE) EE EE EE EE EE EE EE BIT 7 EE BIT 0 EEPROM for PW1 and/or PW2 level access.
PAGE 54
DS1878 SFP+ Controller with Digital LDD Interface Table 01h, Register F8h: ALARM EN3 F8h POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI BIT 7 MON2 LO BIT 0 Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory, Register 71h) logic.
PAGE 55
SFP+ Controller with Digital LDD Interface F9h POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) MON3 HI MON3 LO MON4 HI MON4 LO BIT 7 RESERVED RESERVED DS1878 Table 01h, Register F9h: ALARM EN2 RESERVED RESERVED BIT 0 Layout is identical to ALARM2 in Lower Memory, Register 71h. Enables alarms to create TXFINT (Lower Memory, Register 71h) logic.
PAGE 56
DS1878 SFP+ Controller with Digital LDD Interface Table 01h, Register FAh: ALARM EN1 FAh POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI BIT 7 TXP LO BIT 0 Layout is identical to ALARM1 in Lower Memory, Register 72h. Enables alarms to create internal signal FETG (see Figure 15) logic.
PAGE 57
SFP+ Controller with Digital LDD Interface FBh POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) LOS HI LOS LO RESERVED RESERVED BIAS MAX RESERVED DS1878 Table 01h, Register FBh: ALARM EN0 RESERVED BIT 7 RESERVED BIT 0 Layout is identical to ALARM0 in Lower Memory, Register 73h. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h or 05h.
PAGE 58
DS1878 SFP+ Controller with Digital LDD Interface Table 01h, Register FCh: WARN EN3 F8h POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI BIT 7 MON2 LO BIT 0 Layout is identical to WARN3 in Lower Memory, Register 74h. Enables warnings to create TXFINT (Lower Memory, Register 71h) logic.
PAGE 59
SFP+ Controller with Digital LDD Interface F9h POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) MON3 HI MON3 LO MON4 HI MON4 LO RESERVED BIT 7 RESERVED DS1878 Table 01h, Register FDh: WARN EN2 RESERVED RESERVED BIT 0 Layout is identical to WARN2 in Lower Memory, Register 75h. Enables warnings to create TXFINT (Lower Memory, Register 71h) logic.
PAGE 60
DS1878 SFP+ Controller with Digital LDD Interface Table 02h Register Descriptions Table 02h, Register 80h: MODE 80h POWER-ON VALUE 3Fh READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RTBL246) MEMORY TYPE Volatile SEEB RESERVED DAC1 EN DAC2 EN AEN MOD EN APC EN BIT 7 60 BIAS EN BIT 0 BIT 7 SEEB: 0 = (Default) Enables EEPROM writes to SEE bytes.
PAGE 61
SFP+ Controller with Digital LDD Interface 81h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS (PW2 and AEN = 0) or (PW1 and RWTBL246 and AEN = 0) MEMORY TYPE Volatile 27 26 25 24 23 22 DS1878 Table 02h, Register 81h: TEMPERATURE INDEX (TINDEX) 21 BIT 7 20 BIT 0 Holds the calculated index based on the temperature measurement. This index is used for the address during lookup of Tables 04h, 06h–08h.
PAGE 62
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register 84h–85h: DAC1 VALUE FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS (PW2 and DAC1 EN = 0) or (PW1 and RWTBL246 and DAC1 EN = 0) MEMORY TYPE Volatile 84h 0 0 0 0 0 0 0 28 85h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The digital value used for DAC1 and recalled from Table 07h at the adjusted memory address found in TINDEX.
PAGE 63
SFP+ Controller with Digital LDD Interface 88h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) SEE SEE SEE SEE SEE APC_SR2 BIT 7 BITS 7:3 DS1878 Table 02h, Register 88h: SAMPLE RATE APC_SR1 APC_SR0 BIT 0 SEE APC_SR[2:0]: 3-bit sample rate for comparison of APC control. Defines the sample rate for comparison of APC control.
PAGE 64
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register 89h: CNFGA 89h FACTORY DEFAULT 80h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) LOSC VCCTXF INV LOS ASEL MASK INVRSOUT RSELPIN BIT 7 BIT 7 BIT 6 BIT 5 64 INVTXF BIT 0 LOSC: LOS Configuration. Defines the source for the LOSOUT pin (see Figure 16). 0 = LOS LO alarm is used as the source.
PAGE 65
SFP+ Controller with Digital LDD Interface 8Ah FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RESERVED RESERVED TXF_TXDEN RESERVED RESERVED ALATCH DS1878 Table 02h, Register 8Ah: CNFGB QTLATCH BIT 7 BITS 7:6 BIT 5 BITS 4:3 WLATCH BIT 0 RESERVED TXF_TXDEN: 0 = TXFOUT does not go high when TXD goes high. 1 = TXFOUT goes high when TXD goes high.
PAGE 66
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register 8Bh: CNFGC 8Bh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) XOVEREN INVMON2 TXDM34 TXDFG TXDFLT TXDIO RSSI_FC BIT 7 BIT 0 BIT 7 XOVEREN: Enables RSSI conversion to use the XOVER (Table 02h, Register 90h–91h) value during MON3 conversions. 0 = Uses hysteresis for linear RSSI measurements.
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SFP+ Controller with Digital LDD Interface DS1878 Table 02h, Register 8Ch: DEVICE ADDRESS 8Ch FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 This value becomes the I2C slave address for the main memory when the ASEL (Table 02h, Register 89h) bit is set. If A0h is programmed to this register, the auxiliary memory is disabled.
PAGE 68
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register 8Fh: RIGHT-SHIFT0 (RSHIFT0) 8Fh FACTORY DEFAULT 30h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RESERVED MON3C2 MON3C1 MON3C0 RESERVED MON3F2 MON3F1 BIT 7 MON3F0 BIT 0 Allows for right-shifting the final answer of MON3 coarse (MON3C) and MON3 fine (MON3F) voltage measurements.
PAGE 69
SFP+ Controller with Digital LDD Interface DS1878 Table 02h, Register 92h–93h: VCC SCALE Table 02h, Register 94h–95h: MON1 SCALE Table 02h, Register 96h–97h: MON2 SCALE Table 02h, Register 98h–99h: MON3 FINE SCALE Table 02h, Register 9Ah–9Bh: MON4 SCALE Table 02h, Register 9Ch–9Dh: MON3 COARSE SCALE FACTORY CALIBRATED 92h, 94h, 96h, 98h, 9Ah, 9Ch 93h, 95h, 97h, 99h, 9Bh, 9Dh READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE
PAGE 70
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register A0h–A1h: XOVER FINE FACTORY DEFAULT FFFFh READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) MEMORY TYPE Nonvolatile (SEE) A0h 215 214 213 212 211 210 29 28 A1h 27 26 25 24 23 22 21 0 BIT 7 BIT 0 Defines the crossover value for RSSI measurements of nonlinear inputs when XOVEREN is set to 1 (Table 02h, Register 8Bh).
PAGE 71
SFP+ Controller with Digital LDD Interface DS1878 Table 02h, Register AEh–AFh: INTERNAL TEMP OFFSET FACTORY CALIBRATED READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) AEh S 28 27 26 25 24 23 22 AFh 21 20 2-1 2-2 2-3 2-4 2-5 2-6 BIT 7 BIT 0 Allows for offset control of temperature measurement if desired. The final result must be XORed with BB40h before writing to this register.
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DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register B0h–B3h: PW1 FACTORY DEFAULT FFFF FFFFh READ ACCESS N/A WRITE ACCESS PW2 or (PW1 and WPW1) MEMORY TYPE Nonvolatile (SEE) B0h 231 230 229 228 227 226 225 224 B1h 223 222 221 220 219 218 217 216 B2h 215 214 213 212 211 210 29 28 B3h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The PWE value is compared against the value written to this location to enable PW1 access.
PAGE 73
SFP+ Controller with Digital LDD Interface B8h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RESERVED HLOS2 HLOS1 HLOS0 RESERVED LLOS2 DS1878 Table 02h, Register B8h: LOS RANGING LLOS21 BIT 7 LLOS0 BIT 0 This register controls the full-scale range of the quick-trip monitoring for the differential inputs of MON3. BIT 7 RESERVED (Default = 0) HLOS[2:0]: HLOS Full-Scale Ranging.
PAGE 74
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register B9h: COMP RANGING FACTORY DEFAULT B9h 00h READ ACCESS PW2 WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE) RESERVED BIAS2 BIAS1 BIAS0 RESERVED APC2 APC1 BIT 7 APC0 BIT 0 The upper nibble of this byte controls the full-scale range of the quick-trip monitoring for BIAS. The lower nibble of this byte controls the full-scale range for the quick-trip monitoring of the APC reference as well as the closed-loop monitoring of APC.
PAGE 75
SFP+ Controller with Digital LDD Interface BAh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 28 27 26 25 24 23 DS1878 Table 02h, Register BAh: ISTEPH 22 BIT 7 21 BIT 0 ISTEP is the initial step value used at power-on or after a TXD pulse to control the BIAS register. The particular ISTEP used depends on the value of TINDEX and ISTEPTI (Table 02h, Register C5h).
PAGE 76
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register BCh: HTXP BCh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 Fast-comparison DAC threshold adjust for high TXP. This value is added to the APC DAC value recalled from Table 06h. If the sum is greater than 0xFF, 0xFF is used.
PAGE 77
SFP+ Controller with Digital LDD Interface DS1878 Table 02h, Register BEh: HLOS BEh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 Fast-comparison DAC threshold adjust for high LOS. The combination of HLOS and LLOS creates a hysteresis comparator. As RSSI falls below the LLOS threshold, the LOS LO alarm bit is set to 1.
PAGE 78
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register C0h: PW_ENA C0h FACTORY DEFAULT 10h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RWTBL78 RWTBL1C RWTBL2 RWTBL1A RWTBL1B WLOWER WAUXA BIT 7 78 WAUXB BIT 0 BIT 7 RWTBL78: Tables 07h–08h 0 = (Default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. BIT 6 RWTBL1C: Table 01h or 05h bytes F8h–FFh.
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SFP+ Controller with Digital LDD Interface C1h FACTORY DEFAULT 03h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RWTBL46 RTBL1C RTBL2 RTBL1A RTBL1B WPW1 DS1878 Table 02h, Register C1h: PW_ENB WAUXAU WAUXBU BIT 7 BIT 0 BIT 7 RWTBL46: Read and Write Tables 04h, 06h 0 = (Default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2.
PAGE 80
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register C2h: MODTI C2h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 The modulation temperature index defines the TempCo boundary for the MODULATION LUT. The MODTC bit (Table 02h, Register C6h) defines the polarity of the TempCo.
PAGE 81
SFP+ Controller with Digital LDD Interface C4h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 BIT 7 DS1878 Table 02h, Register C4h: DAC2TI 21 20 BIT 0 DAC2 temperature index defines the TempCo boundary for the DAC2 LUT. The DAC2TC bit (Table 02h, Register C6h) defines the polarity of the TempCo.
PAGE 82
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register C6h: LUTTC C6h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) MODTC DAC1TC DAC2TC RESERVED RESERVED RESERVED RESERVED BIT 7 BIT 0 BIT 7 MODTC: Modulation TempCo 0 = Positive TempCo.
PAGE 83
SFP+ Controller with Digital LDD Interface C7h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 DS1878 Table 02h, Register C7h: TBLSELPON 22 21 BIT 7 20 BIT 0 Chooses the initial value for the table-select byte (Lower Memory, Register 7Fh) at power-on.
PAGE 84
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register CBh–CCh: BIAS REGISTER FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS N/A MEMORY TYPE Volatile CBh RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 28 CCh 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The digital value used for BIAS and resolved from the APC. This register is updated after each decision of the APC loop.
PAGE 85
SFP+ Controller with Digital LDD Interface FACTORY DEFAULT DEVICE VERSION READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS N/A MEMORY TYPE ROM CFh DS1878 Table 02h, Register CFh: DEVICE VER DEVICE VERSION BIT 7 BIT 0 Hardwired connections to show the device version.
PAGE 86
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register D8h–E7h: EMPTY FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE None These registers do not exist. Table 02h, Register E8h: RXCTRL1 E8h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register.
PAGE 87
SFP+ Controller with Digital LDD Interface EAh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 DS1878 Table 02h, Register EAh: SETCML 21 BIT 7 20 BIT 0 A 3-wire slave register.
PAGE 88
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register EDh: IMODMAX EDh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register.
PAGE 89
SFP+ Controller with Digital LDD Interface EFh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 DS1878 Table 02h, Register EFh: SETPWCTRL 21 BIT 7 20 BIT 0 A 3-wire slave register.
PAGE 90
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register F1h: SETTXEQ F1h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. The writing of this register is enabled using EXCTRL[1:0].
PAGE 91
SFP+ Controller with Digital LDD Interface F3h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 DS1878 Table 02h, Register F3h: SETLOSL 21 BIT 7 20 BIT 0 A 3-wire slave register. Only written if SETLOSCTL is 0. If SETLOSCTL is 1, then SETLOSH register is used.
PAGE 92
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register F5h: TXCTRL2 F5h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. The writing of this register is enabled using EXCTRL[1:0].
PAGE 93
SFP+ Controller with Digital LDD Interface F7h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RESERVED RESERVED RESERVED RESERVED RESERVED TXPORDIS DS1878 Table 02h, Register F7h: 3WSET EXCTRL1 BIT 7 BITS 7:3 BIT 2 BITS 1:0 EXCTRL2 BIT 0 RESERVED TXPORDIS: Transmit POR Disable. 0 = The 3-wire interface monitors the TXPOR bit in the laser driver’s TXSTAT1 register.
PAGE 94
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register F9h: ADDRESS F9h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 This byte is used during manual 3-wire communication. When a manual read or write is initiated, this register contains the address for the operation.
PAGE 95
SFP+ Controller with Digital LDD Interface DS1878 Table 02h, Register FBh: READ FACTORY DEFAULT FBh 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS N/A MEMORY TYPE Volatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 This byte is used during maunual 3-wire communication. When a manual read is initiated, the return data is stored in this register.
PAGE 96
DS1878 SFP+ Controller with Digital LDD Interface Table 02h, Register FEh–FFh: RESERVED FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) These registers are reserved.
PAGE 97
SFP+ Controller with Digital LDD Interface Table 06h, Register 80h–A3h: APC LUT 80h–A3h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (EE) 27 26 25 BIT 7 24 23 22 21 20 BIT 0 The APC LUT is a set of registers assigned to hold the temperature profile for the APC reference DAC.
PAGE 98
DS1878 SFP+ Controller with Digital LDD Interface Table 07h Register Descriptions Table 07h, Register 80h–A3h: DAC1 LUT 80h–A3h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL78) and (PW1 and RTBL78) WRITE ACCESS PW2 or (PW1 and RWTBL78) MEMORY TYPE Nonvolatile (EE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 The DAC1 LUT is a set of registers assigned to hold the PWM profile for DAC1. The values in this table determine the set point for DAC1.
PAGE 99
SFP+ Controller with Digital LDD Interface Table 08h, Register 80h–A3h: DAC2 LUT 80h–A3h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78) WRITE ACCESS PW2 or (PW1 and RWTBL78) MEMORY TYPE Nonvolatile (EE) 27 26 25 BIT 7 24 23 22 21 20 BIT 0 The DAC2 LUT is set of registers assigned to hold the PWM profile for DAC2. The values in this table determine the set point for DAC2.
PAGE 100
DS1878 SFP+ Controller with Digital LDD Interface Auxiliary Memory A0h Register Description Auxiliary Memory A0h, Register 00h–FFh: EEPROM 00h–FFh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and WAUXA) or (PW1 and WAUXAU) WRITE ACCESS PW2 or (PW1 and WAUXA) MEMORY TYPE Nonvolatile (EE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 Accessible with the slave address A0h.
PAGE 101
SFP+ Controller with Digital LDD Interface REVISION NUMBER REVISION DATE 0 9/10 Initial release 8/11 Added information about the RSELPIN bit to the IN1, RSEL, RSELOUT section and Table 02h, Register 89: CNFGA; added information about the VCCTXF and TXF_TXDEN bits to the Transmit Fault (TXFOUT) Output section, Table 02h, Register 89: CNFGA, and Table 02h, Register 8Ah: CNFGB 1 DESCRIPTION PAGES CHANGED — 22–26, 64, 65 Maxim cannot assume responsibility for use of any circuitry other than circuitry