Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsIntegrated Circuits (ICs)EDIP 28 64 kBit 8 K x 8

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FEATURES

 10 years minimum data retention in the

absence of external power

 Data is automatically protected during power

loss

 Directly replaces 2k x 8 volatile static RAM

or EEPROM

 Unlimited write cycles

 Low-power CMOS

 JEDEC standard 28-pin DIP package

 Read and write access times of 150 ns

 Full ±10% operating range

 Optional industrial temperature range of

-40°C to +85°C, designated IND

PIN ASSIGNMENT

24-Pin ENCAPSULATED PACKAGE

720-mil EXTENDED

PIN DESCRIPTION

A0-A12 - Address Inputs

DQ0-DQ7 - Data In/Data Out

- Chip Enable

- Write Enable

- Output Enable

- Power (+5V)

GND - Ground

DESCRIPTION

The DS1225Y 64k Nonvolatile SRAM is a 65,536-bit, fully static, nonvolatile RAM organized as 8192

words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which

constantly monitors V

for an out-of-tolerance condition. When such a condition occurs, the lithium

energy source is automatically switched on and write protection is unconditionally enabled to prevent

data corruption. The NV SRAM can be used in place of existing 8k x 8 SRAMs directly conforming to

the popular bytewide 28-pin DIP standard. The DS1225Y also matches the pinout of the 2764 EPROM or

the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the

number of write cycles that can be executed and no additional support circuitry is required for micro-

processor interfacing.

DS1225Y

64k Nonvolatile SRAM

19-5603; Rev 10/10

www.maxim-ic.com

DQ0

DQ1

GND

DQ2

VCC

A11

A10

DQ7

DQ6

DQ5

DQ3

DQ4

A12

NOT RECOMMENDED FOR NEW DESIGNS

Summary of content (8 pages)

PAGE 1
9-5603; Rev 10/10 NOT RECOMMENDED FOR NEW DESIGNS DS1225Y 64k Nonvolatile SRAM www.maxim-ic.
PAGE 2
NOT RECOMMENDED FOR NEW DESIGNS DS1225Y READ MODE The DS1225Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 13 address inputs (A0-A12) defines which of the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE access times are also satisfied.
PAGE 3
NOT RECOMMENDED FOR NEW DESIGNS DS1225Y ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground Operating Temperature Range Commercial: Industrial: Storage Temperature Lead Temperature (soldering, 10s) Note: EDIP is wave or hand soldered only. -0.3V to +6.0V 0°C to +70°C -40°C to +85°C -40°C to +85°C +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
PAGE 4
NOT RECOMMENDED FOR NEW DESIGNS DS1225Y AC ELECTRICAL CHARACTERISTICS PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High Z from Deselection Output Hold from AddressChange Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time (TA: See Note 10; VCC =5.
PAGE 5
NOT RECOMMENDED FOR NEW DESIGNS DS1225Y READ CYCLE SEE NOTE 1 WRITE CYCLE 1 SEE NOTE 2, 3, 4, 6, 7, 8 AND 12 WRITE CYCLE 2 SEE NOTE 2, 3, 4, 6, 7, 8 AND 13 5 of 8
PAGE 6
NOT RECOMMENDED FOR NEW DESIGNS DS1225Y POWER-DOWN/POWER-UP CONDITION SEE NOTE 11 POWER-DOWN/POWER-UP TIMING PARAMETER CE at VIH before Power-Down VCC Slew from VTP to 0V VCC Slew from 0V to VTP CE at VIH after Power-Up SYMBOL tPD tF tR tREC MIN 0 100 0 MAX 2 UNITS µs µs µs ms NOTES 11 (TA = +25°C) PARAMETER Expected Data Retention Time SYMBOL tDR MIN 10 MAX UNITS years NOTES 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery back
PAGE 7
NOT RECOMMENDED FOR NEW DESIGNS DS1225Y 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 9. Each DS1225Y is marked with a 4-digit date code AABB. AA designates the year of manufacture. BB designates the week of manufacture. The expected tDR is defined as starting at the date of manufacture. 10.
PAGE 8
NOT RECOMMENDED FOR NEW DESIGNS DS1225Y REVISION HISTORY REVISION DATE 121907 10/10 DESCRIPTION Added the Package Information table; removed the DIP module package drawing and dimension table Added Not Recommended for New Designs status; updated the storage information, soldering temperature, and lead temperature information in the Absolute Maximum Ratings section; removed the -170 and -200 MIN/MAX information from the AC Electrical Characteristics table; added the updated the Ordering Information table