Datasheet

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DESCRIPTION

The 78Q2123 and 78Q2133, MicroPHY

, are the

smallest 10BASE-T/100BASE-TX Fast Ethernet

transceivers in the market. They include integrated

MII, ENDECs, scrambler/descrambler, dual-speed

clock recovery, and full-featured auto-negotiation

functions. The transmitter includes an on-chip pulse-

shaper and a low-power line driver. The receiver has

an adaptive equalizer and a baseline restoration

circuit required for accurate clock and data recovery.

The transceiver interfaces to Category-5 unshielded

twisted pair (Cat-5 UTP) cabling for 100BASE-TX

applications, and Category-3 unshielded twisted pair

(Cat-3 UTP) for 10BASE-T applications. The MDI is

connected to the line media via dual 1:1 isolation

transformers. No external filter is required. Interface

to the MAC is accomplished through an IEEE-802.3

compliant Media Independent Interface (MII). The

78Q2123/78Q2133 are intended to serve the

embedded Ethernet market, tailored specifically to the

needs of game consoles, broadband modems,

printers, set top boxes and audio/visual equipment. It

is designed for low-power consumption and operates

from a single 3.3V supply. The 78Q2123 is rated for

commercial temperature range and the 78Q2133 is

rated for industrial temperature range.

FEATURES

x Smallest 10/100 PHY available

x 10BASE-T/100BASE-TX IEEE-802.3 compliant

TX and RX functions requiring a dual 1:1 isolation

transformer interface to the line

x Integrated MII,

10BASE-T/100BASE-TX ENDEC,

100BASE-TX scrambler/descrambler, and

full-featured auto-negotiation function

x Full duplex operation capable

x Automatic MDI/MDI-X cross over correction

x Register-programmable transmit amplitude

x Automatic polarity correction during auto-

negotiation and 10BASE-T signal reception

x Power-saving and power-down modes including

transmitter disable

x 2 Programmable LED indicators (Link and

Activity by default)

x User programmable Interrupt pin

Packages:

32-QFN (5x5 mm) and 32-TQFN (5x5mm)

x Low Power (~290mW)

x Single 3.3 V r0.3V Supply

x 78Q2123 rated for 0°C to 70°C operation

x 78Q2133 rated for -40°C to 85°C operation

RXC

TXC

RXD

TXD

SMI

MII

100M

10M

Scrambler,

Parallel/Serial

Parallel/Serial,

Manchester Encoder

MRZ/NRZI

MLT3 Encoder

TX CLK GEN

Auto

MDI-X

Mux

Tx/Rx

Rx/Tx

Carrier Sense,

Collision Detect

CLK

Recovery

10M

100M

Adaptive EQ,

Baseline Wander Correct,

MLT3 Decode, NRZI/NRZ

Clock Reference

LEDs

CLKIN

25MHz

Link

Act

Rev. 2.0 1

DATA SHEET

78Q2123/78Q2133 MicroPHY™

10/100BASE-TX Transceiver

SimplifyingSystemIntegration

Pulse Shaper

and Filter

Manchester Decoder,

Parallel/Serial

MII

Registers

Serial/Parallel

Descrambler,

5B/4B Decoder

Summary of content (37 pages)

PAGE 1
78Q2123/78Q2133 MicroPHY™ 10/100BASE-TX Transceiver Simplifying System IntegrationTM DESCRIPTION DATA SHEET FEATURES TM The 78Q2123 and 78Q2133, MicroPHY , are the smallest 10BASE-T/100BASE-TX Fast Ethernet transceivers in the market. They include integrated MII, ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions. The transmitter includes an on-chip pulseshaper and a low-power line driver.
PAGE 2
78Q2123/78Q2133 Data Sheet DS_21x3_001 Table of Contents 1 Functional Description ..........................................................................................................................5 1.1 General...........................................................................................................................................5 1.1.1 Power Management............................................................................................................5 1.1.
PAGE 3
DS_21x3_001 4 78Q2123/78Q2133 Data Sheet 5 Electrical Specifications ......................................................................................................................23 4.1 Absolute Maximum Ratings .........................................................................................................23 4.2 Recommended Operating Conditions .........................................................................................23 4.3 DCCharacteristics ...............................
PAGE 4
78Q2123/78Q2133 Data Sheet DS_21x3_001 Figures Figure 1: RST Pulse Duration ...........................................................................................................................25 Figure 2: Transmit Inputs to the 78Q2123/78Q2133........................................................................................25 Figure 3: Receive Outputs from the 78Q2123/78Q2133 .................................................................................
PAGE 5
DS_21x3_001 78Q2123/78Q2133 Data Sheet 1 Functional Description 1.1 General 1.1.1 Power Management The 78Q2123 and 78Q2133 have three power saving modes: x Chip Power-Down x x Receive Power Management Transmit High Impedance Mode Chip power-down is activated by setting the PWRDN bit in MII register MR0.11. When the chip is in power-down mode, all on-chip circuitry is shut off, and the device consumes minimum power.
PAGE 6
78Q2123/78Q2133 Data Sheet 1.1.5 DS_21x3_001 Receive Signal Qualification The integrated signal qualifier has separate squelch and unsquelch thresholds. It also includes a built-in timer to ensure fast and accurate signal detection and line noise rejection. Upon detection of two or more valid 10BASE-T or 100BASE-TX pulses on the line receive port, signal detect is indicated. The signal detect threshold is then lowered by about 40%.
PAGE 7
DS_21x3_001 78Q2123/78Q2133 Data Sheet The received MLT-3 signal is converted to 5 bit NRZ code groups and output from the RX_ER and RXD[3:0] pins, RX_ER being the MSB of the data output. The RX_DV and TX_EN pins are unused in PCS Bypass mode. 1.3 1.3.1 10BASE-T OPERATION 10BASE-T Transmit The 78Q2123/78Q2133 take 4-bit parallel NRZ data via the MII interface and passes it through a parallel to serial converter.
PAGE 8
78Q2123/78Q2133 Data Sheet 1.4 DS_21x3_001 Auto-Negotiation The 78Q2123/78Q2133 support the auto-negotiation functions of Clause 28 of IEEE-802.3 for 10/100 Mbps operation over copper wiring. This function can be enabled via register settings. The auto-negotiation function defaults to ON and bit MR0.12 (ANEGEN) is high after reset. Software can disable the auto-negotiation function by writing to bit MR0.12.
PAGE 9
DS_21x3_001 1.5 1.5.1 78Q2123/78Q2133 Data Sheet Media Independent Interface MII Transmit and Receive Operation The MII interface on the 78Q2123/78Q2133 provide independent transmit and receive paths for both 10Mb/s and 100Mb/s data rates as described in Clause 22 of the IEEE-802.3 standard. The transmit clock, TX_CLK, provides the timing reference for the transfer of TX_EN, TXD3-0, and TX_ER signals from the MAC to the 78Q2123/78Q2133.
PAGE 10
78Q2123/78Q2133 Data Sheet 1.6 DS_21x3_001 Additional Features 1.6.1 LED Indicators There are two LED pins that can be used to indicate various states of operation of the 78Q2123/78Q2133.
PAGE 11
DS_21x3_001 78Q2123/78Q2133 Data Sheet 2 Pin Description 2.1 Legend Type Description A Type Analog Pin CI Description TTL-level Input CIU TTL-level Input with Pull-up CIO TTL-compatible Bi-directional Pin CIS TTL-level Input with Schmitt Trigger COZ Tristate-able CMOS Output CO CMOS Output S 2.
PAGE 12
78Q2123/78Q2133 Data Sheet RXD[3:0] DS_21x3_001 [5:8] COZ RECEIVE DATA: Received data is provided to the MAC via RXD[3:0]. These pins are tri-stated in isolate mode. RX_ER 13 COZ RECEIVE ERROR: RX_ER is asserted high when an error is detected during frame reception. In PCS bypass mode, this pin becomes the MSB of the receive 5-bit code group. This pin is tri-stated in isolate mode. MDC 2 CIS MANAGEMENT DATA CLOCK: MDC is the clock used for transferring data via the MDIO pin.
PAGE 13
DS_21x3_001 2.7 78Q2123/78Q2133 Data Sheet LED Signals (Programmability Is Secondary Requirement) Signal Pin Type Description LED0 4 CO PROGRAMMABLE LED. Active low. Default status: LINK OK. Active to indicate link with far end PHY. LED1 3 CO PROGRAMMABLE LED. Active low. Default status: RX or TX ACTIVITY. Active to indicate TX or RX activity on the MDI. Other LED options selectable via MR23: TRANSMIT: ON when there is a transmission (normally OFF).
PAGE 14
78Q2123/78Q2133 Data Sheet DS_21x3_001 3 Register Description The 78Q2123/78Q2133 implement 13 16-bit registers, which are accessible via the MDIO and MDC pins. The supported registers are shown below in the following table. Attempts to read unsupported registers will be ignored and the MDIO pin will not be enabled as an output, as per the IEEE 802.3 specification. All of the registers except those that are unique to the 78Q2123/78Q2133 will respond to the broadcast PHYAD value of ‘00000’.
PAGE 15
DS_21x3_001 3.1 78Q2123/78Q2133 Data Sheet MR0: Control Register Bit Symbol Type Default Description 0.15 RESET R/WC 0 Reset: Setting this bit to ‘1’ resets the device and sets all registers to their default states. This bit is self-clearing. 0.14 LOOPBK R/W 0 Loopback: When this bit is set to ‘1’, input data at TXD[3:0] is output at RXD[3:0]. No transmission of data on the network medium occurs and receive data on the network medium is ignored.
PAGE 16
78Q2123/78Q2133 Data Sheet 3.2 DS_21x3_001 MR1: Status Register Bits 1.15 through 1.11 reflect the ability of the 78Q2123/78Q2133. They do not reflect any ability changes made via the MII Management Interface to bits 0.13 (SPEEDSL) , 0.12 (ANEGEN) and 0.8 (DUPLEX) in the Control Register. Bit Symbol Type Default 1.15 100T4 R 0 100BASE-T4 Ability: Reads ‘0’ to indicate the 78Q2123/78Q2133 do not support 100Base-T4 mode. 1.
PAGE 17
DS_21x3_001 78Q2123/78Q2133 Data Sheet cleared by a read operation. 1.0 3.3 EXTD R 1 Extended Capability: Reads ’1’ to indicate the 78Q2123/78Q2133 provide an extended register set (MR2 and beyond). MR2: PHY Identifier Register 1 Bit Symbol Type Value Description 2.15:0 OUI [23:6] R 000Eh Organizationally Unique Identifier: This value is 00-C0-39 for Teridian Semiconductor Corporation. This register contains the first 16-bits of the identifier. 3.
PAGE 18
78Q2123/78Q2133 Data Sheet DS_21x3_001 4.5 A0 R/W (1) 10BASE-T: If the MR1.11 bit is ‘1’, this bit will be set to ‘1’ upon reset and will be writeable. Otherwise, this bit cannot be set to ‘1’ by the management. 4.4:0 S4:0 R 01h Selector Field: Hard coded with the value of ‘00001’ for IEEE 802.3. Note: Technology Ability Field: MR4.12:5 are the Technology Ability Field bits (A7:0). The default value of this field is dependent upon the MR1.15:11 register bits.
PAGE 19
DS_21x3_001 78Q2123/78Q2133 Data Sheet prohibited, CRS responds to receive activity only and, in 10Base-T mode, the SQE test function is disabled. 16.14 INPOL R/W 0 When this bit is ‘0’, the INTR pin is forced low to signal an interrupt. Setting this bit to ‘1’ causes the INTR pin to be forced high to signal an interrupt. 16.13 RSVD R 0 Reserved 16.12 TXHIM R/W 0 Transmitter High-Impedance Mode: When set, the TXOP/TXON transmit pins and the TX_CLK pin are put into a high-impedance state.
PAGE 20
78Q2123/78Q2133 Data Sheet 3.9 DS_21x3_001 MR17: Interrupt Control/Status Register The Interrupt Control/Status Register provides the means for controlling and observing the events, which trigger an interrupt on the INTR pin. This register can also be used in a polling mode via the MII Serial Interface as a means to observe key events within the PHY via one register address. Bits 0 through 7 are status bits, which are each set to logic one based upon an event.
PAGE 21
DS_21x3_001 78Q2123/78Q2133 Data Sheet 3.10 MR18: Diagnostic Register Bit Symbol Type Default Description 18.15:13 RSVD R 0 Reserved 18.12 ANEGF RC 0 Auto-Negotiation Fail Indication: This bit is set when auto-negotiation completes and no common technology was found. It remains set until read. 18.
PAGE 22
78Q2123/78Q2133 Data Sheet DS_21x3_001 3.15 MR23: LED Configuration Register Bit Symbol Type Default Description 23.15:8 Reserved NA <0000> Must set to zero on each write to MR23 23.7:4 LED1[3:0] R/W <1h> 0000 = Link OK 0001 = RX or TX Activity (Default LED1) 0010 = TX Activity 0011 = RX Activity 0100 = Collision 0101 = 100 BASE-TX mode 0110 = 10 BASE-T mode 0111 = Full Duplex 1000 = Link OK/Blink=RX or TX Activity 23.
PAGE 23
DS_21x3_001 78Q2123/78Q2133 Data Sheet 4 Electrical Specifications 4.1 Absolute Maximum Ratings Operation above maximum rating may permanently damage the device. Parameter Rating DC Supply Voltage (Vcc) -0.5 to 4.0 VDC Storage Temperature -65 to 150 qC Pin Voltage (except TXOP/N) -0.3 to (Vcc+0.6) VDC Pin Voltage (TXOP/N only) -0.3 to (Vcc+1.4) VDC Pin Current r 120 mA 4.
PAGE 24
78Q2123/78Q2133 Data Sheet 4.4 DS_21x3_001 Digital I/O Characteristics Pins of type CI, CIU, CID, CIO Parameter Symbol Conditions Min Nom Max Unit 0.8 V Input Voltage Low Vil Input Voltage High Vih 2.0 3.6 V Input Current Iil, Iih -1 1 PA Pull-up Resistance Rpu 78 k: Input Capacitance Cin Type CIU only 38 56 8 pF Pins of type CIS Parameter Symbol Conditions Min Low-to-High Threshold Vt+ High-to-Low Threshold Vt- 0.
PAGE 25
DS_21x3_001 4.5 4.5.1 78Q2123/78Q2133 Data Sheet Digital Timing Characteristics RST Characteristics VCC Oscillator RST Treset Figure 1: RST Pulse Duration Parameter Symbol RST Pulse Assertion 4.5.2 Treset Conditions Min VCC = 3.
PAGE 26
78Q2123/78Q2133 Data Sheet 4.5.3 DS_21x3_001 MII Receive Interface Characteristics Symbol Receive Output Delay: RX_CLK to RXD[3:0], RX_DV, RX_ER Conditions RXDLY RX_CLK Duty-Cycle Min Nom Max Unit 10 30 ns 40 60 % Max Unit Figure 3: Receive Outputs from the 78Q2123/78Q2133 4.
PAGE 27
DS_21x3_001 4.6.
PAGE 28
78Q2123/78Q2133 Data Sheet 4.6.
PAGE 29
DS_21x3_001 4.6.3 78Q2123/78Q2133 Data Sheet 100BASE-TX System Timing System timing requirements for 100BASE-TX operation are listed in Table 24-2 of Clause 24 of IEEE 802.3.
PAGE 30
78Q2123/78Q2133 Data Sheet 4.7 4.7.1 DS_21x3_001 Analog Electrical Characteristics 100BASE-TX Transmitter Parameter Peak Output Amplitude (|Vp+|, |Vp-|) (see note below) Condition Best-fit over 14 bit times; 0.4 dB Transformer loss |Vp +| |Vp -| Output Amplitude Symmetry Output Overshoot Percent of Vp+, Vp- Rise/Fall time (tr, tf) 10-90% of Vp+, Vp- Rise/Fall time Imbalance Min Nom Max Unit 950 1050 mVpk 0.98 1.
PAGE 31
DS_21x3_001 4.7.4 78Q2123/78Q2133 Data Sheet 10BASE-T Transmitter The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in Clause 14 of IEEE 802.3. Parameter Condition Min Peak Differential Output Signal All data patterns (see note below) 2.2 Harmonic Content (dB below fundamental) 27 Any harmonic All ones data Not tested Link Pulse Width Start-of-Idle Pulse Width Last bit 0 Last bit 1 Nom Max Unit 2.
PAGE 32
78Q2123/78Q2133 Data Sheet DS_21x3_001 LED 1 D1 R1 680 D2 R3 680 VCC R2 5.1K R4 100 R5 100 LED 0 VCC INTR VCC C1 0.1uF R10 100 R12 100 R13 100 8 7 6 5 4 3 2 1 9 10 11 12 13 14 15 16 78Q2123 VCCD DD 78Q2133 GN RX_DV RX_CLK RX_ER 78Q2123 TX_ER TX_CLK TX_EN J1 RJ45 0.1uF 9 RXD0 RXD1 RXD2 RXD3 LED0 LED1 MDC MDIO 0.
PAGE 33
DS_21x3_001 4.8 78Q2123/78Q2133 Data Sheet Isolation Transformers Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer characteristics. Name Value Condition Turns Ratio 1 CT : 1 CT r 5% Open-Circuit Inductance 350 PH (min) @ 10 mV, 10 kHz Leakage Inductance 0.40 PH (max) @ 1 MHz (min) Inter-Winding Capacitance 25 pF (max) D.C.
PAGE 34
78Q2123/78Q2133 Data Sheet DS_21x3_001 Tr XTLP Tf Tclkper Tclkhi Figure 8: External XTLP Oscillator Characteristics 4.9.1 External XTLP Oscillator Characteristics Parameter Symbol XTLP Input Level Condition Min Nom XTLP Period Absolute Jitter V See Note 1 25.000 MHz Tclkper See Note 1 40 ns Tclkhi / Tclkper Tr, Tf Input signaling requirements = CIS Note 1: IEEE 802.3 frequency tolerance r50 ppm. 34 0.
PAGE 35
DS_21x3_001 78Q2123/78Q2133 Data Sheet 5 Package Pin Designations INTR TXON TXOP GND RXIP RXIN PWR XTLN 32 31 30 29 28 27 26 25 (Top View) MDIO 1 24 XTLP MDC 2 23 RST LED1 3 22 CRS LED0 4 21 COL RXD3 5 20 TXD3 RXD2 6 19 TXD2 RXD1 7 18 TXD1 RXD0 8 17 TXD0 13 14 15 16 TX_ER TX_CLK TX_EN 11 RX_DV RX_ER 10 GND RX_CLK 12 9 PWR TERIDIAN 78Q2123 78Q2133 Note: For information only, actual package outline will vary depending on package type.
PAGE 36
78Q2123/78Q2133 Data Sheet DS_21x3_001 6 Package Information PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
PAGE 37
DS_21x3_001 78Q2123/78Q2133 Data Sheet Revision History Rev. # Date Comments 1.0 9/15/2005 First publication. 1.6 4/16/2010 Removed the 32-pin TQFP option. 2.0 9/24/2014 Added 32-TQFN package. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product.