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78Q2120C

10/100BASE-TX

Transceiver

DATA SHEET

TXD[3:0]

4B/5B Encoder,

Scrambler,

Parallel/Serial

Parallel/Serial,

Manchester Encoder

Manchester Decoder,

Parallel/Serial

Serial/Parallel

Descrambler,

5B/4B Decoder

NRZ/NRZI

MLT3 Encoder

TX CLK GEN

Carrier Sense,

Collision Detect

CLK

Recovery

Clock Reference

100M

10M

25MHz

Pulse Shaper

and Filter

uto

Negotiation

daptive EQ,

Baseline Wander Correct,

MLT3 Decode, NRZI/NRZ

LEDs

LEDL LEDBTX LEDTX LEDCOL

LEDBT LEDFX LEDRX

MDI

10M 100M

CKIN

GND

VCC

MII

Registers

Interface

Logic

RXD[3:0]

TX_CLK

RX_CLK

4B/5B Encoder,

Scrambler,

Parallel/Serial

Parallel/Serial,

Manchester Encoder

Manchester Decoder,

Parallel/Serial

Serial/Parallel

Descrambler,

5B/4B Decoder

NRZ/NRZI

MLT3 Encoder

TX CLK GEN

Carrier Sense,

Collision Detect

CLK

Recovery

Clock Reference

100M

10M

25MHz

Pulse Shaper

and Filter

uto

Negotiation

daptive EQ,

Baseline Wander Correct,

MLT3 Decode, NRZI/NRZ

LEDs

MDI

10M 100M

RXIP/N

TXOP/N

GND

VCC

MII

Registers

Interface

Logic

January 2009

DESCRIPTION

The 78Q2120C is a 10BASE-T/100BASE-TX Fast

Ethernet transceiver. It includes integrated MII,

ENDECs, scrambler/descrambler, dual-speed clock

recovery, and full-featured auto-negotiation function.

The transmitter includes an on-chip pulse-shaper and

a low-power line driver. The receiver has an adaptive

equalizer and a baseline restoration circuit required

for accurate clock and data recovery. The transceiver

interfaces to Category-5 unshielded twisted pair (Cat-

5 UTP) cabling for 100BASE-TX/10BASE-T and

Category-3 unshielded twisted pair for 10BASE-T.

Connection to the line media is via 1:1 isolation

transformers. No external filter is required. Interface

to the MAC is accomplished through an IEEE-802.3

compliant Media Independent Interface (MII). The

product is fabricated in an advanced CMOS process

for high performance and low power operation.

FEATURES

• 10BASE-T/100BASE-TX IEEE-802.3 compliant

TX and RX functions requiring a dual 1:1

isolation transformer interface to the line

• Integrated MII, 10BASE-T/100BASE-TX ENDEC,

100BASE-TX scrambler/descrambler, and full-

featured auto-negotiation function

• Full duplex operation capable

• PCS Bypass supports 5-bit symbol interface

• Register-programmable transmit amplitude

• Dual speed digital clock recovery

• Automatic polarity correction during auto-

negotiation and 10BASE-T signal reception

• Power-saving and power-down modes

including transmitter disable

• LED indicators: LINK, TX, RX, COL, 100, 10,

FDX

• User programmable Interrupt pin

• 64-Pin TQFP (JEDEC LQFP) package

• Single 3.3 V ± 0.3V Supply

BLOCK DIAGRAM

Summary of content (35 pages)

PAGE 1
78Q2120C 10/100BASE-TX Transceiver DATA SHEET January 2009 DESCRIPTION FEATURES The 78Q2120C is a 10BASE-T/100BASE-TX Fast Ethernet transceiver. It includes integrated MII, ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation function. The transmitter includes an on-chip pulse-shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery.
PAGE 2
78Q2120C 10/100BASE-TX Transceiver • Chip Power-Down mode of operation, a 25MHz crystal should be connected between the XTLP and XTLN pins. Alternatively, an external 25MHz clock signal can be connected to the CKIN pin. The chip senses activity on the CKIN pin, and will automatically configure itself to use the external clock. In this mode of operation, a crystal is not required and the XTLP and XTLN pins should be left floating or connected together.
PAGE 3
78Q2120C 10/100BASE-TX Transceiver CDR immediately re-aligns the phase of the clock to synchronize with the incoming data. Hence clock acquisition is fast and immediate. 100BASE-TX OPERATION 100BASE-TX Transmit The 78Q2120C contains all of the necessary circuitry to convert the transmit MII signaling from a MAC to an IEEE-802.3 compliant data-stream driving Cat-5 UTP cabling. The internal PCS interface maps 4 bit nibbles from the MII to 5 bit code groups as defined in Table 24-1 of IEEE-802.3.
PAGE 4
78Q2120C 10/100BASE-TX Transceiver SQE TEST The 78Q2120C supports the Signal Quality Error (SQE) function detailed in IEEE-802.3. At an interval of 1µs after each negative transition of the TXEN pin in 10BASE-T mode, the COL pin will go high for a period of 1µs. SQE is not signaled during transmission after collision is detected. SQE is automatically disabled when repeater mode is enabled. This function can be disabled through register bit MR16.11.
PAGE 5
78Q2120C 10/100BASE-TX Transceiver Station Management Interface The station management interface consists of circuitry which implements the serial protocol as described in Clause 22.2.4.5 of IEEE-802.3. A 16bit shift register receives serial data applied to the MDIO pin at the rising-edge of the MDC clock signal. Once the preamble is received, the station management control logic looks for the start-offrame sequence and a read or write op-code, followed by the PHYAD and REGAD fields.
PAGE 6
78Q2120C 10/100BASE-TX Transceiver PIN DESCRIPTION LEGEND TYPE A DESCRIPTION TYPE Analog Pin CI DESCRIPTION TTL-level Input (5V compatible) CIU TTL-level Input w/ Pull-up (5V compatible) CIO TTL-compatible Bi-directional Pin (5V compatible) CID TTL-level Input w/ Pull-down COZ Tristate-able CMOS output (5V compatible) CIS TTL-level Input w/ Schmitt Trigger G Ground S Supply (5V compatible) CO CMOS Output MII (MEDIA INDEPENDENT INTERFACE) NAME PIN TYPE DESCRIPTION TX_CLK 27 COZ T
PAGE 7
8Q2120C 10/100BASE-TX Transceiver MII (continued) NAME PIN TYPE DESCRIPTION RX_ER 25 COZ RECEIVE ERROR: RX_ER is asserted high when an error is detected during a frame reception. In PCS bypass mode, this pin becomes the MSB of the receive 5-bit code group. This pin is tristated in the isolate mode. MDC 18 CIS MANAGEMENT DATA CLOCK: MDC is the clock used for transferring data via the MDIO pin.
PAGE 8
78Q2120C 10/100BASE-TX Transceiver CONTROL AND STATUS (CONTINUED) NAME PIN TYPE ISO 2 CI ISOLATE: When set to logic one, the 78Q2120C will present a high impedance on its MII output pins. This allows for multiple chips to be attached to the same MII interface. When the 78Q2120C is isolated, it still responds to management transactions. This high impedance state can also be achieved using the ISO bit in the MII register (MR0.10).
PAGE 9
78Q2120C 10/100BASE-TX Transceiver LED INDICATORS The LED pins use standard logic drivers. They output a logic low when the LED is meant to be on and a logic high when it is meant to be off. The LED should be connected in series with a resistor between the output pin and the power supply. NAME PIN TYPE DESCRIPTION LEDL 40 CO LED LINK: ON for link up. LEDTX 39 CO LED TRANSMIT: ON when there is a transmission (normally OFF). LEDRX 38 CO LED RECEIVE: ON when there is a reception (normally OFF).
PAGE 10
78Q2120C 10/100BASE-TX Transceiver REGISTER DESCRIPTION The 78Q2120C implements 11 16-bit registers, which are accessible via the MDIO and MDC pins. The supported registers are shown below in the following table. Attempts to read unsupported registers will be ignored and the MDIO pin will not be enabled as an output, as per the IEEE 802.3 specification. All of the registers except those which are unique to the 78Q2120C, will respond to the broadcast PHYAD value of ‘00000’.
PAGE 11
78Q2120C 10/100BASE-TX Transceiver MR0: Control Register BIT 0.15 SYMBOL RESET TYPE R/SC 0.14 LOOPBK R/W 0 Loopback: When this bit is set to ‘1’, no transmission of data on the network medium occurs and any receive data on the network medium is ignored. The loopback signal path will encompass most of the digital circuitry. 0.13 SPEEDSL R/W (1) Speed Selection: This bit determines the speed of operation of the 78Q2120C.
PAGE 12
78Q2120C 10/100BASE-TX Transceiver MR0: Control Register (continued) BIT 0.8 SYMBOL DUPLEX TYPE R/W DEFAULT DESCRIPTION (1) Duplex Mode: This bit determines whether the device supports fullduplex or half-duplex. A ‘1’ indicates full-duplex operation and a ‘0’ indicates half-duplex. This bit will default to ‘0’ upon reset and will be writeable if the TECH[2:0] pins are all logic zero and autonegotiation is not enabled.
PAGE 13
78Q2120C 10/100BASE-TX Transceiver MR1: Status Register BIT 1.9 SYMBOL 100T2_H TYPE R DEFAULT DESCRIPTION 0 100BASE-T2 Half Duplex Ability: Reads ‘0’ to indicate the 78Q2120C does not support 100Base-T2 full duplex mode. 1.8 EXTS R 0 Extended Status Information Availability: Reads ‘0’ to indicate the 78Q2120C does not support Extended Status information on MR15. 1.7 RSVD R 0 Reserved 1.
PAGE 14
78Q2120C 10/100BASE-TX Transceiver MR4: Auto-Negotiation Advertisement Register BIT 4.15 SYMBOL NP 4.14 RSVD R 0 Reserved 4.13 RF R/W 0 Remote Fault: Setting this bit to ‘1’ allows the device to indicate to the link partner a Remote Fault Condition. 4.12:5 TAF R/W (0Fh) Technology Ability Field: The default value of this field is dependent upon the MR1.15:11 register bits. This field can be overwritten by management to auto-negotiate to an alternate common technology.
PAGE 15
78Q2120C 10/100BASE-TX Transceiver MR5: Auto-Negotiation Link Partner Ability Register BIT 5.15 SYMBOL NP TYPE DEFAULT DESCRIPTION R 0 Next Page: When ‘1’ is read, it indicates the link partner wishes to engage in Next Page exchange. 5.14 ACK R 0 Acknowledge: When ‘1’ is read, it indicates the link partner has successfully received at least 3 consecutive and consistent FLP bursts. 5.13 RF R 0 Remote Fault: When ‘1’ is read, it indicates the link partner has a fault. 5.
PAGE 16
78Q2120C 10/100BASE-TX Transceiver MR16: Vendor Specific Register BIT 16.15 SYMBOL RPTR 16.14 INPOL R/W 0 When this bit is ‘0’, the INTR pin is forced low to signal an interrupt. Setting this bit to ‘1’ causes the INTR pin to be forced high to signal an interrupt. 16.13 RSVD R 0 Reserved 16.12 TXHIM R/W 0 Transmitter High-Impedance Mode: When set, the TXOP/TXON transmit pins and the TX_CLK pin are put into a high-impedance state. The receive circuitry remains fully functional. 16.
PAGE 17
78Q2120C 10/100BASE-TX Transceiver MR16: Vendor Specific Register (continued) Bit 16.1 Symbol PCSBP Type R/W Default (0) 16.0 RXCC R/W 0 Description PCS Bypass Mode: When set, the 100Base-TX PCS and scrambling/ descrambling functions are bypassed. Scrambled 5-bit code groups for transmission are applied to the TX_ER, TXD[3:0] pins and received on the RX_ER, RXD[3:0] pins. The RX_DV and TX_EN signals are not valid in this mode.
PAGE 18
78Q2120C 10/100BASE-TX Transceiver MR17: Interrupt Control/Status Register (continued) BIT 17.3 SYMBOL LP-ACK_INT TYPE DEFAULT DESCRIPTION RC 0 Link Partner Acknowledge Interrupt: This bit is set high by the auto-negotiation logic when FLP bursts are received with the acknowledge bit set. 17.2 LS_CHG_INT RC 0 Link Status Change Interrupt: This bit is set when the link transitions from an OK status to a FAIL status. 17.
PAGE 19
78Q2120C 10/100BASE-TX Transceiver MR19: Transceiver Control BIT 19.15:12 SYMBOL RSVD TYPE R 19.11:10 TXO[1:0] R/W DEFAULT DESCRIPTION 0100 Reserved 01 Transmit Amplitude Selection: Sets the transmit output amplitude to account for transmit transformer insertion loss. 00 : Gain set for 0.0dB of insertion loss 01 : Gain set for 0.4dB of insertion loss 10 : Gain set for 0.8dB of insertion loss 11 : Gain set for 1.2dB of insertion loss 19.9:0 RSVD R XXXh Reserved MR20: Reserved BIT 20.
PAGE 20
78Q2120C 10/100BASE-TX Transceiver ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Operation above maximum rating may permanently damage the device. PARAMETER RATING DC Supply Voltage (Vcc) -0.5 to 4.0 VDC Storage Temperature -65 to 150°C Pin Voltage (CMOS inputs) -0.3 to 5.5 VDC Pin Voltage (CMOS outputs except TXOP/N) -0.3 to (Vcc+0.6) VDC Pin Voltage (TXOP/N only) -0.3 to (Vcc+1.
PAGE 21
78Q2120C 10/100BASE-TX Transceiver DIGITAL I/O CHARACTERISTICS: Pins of type CI, CIU, CID, CIO: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT 0.8 V Input Voltage Low Vil Input Voltage High Vih 2.0 5.5 V Input Current Iil, Iih -1 1 µA Pull-up Resistance Rpu Type CIU only 38 56 78 kΩ Pull-down Resistance Rpd Type CID only 38 56 78 kΩ Input Capacitance Cin 8 pF Pins of type CIS: PARAMETER SYMBOL CONDITIONS MIN NOM MAX UNIT Low-to-High Threshold Vt+ 1.3 1.
PAGE 22
78Q2120C 10/100BASE-TX Transceiver DIGITAL TIMING CHARACTERISTICS RST Characteristics VCC Oscillator RST Treset RST Pulse Duration PARAMETER RST Pulse Assertion Page: 22 of 35 SYMBOL Treset CONDITIONS VCC = 3.3V and oscillator stabilized © 2009 Teridian Semiconductor Corporation MIN 30 NOM MAX UNIT Oscillator Clock Cycles Rev 1.
PAGE 23
78Q2120C 10/100BASE-TX Transceiver MII Transmit Interface CHARACTERISTICS SYMBOL CONDITIONS MIN NOM MAX UNIT Setup Time: TX_CLK to TXD[3:0], TX_EN, TX_ER TXSU 15 ns Hold Time: TX_CLK to TXD[3:0], TX_EN, TX_ER TXHD 0 ns CKIN-to-TX_CLK Delay TCKIN 0 40 ns 40 60 % MAX UNIT 10 30 ns 40 60 % TX_CLK Duty-Cycle TCKIN CKIN TX_CLK TXSU TXHD TXD[3:0] TX_EN or TX_ER Transmit Inputs to the 78Q2120C MII Receive Interface CHARACTERISTICS SYMBOL Receive Output Delay: RX_CLK to RXD[3:0
PAGE 24
78Q2120C 10/100BASE-TX Transceiver MDIO Interface Input Timing CHARACTERISTICS SYMBOL CONDITIONS MIN NOM MAX UNIT Setup Time: MDC to MDIO MIOSU 10 ns Hold Time: MDC to MDIO MIOHD 10 ns Max Frequency: MDC Fmax 25 MHz MAX UNIT MC2D 30 ns MDIO output from high Z to driven after MDC MCZ2D 30 ns MDIO output from driven to high Z after MDC MCD2Z 30 ns MDC MIOHD MIOSU MDIO MDIO as an Input to the 78Q2120C MDIO Interface Output Timing CHARACTERISTICS SYMBOL MDC to MDIO data delay
PAGE 25
Page: 25 of 35 1 1 Z Z © 2009 Teridian Semiconductor Corporation 1 Preamble 1 Preamble 1 1 1 0 Read 1 0 1 1 Write 0 Start of Operation Frame Code 0 Start of Operation Frame Code A A A A A A A PHY Address A PHY Address A A R R R R R R R R R R 0 1 0 Turnaround Z Turnaround D D D D D D D D D D D D D D D Data D Data D D D D D D D D D D D D D D D D Z Z 78Q2120C 10/100BASE-TX Transceiver MDIO Interface Output Timing Rev 1.
PAGE 26
78Q2120C 10/100BASE-TX Transceiver 100BASE-TX System Timing System timing requirements for 100BASE-TX operation are listed in Table 24-2 of Clause 24 of IEEE 802.3.
PAGE 27
78Q2120C 10/100BASE-TX Transceiver ANALOG ELECTRICAL CHARACTERISTICS 100BASE-TX Transmitter PARAMETER Peak Output Amplitude (|Vp+|, |Vp-|) (see note below) CONDITION MIN Best-fit over 14 bit times; NOM MAX UNIT 950 1050 mVpk 0.98 1.02 0.
PAGE 28
78Q2120C 10/100BASE-TX Transceiver 100BASE-TX Receiver PARAMETER CONDITION MIN NOM MAX UNIT Signal Detect Assertion Threshold 500 600 700 mVppd Signal Detect De-assertion Threshold 275 350 425 mVppd Differential Input Resistance 20 Jitter Tolerance (pk-pk) Not tested in production Baseline Wander Tracking kΩ 4 ns -75 +75 % Signal Detect Assertion Time Not tested 1000 µs Signal Detect De-assertion Time Not tested 4 µs 10BASE-T Transmitter The Manchester-encoded data pulses,
PAGE 29
78Q2120C 10/100BASE-TX Transceiver 10BASE-T Transmitter (Informative) The specifications in the following table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. PARAMETER CONDITION MIN Output return loss Output Impedance Balance 1 MHz < freq < 20 MHz NOM MAX UNIT 15 dB f 29 − 17 log   10  dB Peak Common-mode Output Voltage 50 mV Common-mode rejection 15 Vpk, 10.
PAGE 30
78Q2120C 10/100BASE-TX Transceiver VCC C1 0.1 C2 0.1 GND C3 0.1 GND GND C4 0.1 GND VCC C8 0.01 100 R7 R8 R9 R10 R11 R12 RXCLK RXER RXD3 RXD2 RXD1 RXD0 24 25 19 20 21 22 100 100 100 100 100 100 18 17 MDC MDIO R1 5.1K 6 RESET VCC 7 47 44 45 46 VCC 64 2 1 1) Recommend to leave pins 56 and 56 as NC for 78Q2120C09 device.
PAGE 31
78Q2120C 10/100BASE-TX Transceiver ISOLATION TRANSFORMERS Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated commonmode choke are recommended for exceeding FCC requirements. This table gives the recommended line transformer characteristics: NAME VALUE CONDITION Turns Ratio 1 CT : 1 CT ± 5% Open-Circuit Inductance 350 µH (min) @ 10 mV, 10 kHz Leakage Inductance 0.40 µH (max) @ 1 MHz (min) Inter-Winding Capacitance 25 pF (max) D.C.
PAGE 32
78Q2120C 10/100BASE-TX Transceiver Tr CKIN Tf Tclkper Tclkhi External CKIN Oscillator Characteristics EXTERNAL CKIN OSCILLATOR CHARACTERISTICS PARAMETER CKIN Frequency CKIN Period SYMBOL Absolute Jitter MIN NOM MAX UNIT f See Note 1 25.000 MHz Tclkper See Note 1 40 ns CKIN Duty Cycle Rise / Fall Time CONDITION Tclkhi / Tclkper Tr, Tf Input signaling requirements = CI 45 55 % 4.0 ns 0.1 ns Note 1: IEEE 802.
PAGE 33
78Q2120C 10/100BASE-TX Transceiver PACKAGE PIN DESIGNATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RPTR LEDFDX GND NC GND RXIP RXIN 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 78Q2120C LEDBT ANEGA TECH0 TECH1 TECH2 VCC GND VCC LEDL LEDTX LEDRX LEDCOL LEDBTX INTR CRS COL Page: 33 of 35 © 2009 Teridian Semiconductor Corporation TXD3 TXD0 TXD1 TXD2 TX_ER TX_CLK TX_EN RX_DV RX_CLK RX_ER RXD2 RXD1 RXD0 MDIO MDC RXD3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ISODEF ISO GND CK
PAGE 34
78Q2120C 10/100BASE-TX Transceiver MECHANICAL SPECIFICATIONS 64-LQFP (Top View) 11.7 (0.460) 12.3 (0.484) 11.7 (0.460) + 12.3 (0.484) PIN No. 1 Indicator 9.8 (0.386) 10.2 (0.402) 0.50 (0.0197) Typ. 0.60 (0.024) Typ. Page: 34 of 35 0.14 (0.006) 0.28 (0.011) © 2009 Teridian Semiconductor Corporation 0.00 (0) 0.20 (0.008) 1.40 (0.055) 1.60 (0.063) Rev 1.
PAGE 35
78Q2120C 10/100BASE-TX Transceiver ORDERING INFORMATION PART DESCRIPTION ORDER NUMBER 78Q2120C (Revision 9) 64-pin LQFP 78Q2120C (Revision 9) 64-pin LQFP - Lead Free PACKAGE MARK 78Q2120C09-64CGT 78Q2120C-CGT xxxxxxxxxxx9 78Q2120C09-64CGT/F 78Q2120C-CGT xxxxxxxxxxx9F REVISION HISTORY Rev. # 1.0 1.1 1.2 1.3 Date September 2004 January 2005 August 2005 January 2009 Comments Final Data Sheet release 1. Revised ordering number (added 64) 2.