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78M6612

Single-Phase, Dual-Outlet

Power and Energy Measurement IC

DATA SHEET

DS_6612_001

Rev 2 1

19-5348; Rev 2; 1/12

DESCRIPTION

The Teridian™ 78M6612 is a highly integrated, single-phase,

power and energy measurement and monitoring system-on-

chip (SoC) that includes a 32-bit compute engine (CE), an

MPU core, RTC, and flash. Our Single Converter

Technology

with a 22-bit delta-sigma ADC, four analog

inputs, digital temperature compensation, and precision

voltage reference supports a wide range of single-phase,

dual-outlet power measurement applications with very few

external components.

With measurement technology leveraged from Maxim’s flagship

utility metering ICs, the device offers features including 32 KB

of flash program memory, 2 KB shared RAM, three low-power

modes with internal timer or external event wake-up, two

UARTs, I

C/MICROWIRE® EEPROM I/F, and an in-system

programmable flash. Complete outlet measurement unit (OMU)

and AC power monitor (AC-PMON) firmware is available or can

be preloaded into the IC.

A complete array of ICE and development tools, programming

libraries and reference designs enable rapid development and

certification of power and energy measurement solutions that

meet the most demanding worldwide electricity metering

standards.

MPU

RTC

TIMERS

XIN

XOUT

VREF

TX0

RX0

COM0..3

V3.3A

V3.3

SYS

VBAT

V2.5

VBIAS

SEG0..18

GNDA

GNDD

SEG 24..31/

DIO 4..11

SEG 34..37/

DIO 14..17

ICE

C or µWire

EEPROM

POWER

FAULT

COMPARATOR

SERIAL PORTS

OSC/PLL

CONVERTER

DIO, PULSE

COMPUTE

ENGINE

FLASH

RAM

VOLTAGE REF

REGULATOR

POWER SUPPLY

TERIDIAN

78M6612

TEMP

SENSOR

32 kHz

LIVE

NEUT

PWR MODE

CONTROL

WAKE-UP

BATTERY

ICE_E

GNDD

V3P3D

SEG 32,33,

38/ICE

TX1

RX1

OPTIONAL

OUTLET

OPTIONAL

FEATURES

• Measures Each Outlet of a Duplex Receptacle with

a Single IC

• Provides Complete Energy Measurement and

Communication Protocol Capability in a Single IC

• Intelligent Switch Control Capability

• < 0.5% Wh Accuracy Over 2000:1 Current Range

and Over Temperature

• Exceeds IEC 62053/ANSIC12.20 Standards

• Voltage Reference < 40 ppm/°C

• Four Sensor Inputs – VDD Referenced

• Low Jitter Wh and VARh Pulse Test Outputs

(10 kHz max)

• Pulse Count for Pulse Outputs

• Line Frequency Count for RTC

• Digital Temperature Compensation

• Sag Detection for Phase A and B

• Independent 32-Bit Compute Engine

• 46-64 Hz Line Frequency Range with Same Calibration

• Phase Compensation (±7°)

• Battery Backup for RTC and Battery Monitor

• Three Battery Modes with Wake-Up Timer:

Brownout Mode (48 µA)

LCD Mode (5.7 µA)

Sleep Mode (2.9 µA)

• Energy Display on Main Power Failure

• Wake-Up Timer

• 22-Bit Delta-Sigma ADC

• 8-Bit MPU (80515), 1 Clock Cycle per Instruction

with Integrated ICE for MPU Debug

• RTC with Temperature Compensation

• Auto-Calibration

• Hardware watchdog Timer, Power-Fail Monitor

• LCD Driver (Up to 152 Pixels)

• Up to 18 General-Purpose I/O Pins

• 32 kHz Time Base

• 32 KB Flash with Security

• 2 KB MPU XRAM

• Two UARTs

• Digital I/O Pins Compatible with 5 V Inputs

• 64-Pin LQFP or 68-Pin QFN Package

• RoHS-Compliant (6/6) Lead(Pb)-Free Packages

• Complete Application Firmware Available

Teridian is a trademark and Single Converter Technology is a registered

trademark of Maxim Integrated Products, Inc.

MICROWIRE is a registered trademark of National Semiconductor Corp.

Summary of content (46 pages)

PAGE 1
9-5348; Rev 2; 1/12 78M6612 Single-Phase, Dual-Outlet Power and Energy Measurement IC DATA SHEET DS_6612_001 FEATURES DESCRIPTION The Teridian™ 78M6612 is a highly integrated, single-phase, power and energy measurement and monitoring system-onchip (SoC) that includes a 32-bit compute engine (CE), an MPU core, RTC, and flash.
PAGE 2
78M6612 Data Sheet DS_6612_001 Table of Contents 1 Hardware Description .................................................................................................................... 7 1.1 Hardware Overview................................................................................................................. 7 1.2 Analog Front End (AFE) .......................................................................................................... 8 1.2.1 Input Multiplexer .....................
PAGE 3
DS_6612_001 4.3 4.4 4.5 78M6612 Data Sheet Recommended Operating Conditions .................................................................................... 29 Performance Specifications ................................................................................................... 30 4.4.1 Input Logic Levels ..................................................................................................... 30 4.4.2 Output Logic Levels............................................................
PAGE 4
78M6612 Data Sheet DS_6612_001 Figures Figure 1: IC Functional Block Diagram ..................................................................................................... 6 Figure 2: AFE Block Diagram ................................................................................................................... 8 Figure 3: Connecting an External Load to DIO Pins ............................................................................... 15 Figure 4: Functions Defined by V1 ................
PAGE 5
DS_6612_001 78M6612 Data Sheet Tables Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles....................................................... 8 Table 2: Data/Direction Registers and Internal Resources for DIO Pin Groups ....................................... 14 Table 3: DIO_DIR Control Bit ................................................................................................................. 15 Table 4: Selectable Controls using the DIO_DIR Bits .............................
PAGE 6
78M6612 Data Sheet DS_6612_001 IA VA IB VB ∆Σ ADC CONVERTER VBAT VREF MUX CTRL EQU MUX_ALT CHOP_E MUX_DIV MCK PLL RTCLK (32KHz) DIV ADC CK32 32KHz CKOUT_E CKADC 4.9MHz CK_GEN V2P5 V3P3D CK_2X MUX_SYNC CKCE <4.
PAGE 7
DS_6612_001 78M6612 Data Sheet 1 Hardware Description 1.1 Hardware Overview The Teridian 78M6612 single-chip measurement and monitoring IC integrates all the primary AC measurement and control blocks required to implement a solid-state electricity Power and Energy Measurement function.
PAGE 8
78M6612 Data Sheet 1.2 DS_6612_001 Analog Front End (AFE) The AFE functions as a data acquisition system, controlled by the MPU. It consists of an input multiplexer, a delta-sigma A/D converter, and a voltage reference. The main signals (IA, VA, IB, VB) are sampled and the ADC counts obtained are stored in CE DRAM where they can be accessed by the CE and, if necessary, by the MPU.
PAGE 9
DS_6612_001 1.2.2 78M6612 Data Sheet A/D Converter (ADC) A single delta-sigma A/D converter digitizes the voltage and current inputs to the 78M6612. The resolution of the ADC is configurable to either 21 or 22 bit. At the end of each ADC conversion, the FIR filter output data is stored into the CE RAM location. 1.2.3 FIR Filter The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer.
PAGE 10
78M6612 Data Sheet 1.3 DS_6612_001 Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include: • Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when multiplied with the constant sample time).
PAGE 11
DS_6612_001 1.4 78M6612 Data Sheet 80515 MPU Core The 78M6612 includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 5 MHz (4.9152 MHz) clock results in a processing throughput of 5 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases.
PAGE 12
78M6612 Data Sheet 1.5.3 DS_6612_001 Real-Time Clock (RTC) The RTC is driven directly by the crystal oscillator. The RTC consists of a counter chain and output registers. The counter chain consists of seconds, minutes, hours, day of week, day of month, month, and year. The RTC is not supported in all firmware libraries. Contact Maxim support for more information. 1.5.4 Temperature Sensor The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference.
PAGE 13
DS_6612_001 1.5.6 78M6612 Data Sheet Optical Interface The device includes an interface to implement an IR/optical port on UART1. The pin TX1 is designed to directly drive an external LED for transmitting data on an optical link. The pin RX1 is designed to sense the input from an external photo detector used as the receiver for the optical link. The IR/optical interface is not supported in all firmware libraries. Contact Maxim support for more information. 1.5.
PAGE 14
78M6612 Data Sheet DS_6612_001 Table 2: Data/Direction Registers and Internal Resources for DIO Pin Groups DIO Pin no. (64 LQFP) Pin no.
PAGE 15
DS_6612_001 78M6612 Data Sheet Table 3: DIO_DIR Control Bit DIO_DIR [n] DIO Pin n Function 0 1 Input Output Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (WPULSE = DIO6, VARPULSE = DIO7) using DIO_PW and DIO_PV registers. In this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5 can be configured to implement the EEPROM Interface.
PAGE 16
78M6612 Data Sheet DS_6612_001 Table 4: Selectable Controls using the DIO_DIR Bits DIO_R Value 1.5.
PAGE 17
DS_6612_001 78M6612 Data Sheet 1.5.10 Hardware Watchdog Timer V1 V3P3 V3P3 - 10mV WDT disabled V3P3 400mV Normal operation, WDT enabled VBIAS In addition to the basic watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, watchdog timer (WDT) is included in the device. It uses the crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds.
PAGE 18
78M6612 Data Sheet DS_6612_001 2 Functional Description 2.1 Theory of Operation The energy delivered by a power source into a load can be expressed as: t E = ∫ V (t ) I (t )dt 0 The following formulas apply for wide band mode (true RMS): • P = ∑ (i(t) * v(t)) • • • Q = √(S – P ) S=V*I V = √∑v(t)2 • I = √∑i(t)2 2 2 For actual measurement equations, refer to the applicable 78M6612 Firmware Description Document.
PAGE 19
DS_6612_001 2.2 2.2.1 78M6612 Data Sheet Fault and Reset Behavior Reset Mode When the RESET pin is pulled high, all digital activity stops. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are set to their default states. As long as V1, the input voltage at the power fault block, is greater than VBIAS, the internal 2.5 V regulator continues to provide power to the digital section. Once initiated, the reset mode persists until the reset timer times out.
PAGE 20
78M6612 Data Sheet 2.4 DS_6612_001 CE/MPU Communication Figure 7 shows the functional relationship between the CE and the MPU. The CE is controlled by the MPU via shared registers in the I/O RAM and RAM. The CE outputs two interrupt signals to the MPU to indicate the CE is actively processing data and the CE is updating data to the output region of the RAM.
PAGE 21
DS_6612_001 78M6612 Data Sheet 3 Application Information 3.1 Connection of Sensors (CT, Resistive Shunt) Figure 8, Figure 9, and Figure 10 show how resistive voltage dividers, resistive current shunts, and current transformers are connected to the voltage and current inputs of the 78M6612.
PAGE 22
78M6612 Data Sheet 3.2 DS_6612_001 Connecting 5 V Devices All digital input pins of the 78M6612 are compatible with external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V devices. 3.
PAGE 23
DS_6612_001 3.5 78M6612 Data Sheet Connecting LCDs The 78M6612 has an on-chip LCD controller capable of controlling static or multiplexed LCDs. Figure 11 shows the basic connection for an LCD. 78M6612 LCD segments commons Figure 11: Connecting LCDs The LCD segment pins can be organized in the following groups: • Seventeen pins are dedicated LCD segment pins (SEG0 to SEG13, SEG16 to SEG18). • Four pins are dual-function pins CKTEST/SEG19, E_RXTX/SEG38, E_TCLK/SEG33, and E_RST/SEG32.
PAGE 24
78M6612 Data Sheet 3.7 DS_6612_001 Connecting Three-Wire EEPROMs µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 13 and described below: • • DIO5 connects to both the DI and DO pins of the three-wire device. The CS pin must be connected to a vacant DIO pin of the 78M6618. • • In order to prevent bus contention, a 10 kΩ to resistor is used to separate the DI and DO signals.
PAGE 25
DS_6612_001 3.9 78M6612 Data Sheet UART1 (TX1/RX1) The TX1 and RX1 pins can be used for a regular serial interface (by connecting a RS-232 transceiver for example), or they can be used to directly operate optical components (for example, an infrared diode and phototransistor implementing a FLAG interface). 3.10 Connecting V1 and Reset Pins A voltage divider should be used to establish that V1 is in a safe range (see Figure 15). V1 must be lower than 2.
PAGE 26
78M6612 Data Sheet DS_6612_001 3.11 Connecting the Emulator Port Pins Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection from EMI as illustrated in Figure 17. Production boards should have the ICE_E pin connected to ground. LCD Segments (optional ) V3P3D 62Ω 78M661 2 ICE_E E_RST 6 Ω 2 62 Ω 22p F 22p F 22p F E_RXT E_RXTX X E_TCL E_TCLK K Figure 17: External Components for the Emulator Interface 3.
PAGE 27
DS_6612_001 78M6612 Data Sheet 3.15 Measurement Calibration Once the 78M6612 energy measurement device has been installed in a measurement system, it is typically calibrated. A complete calibration includes the following: • Calibration of the metrology section, i.e. calibration for tolerances of the current sensors, voltage dividers and signal conditioning components as well as of the internal reference voltage (VREF). • Establishment of the reference temperature (Section 3.
PAGE 28
78M6612 Data Sheet DS_6612_001 4 Electrical Specifications 4.1 Absolute Maximum Ratings Table 5 shows the absolute maximum ranges for the device. Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions (Section 4.3) is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PAGE 29
DS_6612_001 4.2 78M6612 Data Sheet Recommended External Components Table 6: Recommended External Components Name From To C1 V3P3A AGND C2 V3P3D CSYS Value Unit Bypass capacitor for 3.3V supply. ≥0.1±20% µF DGND Bypass capacitor for 3.3V output. 0.1±20% µF V3P3SYS DGND Bypass capacitor for V3P3SYS. ≥1.0±30% µF C2P5 V2P5 DGND Bypass capacitor for V2P5. 0.1±20% µF XTAL XIN XOUT 32.768 kHz crystal – electrically similar to ECS .327-12.
PAGE 30
78M6612 Data Sheet 4.4 4.4.1 DS_6612_001 Performance Specifications Input Logic Levels Table 8: Input Logic Levels Parameter Condition Min † Digital high-level input voltage , VIH Typ Max 2 V † Digital low-level input voltage , VIL Input pull-up current, IIL E_RXTX, E_RST, CKTEST Other digital inputs VIN=0V, ICE_E=1 Input pull down current, IIH ICE_E Other digital inputs VIN=V3P3D Unit 0.
PAGE 31
DS_6612_001 4.4.4 78M6612 Data Sheet Battery Monitor Table 11: Power-Fault Comparator Performance Specifications (BME=1) Parameter Condition Load Resistor LSB Value - does not include the 9-bit left shift at CE input. FIR_LEN=0 FIR_LEN=1 Offset Error 4.4.5 Min Typ Max Unit 27 45 63 kΩ -6.0 -2.6 -5.4 -2.3 -72 -4.9 -2.0 µV µV +100 mV Typ Max Unit 6.1 7.
PAGE 32
78M6612 Data Sheet 4.4.7 DS_6612_001 2.5V Voltage Regulator Unless otherwise specified, load = 5 mA. Table 14: 2.5 V Voltage Regulator Performance Specifications Parameter Condition Voltage overhead V3P3-V2P5 Reduce V3P3 until V2P5 drops 200 mV PSSR ∆V2P5/∆V3P3 RESET=0, iload=0 4.4.8 Min Typ Max Unit 440 mV +3 mV/V -3 Low Power Voltage Regulator Unless otherwise specified, V3P3SYS=V3P3A=0.
PAGE 33
DS_6612_001 78M6612 Data Sheet 4.4.10 VREF, VBIAS Unless otherwise specified, VREF_DIS=0. Table 17: VREF, VBIAS Performance Specifications Parameter Condition VREF output voltage, VNOM(25) Ta = 22ºC Min Typ Max Unit 1.193 1.195 1.197 V 50 mV 2.
PAGE 34
78M6612 Data Sheet DS_6612_001 4.4.12 ADC Converter, V3P3A Referenced FIR_LEN=0, VREF_DIS=0, LSB values do not include the 9-bit left shift at CE input.
PAGE 35
DS_6612_001 4.5 4.5.1 78M6612 Data Sheet Timing Specifications RAM and Flash Memory Table 22: RAM and Flash Memory Specifications Parameter CE DRAM wait states Flash Read Pulse Width Flash write cycles Flash data retention Flash data retention Flash byte writes between page or mass erase operations Condition Min CKMPU = 4.9152 MHz CKMPU = 1.
PAGE 36
78M6612 Data Sheet DS_6612_001 5 Packaging 5.1 Pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 E_TCLK/SEG33 E_RST/SEG32 GNDD XOUT TEST XIN GNDD RX1/DIO1 V1 VREF IA IB VB VA V3P3A GNDA 5.1.
PAGE 37
DS_6612_001 5.1.2 78M6612 Data Sheet Package Outline (LQFP 64) 11.7 12.3 11.7 + 12.3 PIN No. 1 Indicator 9.8 10.2 0.60 Typ. 0.50 Typ. 0.00 0.20 0.14 0.28 1.40 1.60 NOTE: Controlling dimensions are in mm.
PAGE 38
78M6612 Data Sheet 5.1.3 DS_6612_001 Recommended PCB Land Pattern for the LQFP-64 Package x y e A G x y e A G Recommended PCB Land Pattern Dimensions Symbol Description Typical Dimension e Lead pitch 0.5 mm x Pad width 0.25 mm y Pad length. See Note. 2.0 mm A 7.75 mm G 9.0 mm Note: The y dimension has been elongated to allow for hand soldering and reworking. Production assembly may allow this dimension to be reduced as long as the G dimension is maintained.
PAGE 39
DS_6612_001 GNDA V3P3A VA IB VB IA VREF V1 RX1/DIO1 XIN GNDD XOUT TEST GNDD E_RST/SEG32 E_TCLK/SEG33 Pinout SEG41/DIO21 GNDD 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 E_RXTX/SEG38 2 50 V2P5 RESET TX1/DIO2 3 49 VBAT TMUXOUT 4 48 RX0 DIO3 5 47 SEG40/DIO20 TX0 6 46 SEG31/DIO11 45 SEG30/DIO10 44 SEG29/DIO9 43 SEG28/DIO8 42 SEG27/DIO7 SEG3 7 V3P3D 8 CKTEST/SEG19 9 V3P3SYS 10 TERIDIAN 78M6612-IM COM3 35 17 18 19 20 21 22 23 24 25 26 27 28 2
PAGE 40
78M6612 Data Sheet 5.2.2 DS_6612_001 Package Outline 0.850 Dimensions (in mm): *) Pin length is nominally 0.4 mm (min. 0.3 mm, max 0.4 mm). **) Exposed pad is internally connected to GNDD.
PAGE 41
DS_6612_001 5.2.3 78M6612 Data Sheet Recommended PCB Land Pattern for the QFN-68 Package Recommended PCB Land Pattern Dimensions Symbol Description Typical Dimension e Lead pitch 0.4 mm x Pad width 0.23 mm y Pad length. See Note 3. 0.8 mm d See Note 1. 6.3 mm A 6.63 mm G 7.2 mm Note 1: Do not place unmasked vias in region denoted by dimension d. Note 2: Soldering of bottom internal pad is not required for proper operation.
PAGE 42
78M6612 Data Sheet DS_6612_001 6 Pin Descriptions 6.1 Power/Ground Pins Table 27: Power/Ground Pins Name Type Circuit GNDA P – Analog ground: This pin should be connected directly to the ground plane. GNDD P – Digital ground: This pin should be connected directly to the ground plane. V3P3A P – Analog power supply: A 3.3V power supply should be connected to this pin, must be the same voltage as V3P3SYS. V3P3SYS P – System 3.3 V supply. This pin should be connected to a 3.
PAGE 43
DS_6612_001 6.
PAGE 44
78M6612 Data Sheet DS_6612_001 7 I/O Equivalent Circuits V3P3D V3P3D V3P3A 110K Digital Input Pin CMOS Input LCD SEG Output Pin LCD Driver GNDD from internal reference VREF Pin GNDA GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D VREF Equivalent Circuit Type 9: VREF LCD Output Equivalent Circuit Type 5: LCD SEG or pin configured as LCD SEG V3P3A V3P3D Digital Input Pin CMOS Input 110K GNDD GNDD Analog Input Pi
PAGE 45
DS_6612_001 78M6612 Data Sheet 8 Ordering Information Part Description (Package, accuracy) Flash Memory Size Packaging Ordering Number Package Marking 78M6612 64-pin LQFP, 0.5% (Lead(Pb)-free) 32KB Bulk 78M6612-IGT/F 78M6612-IGT 78M6612 64-pin LQFP, 0.5% (Lead(Pb)-free) 32KB Tape & Reel 78M6612-IGTR/F 78M6612-IGT 78M6612 64-pin LQFP, 0.5% (Lead(Pb)-free) 32KB *Programmed, Bulk 78M6612-IGT/F/P 78M6612-IGT 78M6612 64-pin LQFP, 0.
PAGE 46
78M6612 Data Sheet DS_6612_001 Revision History REVISION DATE DESCRIPTION 1.0 4/1/2009 First publication. 1.3 5/7/2010 Moved firmware specific information to respective developers manuals. Added Caution to Section 1.4.6: “Caution. If UART1 is being used for full duplex operation, TX interrupts may be inadvertently cleared and thus a TX safety timer is recommended.” Added Caution to Section 1.4.6 about UART0 interrupts. In Section 3.10, changed “I/O RAM register TX1DIS” to “I/O RAM register TX1E”.