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73S8010R

Low Cost Smart Card Interface

Simplifying System Integration™

DATA SHEET

DS_8010R_022 August 2009

DESCRIPTION

The Teridian 73S8010R is a single smart card

interface IC that provides full electrical compliance

with ISO-7816-3 and EMV 4.0 (EMV2000)

specifications.

Interfacing with the host is done through the two-wire

C bus and one interrupt output to inform the

system controller of the card presence and faults.

The card clock signal can be generated by an

on-chip oscillator using an external crystal, or by

connection to a clock signal.

The Teridian 73S8010R incorporates an ISO-7816-3

activation/deactivation sequencer that controls the

card signals. Level-shifters drive the card signals with

the selected card voltage (3 V or 5 V), coming from an

internal Low Drop-Out (LDO) voltage regulator. This

LDO regulator is powered by a dedicated power

supply input, V

. Digital circuitry is separately

With its embedded LDO regulator, the Teridian

73S8010R is a cost-effective solution for any

application where a 5 V (typically -5% +10%) power

supply is available. Hardware support for auxiliary

I/O lines, C4 / C8 contacts is provided.

Emergency card deactivation is initiated upon

card extraction or upon any fault generated by

the protection circuitry. The fault can be a card

over-current, a V

(digital power supply), a V

(regulator power supply), a V

(card power supply)

or an over-heating fault.

The card over-current circuitry is a true current detect

function, as opposed to V

voltage drop detection, as

usually implemented in ICC interface ICs.

The V

voltage fault has a threshold voltage that

can be adjusted with an external resistor or resistor

network. It allows automated card deactivation at a

customized V

voltage threshold value. It can be

used, for instance, to match the system controller

operating voltage range.

APPLICATIONS

• Set-Top-Box Conditional Access and

Pay-per-View

• Point of Sales & Transaction Terminals

• Control Access & Identification

• Multiple card and SAM reader configurations

ADVANTAGES

• Single smart card interface

• IC firmware compatible with TDA8020

• Traditional step-up converter is replaced by

an LDO regulator

 Greatly reduced power dissipation

 Fewer external components are required

 Better noise performance

 High current capability (90 mA supplied to

the card)

• Small format (5x5x0.8 mm) QFN32 package option

• True card over-current detection

FEATURES

• Card Interface

• Complies with ISO-7816-3 and EMV 4.0

• An LDO voltage regulator provides 3 V / 5 V to

the card from an external power supply input

• ISO-7816-3 Activation / Deactivation

sequencer with emergency automated

deactivation on card removal or fault

detected by the protection circuitry

• Protection includes 3 voltage supervisors

that detect voltage drops on V

card and

on power supplies V

and V

• Over-current detection 150 mA max

• 1 card detection input

• Auxiliary I/O lines, for C4 / C8 contact

signals

• Host Interface

• Fast mode, 400 kbps I

C slave bus

• 8 possible devices in parallel

• One control register and one status

• Interrupt output to the host for fault

detection

• Crystal oscillator or host clock, up to 27 MHz

• 6 kV ESD protection on the card interface

• SO28 or QFN32 package

Summary of content (25 pages)

PAGE 1
73S8010R Low Cost Smart Card Interface Simplifying System Integration™ DATA SHEET DS_8010R_022 August 2009 APPLICATIONS • DESCRIPTION The Teridian 73S8010R is a single smart card interface IC that provides full electrical compliance with ISO-7816-3 and EMV 4.0 (EMV2000) specifications. Interfacing with the host is done through the two-wire 2 I C bus and one interrupt output to inform the system controller of the card presence and faults.
PAGE 2
73S8010R Data Sheet DS_8010R_022 FUNCTIONAL DIAGRAM VDD GND VDDF_ADJ [17] 18 [20] 21 VPC [2] 5 [3] 6 [4, 5, 6, 9, 16, 25, 32] 7, 8, 9 NC VPC FAULT [21] 22 [1] 4 VDD VOLTAGE SUPERVISOR VOLTAGE REFERENCE GND VDD FAULT LDO REGULATOR & VOLTAGE SUPERVISORS VCC FAULT [18] 19 SCL Int_Clk [19] 20 SDA R-C OSC.
PAGE 3
DS_8010R_022 73S8010R Data Sheet Table of Contents 1 Pinout ............................................................................................................................................. 5 2 5 Electrical Specifications................................................................................................................ 8 2.1 Absolute Maximum Ratings ..................................................................................................... 8 2.
PAGE 4
73S8010R Data Sheet DS_8010R_022 Figures Figure 1: 73S8010R Block Diagram ......................................................................................................... 2 Figure 2: 73S8010R 32-Pin QFN Pinout .................................................................................................. 5 Figure 3: 73S8010R 28-Pin SO Pinout..................................................................................................... 5 Figure 4: Typical 73S8010R Application Schematic ..
PAGE 5
DS_8010R_022 73S8010R Data Sheet 1 Pinout NC SAD2 SAD1 SAD0 AUX2UC AUX1UC I/OUC NC 32 31 30 29 28 27 26 25 The 73S8010R is supplied as a 32-pin QFN package and as a 28-pin SO package.
PAGE 6
73S8010R Data Sheet DS_8010R_022 Table 1 describes the pin functions for the device. Table 1: 73S8010R Pin Definitions Pin Name Pin (SO28) Pin (QFN32) Type Description I/O 11 8 IO Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. AUX1 13 11 IO AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. AUX2 12 10 IO AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
PAGE 7
DS_8010R_022 Pin Name 73S8010R Data Sheet Pin (SO28) Pin (QFN32) Type Description Microcontroller Interface INT 23 22 O Interrupt output signal (negative assertion) to the processor. A 20 kΩ pull up to VDD is provided internally. SAD0 SAD1 SAD2 1 2 3 29 30 31 I I I Serial device address bits. Digital inputs for address selection that allows for the connection of up to 8 devices in parallel.
PAGE 8
73S8010R Data Sheet DS_8010R_022 2 Electrical Specifications This section provides the following:        2.1 Absolute Maximum Ratings Recommended Operating Conditions Smart Card Interface Requirements Digital Signals Characteristics DC Characteristics I2C Interface Characteristics Voltage / Temperature Fault Detection Circuits Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8010R. Permanent device damage may occur if absolute maximum ratings are exceeded.
PAGE 9
DS_8010R_022 2.3 73S8010R Data Sheet Smart Card Interface Requirements Table 4 lists the 73S8010R Smart Card interface requirements. Table 4: DC Smart Card Interface Requirements Symbol Parameter Condition Min Nom Max Unit Card Power Supply (VCC) Regulator General Conditions: -40 °C < T < 85 °C, 4.75 V < VPC < 5.5 V, 2.7 V < VDD < 5.5 V VCC Card supply voltage including ripple and noise Inactive mode -0.1 – 0.1 V Inactive mode ICC = 1 mA -0.1 – 0.4 V Active mode; ICC < 65 mA; 5 V 4.
PAGE 10
73S8010R Data Sheet Symbol DS_8010R_022 Parameter Condition Min Nom Max Unit Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, AUX2UC. VOH Output level, high (I/O, AUX1, AUX2) IOH = 0 µA 0.9 * VCC – VCC+0.1 V IOH = -40 µA 0.75 * VCC – VCC+0.1 V Output level, high (I/OUC, AUX1UC, AUX2UC) IOH = 0 µA 0.9 * VCC – VDD+0.1 V IOH = -40 µA 0.75 * VCC – VDD+0.
PAGE 11
DS_8010R_022 Symbol 73S8010R Data Sheet Parameter Condition Min Nom Max Unit 0.9 * VCC – VCC V Reset and Clock for card interface, RST, CLK VOH Output level, high IOH = -200 µA VOL Output level, low IOL = 200 µA 0 – 0.3 V VINACT Output voltage when outside of session IOL = 0 – – 0.1 V – – 0.3 V IRST_LIM Output current limit, RST – – 30 mA ICLK_LIM Output current limit, CLK t R, t F Output rise time, fall time δ 2.
PAGE 12
73S8010R Data Sheet 2.6 DS_8010R_022 I2C Interface Characteristics 2 Table 7 lists the I C Interface characteristics. 2 Table 7: I C Characteristics Symbol Parameter Condition Min Nom Max Unit VIL Input low voltage -0.3 – 0.3 * VDD V VIH Input high voltage 0.7 * VDD – VDD+0.3 V VOL Output low voltage – – 0.40 V CIN Pin capacitance – – 10 pF IIN Output high voltage IOH = -1 mA VDD - 0.45 – TF Output fall time CL = 0 to 400 pF 20 + 0.
PAGE 13
DS_8010R_022 73S8010R Data Sheet 3 Applications Information This section provides general usage information for the design and implementation of the 73S8010R. 3.1 Example 73S8010R Schematics Figure 4 shows a typical application schematic for the implementation of the 73S8010R. Note that minor changes may occur to the reference material from time to time and the reader is encouraged to contact Teridian for the latest information AUX2UC_to/from_uC AUX1UC_to.
PAGE 14
73S8010R Data Sheet 3.2 DS_8010R_022 System Controller Interface (I2C Bus) 2 A fast-mode 400 kHz I C bus slave interface is used for controlling the 73S8010R device and reading the status of the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1, and SAD2. This allows up to 8 devices to be connected in parallel. Table 9 lists the device address selections for the SAD2:0 settings.
PAGE 15
DS_8010R_022 73S8010R Data Sheet I2C-bus Write to Control Register 2 The I C-bus Write command to the control register follows the format shown in Figure 5. After the START condition, the master sends a slave address. This address is seven bits long followed by an eighth bit which is an opcode bit (R/W) – a ‘zero’ indicates the master will write data to the control register. After the R/W bit, the ’zero’ ACK bit is sent to the master by the device.
PAGE 16
73S8010R Data Sheet DS_8010R_022 SDA MSB LSB MSB LSB SCL 1-7 START condition ADDRESS bits 8 9 R/W bit ACK bit 9 1-8 DATA bits ACK bit STOP condition Figure 6: I2C Bus Read Protocol SDA Tbuf SCL Thi Tsudat Thdsta Tlow Thddat Tsusto 2 Figure 7: I C Bus Timing Diagram Table 13: I2C Bus Timing Parameters 16 Symbol Parameter Min. Typ. Max. Unit Fsclk Clock frequency – – 400 kHz Tlow Clock low 1.3 – – µs Thi Clock high 0.
PAGE 17
DS_8010R_022 3.3 73S8010R Data Sheet Power Supply and Voltage Supervision The Teridian 73S8010R smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by the digital input 5V/#V. This regulator is able to provide either 3 V or 5 V card voltage from the power supply applied on the VPC pin. Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to interface with the system controller.
PAGE 18
73S8010R Data Sheet 3.4 DS_8010R_022 Card Power Supply The card power supply is provided by the LDO regulator, and controlled by the digital ISO-7816-3 sequencer. Card voltage selection is carried out by bit 2 of the control register. Choice of the VCC capacitor: Depending on the application, the requirements in terms of both the VCC minimum voltage and the transient currents that the interface must be able to provide to the card are different.
PAGE 19
DS_8010R_022 3.7 73S8010R Data Sheet Activation Sequence After Power on Reset, the signal INT is low until the VDD is stable. When VDD has been stable for approximately 10 ms and the signal INT is high, the system controller may read the status register to see if the card is present. If all the status bits are satisfied, the system controller can initiate the activation sequence by writing a '1' to the Start/Stop bit (bit 0) of the control register.
PAGE 20
73S8010R Data Sheet DS_8010R_022 Start/Stop RST CLK IO VCC t1 t1 = > .5 μs t3 = > 0.5 μs t2 t3 t4 t2 = > 7.5 μs t4 = > 0.5 μs Figure 9: Deactivation Sequence 3.9 Interrupt The Interrupt is an active low interrupt.
PAGE 21
DS_8010R_022 73S8010R Data Sheet 3.10 Warm Reset 2 The 73S8010R automatically asserts a warm reset to the card when instructed through bit 1 of the I C Control register (bit Warm Reset). The warm reset length is automatically defined as 42,000 card clock cycles. The Warm Reset bit is automatically reset when the card starts answering or when the card is declared mute. IO Warm Reset (bit 1) RST t3 t2 t1 t1 > 1.
PAGE 22
73S8010R Data Sheet DS_8010R_022 4 Mechanical Drawings 4.1 32-pin QFN 0.85 NOM./ 0.9MAX. 0.00 / 0.005 5 0.20 REF. 2.5 1 2.5 2 3 5 SEATING PLANE TOP VIEW SIDE VIEW 0.35 / 0.45 3.0 / 3.75 CHAMFERED 0.30 0.18 / 0.3 1.5 / 1.875 1 2 3 3.0 / 3.75 0.25 1.5 / 1.875 0.5 0.2 MIN. 0.35 / 0.45 0.5 0.25 BOTTOM VIEW Figure 13: 32-pin QFN Package Dimensions 22 Rev. 1.
PAGE 23
DS_8010R_022 4.2 73S8010R Data Sheet 28-Pin SO .050 TYP. (1.270) .305 (7.747) .285 (7.239) PIN NO. 1 BEVEL .715 (18.161) .695 (17.653) .0115 (0.29) .003 (0.076) .110 (2.790) .092 (2.336) .420 (10.668) .390 (9.906) .016 nom (0.40) .335 (8.509) .320 (8.128) Figure 14: 28-Pin SO Package Dimensions Rev. 1.
PAGE 24
73S8010R Data Sheet DS_8010R_022 5 Ordering Information Table 16 lists the order numbers and packaging marks used to identify 73S8010R products.
PAGE 25
DS_8010R_022 73S8010R Data Sheet Revision History Revision Date Description 1.0 7/1/2004 First publication. 1.1 11/10/2004 Make revisions to all references of “I/O” as it relates to the pins for the smart card and microcontroller interfaces, i.e. IO -> I/O and IOUC -> I/OUC. This is done to insure consistency and follow the designations used in ISO 7816. Remove the MLP pin numbering in the pin description. Correct the clock division table under CARD CLOCK.