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73S8010C

Smart Card Interface

Simplifying System Integration™

DATA SHEET

April 2009

DESCRIPTION

The Teridian 73S8010C is a single smart card

interface IC. It provides full electrical compliance

with ISO-7816-3 and EMV 4.0 specifications.

Interfacing with the host is done through the two-wire

I2C bus. Data exchange with the card is managed

from the system controller using the I/O line (and

eventually the auxiliary I/O lines).

An on-chip oscillator using an external crystal, or

connection to a clock signal coming from the

system controller can generate the card clock

signal.

The 73S8010C IC incorporates an ISO-7816-3

activation/deactivation sequencer that controls the

card signals. Level shifters drive the card signals

with the selected card voltage (3 V or 5 V), coming

from an internal DC-DC converter.

With its high-efficiency DC-DC converter, the

Teridian 73S8010C is a cost-effective solution for

any smart card reader application to be powered

from a single 2.7 V to 3.6 V power supply.

Hardware support for auxiliary I/O lines, C4 / C8

contacts, is provided.

Emergency card deactivation is initiated upon card

extraction or upon any fault generated by the

protection circuitry. The fault can be a VDD (digital

power supply), a VCC (card power supply), a card

over-current, or an over-heating fault.

ADVANTAGES

 Single smart card interface

 The inductor-based DC-DC converter provides

higher current and efficiency than the usual

charge-pump capacitor-based converters

 Ideal for battery-powered applications

 Suitable for high current cards and

SAMs: (100 mA max)

 Power down mode: 2 A typical

 Small Format (5x5mm) 32-QFN package option

FEATURES

 Card Interface:

 Complies with ISO-7816-3 and EMV 4.0

 A DC-DC Converter provides 3V / 5V to the

card from an external power supply input

 High-efficiency converter: > 80% @ V

= 3.3 V,

= 5 V and I

= 65 mA

 Up to 100 mA supplied to the card

 ISO-7816-3 Activation / Deactivation sequencer

with emergency automated deactivation on

card removal or fault detected by the protection

circuitry

 Protection include 2 voltage supervisors that

detect voltage drops on card V

and V

power supplies

 The V

voltage supervisor threshold value

can be externally adjusted

 True over-current detection (150 mA max.)

 1 card detection input

 Auxiliary I/O lines, for C4 / C8 contact signals

 Host Interface:

 Fast mode, 400 kbps I

C slave bus

 8 possible devices in parallel

 One control register and one status register

 Interrupt output to the host for fault

detection

 Crystal oscillator or host clock, up to 27 MHz

 Power Supply:

 V

: 2.7 V to 3.6 V

 6 kV ESD Protection on the card interface

 Package: SO28 or 32QFN

APPLICATIONS

 Set-Top-Boxes, DVD / HDD Recorders:

Conditional Access and Pay-per-View slots

 Point of Sales and Transaction Terminals

 EMV slots in cell phones and PDAs

Summary of content (27 pages)

PAGE 1
73S8010C Smart Card Interface Simplifying System Integration™ DATA SHEET April 2009 DESCRIPTION FEATURES The Teridian 73S8010C is a single smart card interface IC. It provides full electrical compliance with ISO-7816-3 and EMV 4.0 specifications.  Card Interface:  Complies with ISO-7816-3 and EMV 4.0  A DC-DC Converter provides 3V / 5V to the card from an external power supply input  High-efficiency converter: > 80% @ VDD= 3.
PAGE 2
73S8010C Data Sheet DS_8010C_024 FUNCTIONAL DIAGRAM Figure 1: 73S8010C Block Diagram Pin number reference to SO28 Package [Pin number] reference to 32QFN Package 2 Rev. 1.
PAGE 3
DS_8010C_024 73S8010C Data Sheet Table of Contents 1 Pin Description .................................................................................................................................... 5 1.1 Card Interface ............................................................................................................................... 5 1.2 Miscellaneous Inputs and Outputs................................................................................................ 5 1.
PAGE 4
73S8010C Data Sheet DS_8010C_024 Figures Figure 1: 73S8010C Block Diagram ............................................................................................................. 2 Figure 2: I2C Bus Write Protocol ................................................................................................................... 8 Figure 3: I2C Bus Read Protocol ...................................................................................................................
PAGE 5
DS_8010C_024 73S8010C Data Sheet 1 Pin Description 1.1 Card Interface Pin (SO) PIN (QFN) I/O 11 9 Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. AUX1 13 11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. AUX2 12 10 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. RST 16 14 Card reset: provides reset (RST) signal to card. CLK 15 13 Card clock: provides clock (CLK) signal to card.
PAGE 6
73S8010C Data Sheet 1.4 DS_8010C_024 Microcontroller Interface Name PIN (SO) PIN Description (QFN) INT 23 22 Interrupt output (negative assertion): Interrupt output signal to the processor. A 20 kΩ pull up to VDD is provided internally. PWRDN 8 5 Power Down control input: Active High. When Power Down (PD) mode is activated, all internal analog functions are disabled to place the 73S8010C in its lowest power consumption mode. Must be tied to ground when the power down function is not used.
PAGE 7
DS_8010C_024 73S8010C Data Sheet 2 Host Interface (I2C Bus) A fast-mode 400 kHz I2C bus slave interface is used for controlling the device and reading the status of the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0, SAD1, and SAD2. This allows up to 8 devices to be connected in parallel.
PAGE 8
73S8010C Data Sheet DS_8010C_024 ACK bit is sent to the master by the device. The master should send the STOP condition after receiving the ACK bit. Figure 2: I2C Bus Write Protocol 2.2 Host Interface Status Table 3 describes the Host Interface Status Register bits (power-on Reset = 0x04). Table 3: Host Status Register Name Bit Description PRES 0 Set when the card is present; reset when the card is not present.
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DS_8010C_024 73S8010C Data Sheet Figure 3: I2C Bus Read Protocol 2.3 I2C-bus Timing Symbol Parameter Conditions Min. Fsclk Clock frequency Tlow Clock low 1.3 s Thi Clock high 0.6 s Thdsta Hold time START condition 0.6 s Tsudat Data set up time 100 ns Thddat Data hold time Tsusto Set up time STOP condition 0.6 s Tbuf Bus free time between a STOP and START condition 1.3 s 5 Typ. Max.
PAGE 10
73S8010C Data Sheet DS_8010C_024 3 Oscillator The Teridian 73S8010C device has an on-chip oscillator that can generate the smart card clock using an external crystal, connected between the XTALIN and XTALOUT pins, to set the oscillator frequency. When the card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be left unconnected. 4 DC-DC Converter – Card Power Supply An internal DC-DC converter provides the card power supply.
PAGE 11
DS_8010C_024 73S8010C Data Sheet 5 Voltage Supervision Two voltage supervisors constantly check the level of the VDD and VCC voltages. A card deactivation sequence is forced when a fault occurs for any of these voltage supervisors. The digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to interface with the system controller.
PAGE 12
73S8010C Data Sheet DS_8010C_024 PRES INT OFF follows PRES regardless of PWRDN PWRDN during a card session has no effect PWRDN PWRDN has effect when the cardi s deactivated Internal RC OSC ~10ms Start/Stop bit After setting PWRDN = 0, the controller must wait at least 10ms before setting Start/Stop = 1 EMV / ISO deactivation time ~= 100 uS Figure 5: Power Down Mode Operation 7 Over-temperature Monitor A built-in detector monitors die temperature.
PAGE 13
DS_8010C_024 73S8010C Data Sheet 9 Deactivation Sequence Deactivation is initiated either by the system controller resetting the Start/Stop bit, or automatically in the event of hardware faults. Hardware faults are over-current, over-temperature, VDD fault, VCC fault, and card extraction during the session. The following steps and Figure 7 show the deactivation sequence and the timing of the card control signals when the system controller clears the Start/Stop bit: 1. 2. 3. 4.
PAGE 14
73S8010C Data Sheet DS_8010C_024 A power-on-reset (POR) event will reset all of the control and status registers to their default states. A VDD fault event does not reset these registers, but it will signal an interrupt condition and by the action of the timer that creates interval “t1,” will not clear the interrupt until VDD is valid for at least the t1 time. The VDD fault can be considered valid for VDD as low as 1.5 to 1.8 volts. At the lower range of the VDD fault, POR will be asserted.
PAGE 15
DS_8010C_024 73S8010C Data Sheet 13 Typical Application Schematic See NOTE 5 AUX2UC_to/f rom_uC AUX1UC_to.
PAGE 16
73S8010C Data Sheet DS_8010C_024 14 Electrical Specification 14.1 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device. Parameter Rating Supply Voltage VDD -0.5 to 4.0 VDC Input Voltage for Digital Inputs -0.3 to (VDD +0.5) VDC Storage Temperature -60 °C to 150 °C Pin Voltage (except LIN and card interface) -0.3 to (VDD +0.5) VDC Pin Voltage (LIN) -0.3 to 6.0 VDC Pin Voltage (card interface) -0.3 to (VCC + 0.
PAGE 17
DS_8010C_024 73S8010C Data Sheet 14.3 DC Characteristics: Card Interface Symbol Parameter Condition Card Power Supply (VCC) DC-DC Converter General conditions, -40 C < T < 85 C, 2.7 V < VDD < 3.
PAGE 18
73S8010C Data Sheet DS_8010C_024 1011B01 Converter efficiency Converter Efficiency (VCC(VCC 5 V) 5V) 100 95 90 Efficiency [%] 85 80 75 70 2.7V 3.0V 65 3.3V 60 3.6V 55 50 0 20 40 60 80 100 Icc [mA] Figure 12: DC – DC Converter Efficiency (VCC = 5 V) Output current on Vcc at 5 V. Input voltage on VDD at 2.7, 3.0, 3.3 and 3.6 volts. 1011B01 Converter efficiency (VCC 3V) 100 95 90 Efficiency [%] 85 80 75 2.7V 70 3.0V 3.3V (Linear) 65 3.
PAGE 19
DS_8010C_024 Symbol Parameter 73S8010C Data Sheet Condition Min. Typ. Max. Unit Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC. IIL requirements only pertain to I//OUC, AUX1UC, and AUX2UC. IOH = 0 0.9 VCC VCC+ 0.1 V IOH = -40 A 0.75 VCC VCC + 0.1 V IOH = 0 0.9 VDD VDD+ 0.1 V IOH = -40 A 0.75 VDD VDD + 0.1 V 0.3 V 1.8 VCC + 0.
PAGE 20
73S8010C Data Sheet Symbol DS_8010C_024 Parameter Condition Min. IOH = -200 A IOL = 200 A IOL = 0 IOL = 1 mA 0.9 VCC 0 Typ. Max. Unit VCC 0.3 0.1 0.3 30 70 V V V V mA mA 8 ns 100 ns 55 % Max.
PAGE 21
DS_8010C_024 73S8010C Data Sheet 14.6 DC Characteristics: I2C Interface Symbol Parameter Condition Min. Typ. Max. Unit SDA, SCL VIL Input Low Voltage -0.3 0.3* VDD V VIH Input High Voltage 0.7*VDD VDD + 0.3 V VOL Output Low Voltage 0.40 V CIN Pin capacitance 10 pF IIN Output High Voltage TF Output fall time TSP Pulse width of spikes that are suppressed IOL = 3 mA IOH = -1 mA VDD - 0.45 CL = 0 to 400 pF 20 + 0.
PAGE 22
73S8010C Data Sheet DS_8010C_024 15 Mechanical Drawings 15.1 32-pin QFN 0 .8 5 N O M . / 0 .9 M A X . 0 .0 0 / 0 .0 0 5 5 0 .2 0 R E F . 2.5 1 2.5 2 3 5 S E A T IN G PLANE S ID E V IE W TOP VIEW 0.35 / 0.45 3.0 / 3.75 0.18 / 0.3 CHAMFERED 0.30 1.5 / 1.875 1 2 3 3.0 / 3.75 0.25 1.5 / 1.875 0.5 0.2 MIN. 0.35 / 0.45 0.5 0.25 BOTTOM VIEW Figure 14: 32-pin QFN Package Drawing 22 Rev. 1.
PAGE 23
DS_8010C_024 73S8010C Data Sheet 15.2 28-pin SO Figure 15: 28-pin SO Package Drawing Rev. 1.
PAGE 24
73S8010C Data Sheet DS_8010C_024 16 Package Pin Designation Use handling procedures necessary for a static sensitive component. NC SAD2 SAD1 SAD0 AUX2UC AUX1UC I/OUC NC 32 31 30 29 28 27 26 25 16.
PAGE 25
DS_8010C_024 73S8010C Data Sheet 16.2 28-pin SO SAD0 1 28 AUX2UC SAD1 2 27 AUX1UC SAD2 3 26 I/OUC GND 4 25 XTALOUT LIN 5 24 XTALIN VDD 6 23 INT NC 7 22 GND PW RDN 8 21 VDD NC 9 20 SDA PRES 10 19 SCL I/O 11 18 VDDF_ADJ AUX2 12 17 VCC AUX1 13 16 RST GND 14 15 CLK 73S8010C Figure 15: 73S8010C 28-pin SO Pin Out (Top View) Rev. 1.
PAGE 26
73S8010C Data Sheet DS_8010C_024 17 Ordering Information Part Description Order Number Packaging Mark 73S8010C-SO 28-pin Lead-Free SO 73S8010C-IL/F 73S8010C-IL 73S8010C-SO 28-pin Lead-Free SO Tape / Reel 73S8010C-ILR/F 73S8010C-IL 73S8010C-QFN 32-pin Lead-Free QFN 73S8010C-IM/F 73S8010C 73S8010C-IMR/F 73S8010C 73S8010C-QFN 32-pin Lead-Free QFN Tape / Reel 18 Related Documentation The following 73S8010C documents are available from Teridian Semiconductor Corporation: 73S8010C Data Sheet (thi
PAGE 27
DS_8010C_024 73S8010C Data Sheet Revision History Revision Date Description 1.0 6/13/2005 First publication. 1.2 9/21/2005 Changed SDATA hold time. 1.3 12/5/2007 Added ISO and ENV logo, remove leaded package options, replace 32QFN punched with SAWN, update 28SO dimension. 1.4 1/17/2008 Changed dimension of bottom exposed pad on 32QFN mechanical package figure. 1.5 4/3/2009 Removed all references to VPC as VPC must be tied to VDD. © 2009 Teridian Semiconductor Corporation.