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73S8009C

Versatile Power Management

and Smart Card Interface IC

Simplifying System Integration™

DATA SHEET

DS_8009C_025 February 2010

DESCRIPTION

The Teridian 73S8009C is a versatile power

management and single smart card interface circuit

that is ideally suited for smart card reader products

that are battery and/or USB bus-powered. In

addition to its EMV 4.1 and ISO-7816-3 compliant

smart card-to-host interface circuitry; it provides

control, conversion, and regulation of power for a

companion host processor circuit and power for the

smart card. The 73S8009C can operate from a

single 2.7 V to 6.5 V source supply, or a

combination of battery power (4.0 V to 6.5 V) and

USB power (4.4 V to 5.5 V).

The 73S8009C supports 5 V, 3 V, and 1.8 V smart

cards. The smart card signals for RST, CLK, IO,

and auxiliary signals AUX1 and AUX2 are

level-shifted to the selected V

value. Although

the host controller is required to handle the

detailed signal timing for activation and de-

activation under normal conditions, the 73S8009C

blocks any spurious signals on CLK, RST and IO

during power-up (as V

rises) and power-down.

The 73S8009C contains two handshaking signals

for the controller: OFF indicates that a card is

present, and RDY indicates that V

is at an

acceptable value. The 73S8009C will perform

emergency deactivation upon card removal,

voltage faults, or over-current events

The power management circuitry of the 73S8009C

allows operation from a wide range of voltages

from multiple sources. V

is converted by using

an inductive, step-up power converter to the

intermediate voltage, V

. V

is used by linear

voltage regulators and switches to create the

voltages V

and as required, V

. V

is used by

the 73S8009C and is also made available for the

companion controller circuit or other external

circuits. The V

BAT

and V

BUS

pins provide inputs

from alternate power sources as required. An

internal switch in the 73S8009C acts as a

single-pole, double-throw switch that selects either

BAT

or V

BUS

to be connected to V

. When the

voltage on V

BUS

is zero, V

BAT

is connected to V

When voltage is applied to V

BUS

, the switch selects

BUS

as the source for power.

When power is supplied by V

or V

BAT

, the

73S8009C is controlled by the ON_OFF pin in the

manner of a “push-on/push-off” button action. The

OFF_REQ and OFF_ACK signals provide

handshaking and control of the power “off”

function by the controller. A SPST momentary

switch to ground connected to ON_OFF is all that

is required for power control. Alternatively, the

“off” state can be initiated from the host controller

through OFF_ACK. When the 73S8009C is “off,”

the current is less than 1 µA.

When power is supplied via the V

BUS

pin, the

73S8009C is unconditionally in the “power-on”

state regardless of the action of the ON/OFF

switch or OFF_ACK signal. Power supply current

operating from the V

BUS

power when V

is off is

less than 500 µA to conform to USB “SUSPEND”

requirements.

APPLICATIONS

• Handheld PINpad smart card readers for

e-commerce, secure login, e-health, Gov’t ID

and loyalty

• Point of Sales & Transaction Terminals

• General Purpose Smart Card Readers

ADVANTAGES

• Ideally suited to USB bus-powered

applications

 Ideal for combo bus-powered and/or

self-powered systems

 Automatic battery switchover in bus

powered systems

• Very low-power mode (sub-µA) with

push-button ON/OFF switch input with

de-bounce

• Provides 3.3 V / 40 mA power to external

circuitry (host processor or peripheral circuits)

• The inductor-based DC-DC converter provides

higher current and efficiency than usual

charge-pump capacitor-based converters:

 Ideal for battery-powered applications

Summary of content (32 pages)

PAGE 1
73S8009C Versatile Power Management and Smart Card Interface IC DATA SHEET Simplifying System Integration™ DS_8009C_025 February 2010 DESCRIPTION The Teridian 73S8009C is a versatile power management and single smart card interface circuit that is ideally suited for smart card reader products that are battery and/or USB bus-powered. In addition to its EMV 4.
PAGE 2
73S8009C Data Sheet DS_8009C_025 FEATURES • • Smart card Interface: • Complies with ISO-7816-3 and EMV 4.1 and derivative standards • A DC-DC Converter provides 1.8 V/3 V/5 V to the card from a wide range of external power supply inputs • Provides up to 65 mA to the card • ISO-7816-3 Card emergency deactivation sequencer • 2 voltage supervisors detect voltage drops on the VCC (card) and VDD (digital) power supplies • Card over-current detection 150 mA max.
PAGE 3
73S8009C Data Sheet DS_8009C_025 FUNCTIONAL DIAGRAM CS 12 10 VBAT VBUS VDD TEST1 TEST2 30 25 29 23 15 vref VOLTAGE REFERENCE 24 ON_OFF S2 S1 VPC LIN VPC FAULT VCC OK VCC = 5 CMDVCC5 5 VCC = 3 CMDVCC3 32 26 27 VCC FAULT 4 OFF VP bias currents CONTROL LOGIC SWITCH/LDO REGULATOR 17 GND 19 POWER DOWN ON/OFF VCC 8 RDY OFF_REQ OFF_ACK RSTIN CLKIN 11 RESET BUFFER 18 CLOCK BUFFER 16 RST 9 6 CLK 14 PRES 7 13 PRES 1.5MHz R-C OSC.
PAGE 4
73S8009C Data Sheet DS_8009C_025 Table of Contents 1 Pinout ............................................................................................................................................. 6 2 3 Electrical Specifications.............................................................................................................. 10 2.1 Absolute Maximum Ratings ................................................................................................... 10 2.
PAGE 5
DS_8009C_025 73S8009C Data Sheet Figures Figure 1: 73S8009C Block Diagram ......................................................................................................... 3 Figure 2: 73S8009C 32-Pin QFN Pinout .................................................................................................. 6 Figure 3: Typical 73S8009C Application Schematic ............................................................................... 17 Figure 4: 73S8009C Logical Block Diagram .................
PAGE 6
73S8009C Data Sheet DS_8009C_025 1 Pinout OFF GND TEST2 VDD GND LIN VPC VBAT 32 31 30 29 28 27 26 25 The 73S8009C is supplied as a 32-pin QFN package. I/OUC 1 24 ON_OFF AUX1UC 2 23 VBUS AUX2UC 3 22 I/O CMDVCC5 4 21 AUX1 CMDVCC3 5 20 AUX2 RSTIN 6 19 VCC CLKIN 7 18 RST RDY 8 17 GND 9 10 11 12 13 14 15 16 OFF_ACK TEST1 OFF_REQ CS PRES PRES VP CLK TERIDIAN 73S8009C Figure 2: 73S8009C 32-Pin QFN Pinout 6 Rev. 1.
PAGE 7
DS_8009C_025 73S8009C Data Sheet Table 1 describes the pin functions for the device. Table 1: 73S8009C Pin Definitions Pin Name Pin (QFN32) Type Equivalent Circuit Description Card Interface I/O 22 IO Figure 16 Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. AUX1 21 IO Figure 16 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. AUX2 20 IO Figure 16 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
PAGE 8
73S8009C Data Sheet DS_8009C_025 Pin Name Pin (QFN32) VBUS 23 LIN 27 PSI Figure 13 Connection to 10 µH inductor for internal step up converter. Note: inductor must be rated for 400 mA maximum peak current. VP 15 PSO Figure 13 Intermediate output of main converter circuit. Requires an external 4.7 µF low ESR filter capacitor to GND. GND Type Equivalent Circuit Description Alternate power source input from USB connector or hub. 28,31 – Ground.
PAGE 9
DS_8009C_025 Pin Name 73S8009C Data Sheet Pin (QFN32) Type Equivalent Circuit ON_OFF 24 I Figure 11 Power control pin. Connected to normally open SPST switch to ground. Closing switch for duration greater than de-bounce period will turn 73S8009C circuit “on.” If 73S8009C is “on,” closing switch will turn 73S8009C to “off” state after the de-bounce period and OFF_REQ/OFF_ACK handshake. OFF_REQ 11 O Figure 19 Digital output. Request to the host system controller to turn the 73S8009C off.
PAGE 10
73S8009C Data Sheet DS_8009C_025 2 Electrical Specifications This section provides the following:       Absolute maximum ratings Recommended operating conditions Smart card interface requirements Digital signals characteristics Voltage / temperature fault detection circuits Thermal characteristics 2.1 Absolute Maximum Ratings Table 2 lists the maximum operating conditions for the 73S8009C. Permanent device damage may occur if absolute maximum ratings are exceeded.
PAGE 11
DS_8009C_025 2.2 73S8009C Data Sheet Recommended Operating Conditions Function operation should be restricted to the recommended operating conditions specified in Table 3. Table 3: Recommended Operating Conditions Parameter Rating Supply voltage VPC 2.7 to 6.5 VDC Supply Voltage VBUS 4.4 to 5.5 VDC Supply Voltage VBAT 4.0 to 6.5 VDC Ambient operating temperature -40 °C to +85 °C 2.3 Smart Card Interface Requirements Table 4 lists the 73S8009C Smart Card interface requirements.
PAGE 12
73S8009C Data Sheet Vrdy Vcc ready voltage (RDY = 1) VCCF RDY = 0 (VCC voltage supervisor threshold) External filter cap for VPC External filter cap for VP CVPC Cvp CF CVDD Ivpcoff 12 External filter capacitor (VCC to GND) VDD filter capacitor VPC supply current for Vcc=0 DS_8009C_025 5 V operation, Vcc rising 3 V operation, Vcc rising 1.8 V operation, Vcc rising VCC = 5 V CF should be ceramic with low ESR (<100 mΩ). Vpc=5 V, Vcc=0 V (off) 4.6 2.75 1.65 – – – – – – – – 4.6 V V V V 8.0 2.0 0.
PAGE 13
DS_8009C_025 73S8009C Data Sheet Symbol Parameter Condition Min Nom Max Unit Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC, DP, DM. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, AUX2UC – VOH Output level, high (I/O, IOH =0 0.9 * VCC VCC+0.1 V AUX1, AUX2) – 0.75 VCC VOH Output level, high (I/OUC, IOH = -40 µA VCC+0.1 V AUX1UC, AUX2UC) – IOH =0 0.9 VDD VDD+0.1 V – 0.75 V VOL Output level, low (I/O, V +0.
PAGE 14
73S8009C Data Sheet DS_8009C_025 Symbol Parameter Condition Reset and Clock for card interface, RST, CLK VOH Output level, high IOH =-200 µA VOL Output level, low IOL=200 µA VINACT IRST_LIM ICLK_LIM t R, t F δ 2.4 Output voltage when outside of session Output current limit, RST Output current limit, CLK Output rise time, fall time Duty cycle for CLK Min Nom Max Unit 0.9 * VCC 0 – – V V – – VCC 0.15 *VCC 0.
PAGE 15
DS_8009C_025 2.5 73S8009C Data Sheet DC Characteristics Table 6 lists the DC characteristics. Table 6: DC Characteristics Symbol VDD Parameter VDD Supply Voltage IDDEXT VDD Current to External Load IVPC Supply Current VBUSON VBUS detection threshold VBUSIDIS VBUS discharge current Condition 2.7v < VPC < 6.5v, IVDDEXT < 40 mA. Vpc = 2.7V, VCC off, IDD = 0 Vpc = 3.3V, VCC off, IDD = 0 Vpc = 5.0V, VCC off, IDD = 0 OFF mode VDD =3.3 V Min 3.0 Nom 3.3 Max 3.6 Unit V – – 40 mA – – – – 1.
PAGE 16
73S8009C Data Sheet DS_8009C_025 3 Applications Information This section provides general usage information for the design and implementation of the 73S8009C. The documents listed in Related Documentation provide more detailed information. 3.1 Example 73S8009C Schematics Figure 3 shows a typical application schematic for the implementation of the 73S8009C with a main system switch.
PAGE 17
DS_8009C_025 73S8009C Data Sheet VP C See NOTE 2 See NOTE 7 10µH VDD VDD_supply_to_uC See NOTE 8 C3 See NOTE 3 VBAT C6 10µF 0.
PAGE 18
73S8009C Data Sheet 3.2 DS_8009C_025 Power Supply and Converter The power supply and converter circuit takes power from any one of three sources; VPC, VBUS, and VBAT . VPC is specified to range from 2.7 to 6.5 volts and would typically be supplied by a single cell battery with a voltage range of 2.7 to approximately 3.1 volts. VPC is also appropriate for system supplies of 3.3 or 5 volts. VBUS is typically supplied by a connected USB cable and ranges in value from 4.5 to 5.5 volts (6.5 V maximum).
PAGE 19
73S8009C Data Sheet VBAT VBUS DS_8009C_025 ON/OFF Debounce and Latch OFF_REQ 100K + OFF_ACK - VPC 10uH ON 0.1µF OFF 10µF Linear/ DC - DC Converter LIN 3.5VREF VP V1.8ThREF V3.0ThREF V5.0ThREF CS Delay Circuit Analog Mux RDY + CMDVCC# CMDVCC% VCC VCC Regulator PRES PRES I/OUC RSTIN 0.47µF SHUTDOWN Card Supply/ Control Logic OFF Card I/O Buffer and Signal Logic CLKIN AUX1UC AUX2UC GND RST CLK AUX1 AUX2 VDD 3.3V Regulator VP I/O GND GND 0.1µF 0.1µF 4.
PAGE 20
73S8009C Data Sheet 3.4 DS_8009C_025 System Controller Interface Four separate digital inputs and two outputs allow direct control of the card interface from the host:      Pin CS: Chip select control. Pin CMDVCC# and/or CMDVCC%: When low, starts an activation sequence. Pin RSTIN: controls the card RST signal. Pin RDY: Indicates when smart card power supply is stable and ready. Pin OFF: Indicator of card presence and any card fault conditions.
PAGE 21
DS_8009C_025 3.6 73S8009C Data Sheet Activation and De-activation Sequence The host controller is fully responsible for the activation sequencing of the smart card signals CLK, RST, I/O, AUX1 and AUX2. All these signals are held low by the 73S8009C when the card is in the deactivated state. Upon card activation (the fall of CMDVCC (#/%)), all the signals are held low by the 73S8009C until RDY goes high.
PAGE 22
73S8009C Data Sheet DS_8009C_025 CMDVCC RST CLK I/O VCC_ON VCC t1 t2 t3 t4 t5 Figure 6: Deactivation Sequence 3.7 OFF and Fault Detection There are two different cases that the system controller can monitor the OFF signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. Outside a card session: In this condition, CMDVCC (#/%) are always high, OFF is low if the card is not present, and high if the card is present.
PAGE 23
DS_8009C_025 3.8 73S8009C Data Sheet Chip Selection The CS pin allows multiple circuits to operate in parallel, driven from the same host control bus. When CS is high, the pins RSTIN, CMDVCC%, CMDVCC# and CLKIN control the chip as described. The pins I/OUC, AUX1UC, and AUX2UC have 11 kΩ pull-up resistors and operate to transfer data to the smart card via I/O, AUX1, and AUX2 when the smart card is activated. The signals OFF and RDY have 20 kΩ pull-up resistors.
PAGE 24
73S8009C Data Sheet 3.9 DS_8009C_025 I/O Circuitry and Timing The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the activation sequencer turns on the I/O reception state. See the Activation and De-activation Sequence section for more details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset.
PAGE 25
DS_8009C_025 73S8009C Data Sheet The delay between the I/O signals is shown in Figure 10. I/O I/OUC tI/O_HL Delay from I/O to I/OUC: Delay from I/OUC to I/O: tI/O_LH tI/O_HL = 100ns tI/OUC_HL = 100ns tI/OUC_HL tI/OUC_LH tI/O_LH = 15ns tI/OUC_LH = 15ns Figure 10: I/O – I/OUC Delays - Timing Diagram Rev. 1.
PAGE 26
73S8009C Data Sheet DS_8009C_025 4 Equivalent Circuits This section provides illustrations of circuits equivalent to those described in the Pinout section. 24K PIN VPC ESD Figure 11: On_Off Pin VDD Output Disable 20K PIN Data From circuit ESD STRONG NFET Figure 12: Open Drain type – OFF and RDY To Internal circuits PIN ESD Figure 13: Power Input/Output Circuit, VDD, LIN, VPC, VCC, VP 26 Rev. 1.
PAGE 27
DS_8009C_025 73S8009C Data Sheet VCC VERY STRONG PFET ESD From circuit CLK PIN ESD VERY STRONG NFET Figure 14: Smart Card CLK Driver Circuit VCC STRONG PFET ESD From circuit RST PIN ESD STRONG NFET Figure 15: Smart Card RST Driver Circuit Rev. 1.
PAGE 28
73S8009C Data Sheet DS_8009C_025 VCC ESD STRONG PFET RL=11K 400ns DELAY From circuit IO PIN STRONG NFET CMOS To circuit ESD Figure 16: Smart Card IO, AUX1, and AUX2 Interface Circuit VDD ESD STRONG PFET RL=11K 400ns DELAY From circuit UC PIN To circuit CMOS STRONG NFET ESD Figure 17: Smart Card I/OUC, AUX1UC and AUX2UC Interface Circuit 28 Rev. 1.
PAGE 29
DS_8009C_025 73S8009C Data Sheet VDD VERY WEAK PFET Pull-up Disable ESD TTL To circuit PIN ESD Pull-down Enable Note: VERY WEAK NFET Pins CMDVCC%, CMDVCC#, CS have the pull-up enabled. Pins RSTIN, CLKIN, PRES, EXT_RST have the pull-down enabled. Pin OFF_ACK has a 100 kΩ resistor connected to pin OFF_REQ internally.
PAGE 30
73S8009C Data Sheet DS_8009C_025 5 Mechanical Drawings 0.85 NOM./ 0.9MAX. 0.00 / 0.005 5 0.20 REF. 2.5 1 2.5 2 3 5 SEATING PLANE SIDE VIEW TOP VIEW 0.35 / 0.45 3.0 / 3.75 CHAMFERED 0.30 0.18 / 0.3 1.5 / 1.875 1 2 3 3.0 / 3.75 0.25 1.5 / 1.875 0.5 0.2 MIN. 0.35 / 0.45 0.5 0.25 BOTTOM VIEW Figure 20: 32-Pin QFN Package Dimensions 30 Rev. 1.
PAGE 31
DS_8009C_025 73S8009C Data Sheet 6 Ordering Information Table 9 lists the order numbers and packaging marks used to identify 73S8009C products.
PAGE 32
73S8009C Data Sheet DS_8009C_025 Revision History Revision Date Description 1.0 2/15/2007 First publication. 1.1 12/5/2007 Replaced 32QFN punched with SAWN. Updated 32QFN package mark. 1.2 1/21/2008 Changed the dimension of the bottom view 32-pin QFN package. 1.3 8/28/2009 Added Pin Current, LIN to Table 2. Added Section 2.7, Thermal Characteristics. Added a note to the end of Section 3.6. Added Section 4, Equivalent Circuits.