73M1866B/73M1966B MicroDAA™ with PCM Highway DATA SHEET Simplifying System Integration™ DS_1x66B_001 DESCRIPTION The 73M1866B and 73M1966B use the Teridian patented Data Access Arrangement function ® (MicroDAA ) designed exclusively for ForeignExchange-Office (FXO) in Voice-over-IP (VoIP) applications. These devices provide much of the circuitry required to connect PCM formatted voice channels to a PSTN via a two-wire twisted pair interface.
73M1866B/73M1966B Data Sheet DS_1x66B_001 Table of Contents 1 Introduction ................................................................................................................................... 6 2 Pinout ............................................................................................................................................. 8 2.1 73M1906B 20-Pin TSSOP Pinout............................................................................................ 8 2.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 8.5 9 10 11 12 13 Transmit and Receive Levels ................................................................................................ 48 8.5.1 A-Law........................................................................................................................ 48 8.5.2 μ-Law ........................................................................................................................ 48 8.5.3 Transmit and Receive Level Control .....
73M1866B/73M1966B Data Sheet DS_1x66B_001 Figures Figure 1: Simple 73M1x66B Reference Block Diagram ............................................................................ 6 Figure 2: 73M1906B 20-Pin TSSOP Pinout.............................................................................................. 8 Figure 3: 73M1916 20-Pin TSSOP Pinout ................................................................................................ 9 Figure 4: 73M1906B 32-Pin QFN Pinout ......................
DS_1x66B_001 73M1866B/73M1966B Data Sheet Tables Table 1: 73M1906B 20-Pin TSSOP Pin Definitions .................................................................................. 8 Table 2: 73M1916 20-Pin TSSOP Pin Definitions ..................................................................................... 9 Table 3: 73M1906B 32-Pin QFN Pin Definitions ..................................................................................... 10 Table 4: 73M1916 32-Pin QFN Pin Definitions .................
73M1866B/73M1966B Data Sheet DS_1x66B_001 1 Introduction The 73M1966B is a two-device chip set that provides embedded FXO functionality by connecting a PCM interface to a voice-band PSTN. The device set supports ITU-T Recommendation G.711 µ-law and A-law companding, and also a 16-bit linear mode. High-voltage isolation is provided by the physical separation of the Host-Side (73M19106) and Line-Side (73M1916) Devices.
DS_1x66B_001 73M1866B/73M1966B Data Sheet The Line-Side Device (73M1916) consists of: 1. 2. 3. 4. 5. 6. Digital Sigma Delta Modulator Transmit Analog Front End Receive Analog Front End including Sigma Delta Modulator 3 Sinc Filter (Sinc3) On-chip Line Interface Circuit Line-Side Barrier Interface Circuit (LSBI) Received data from a host connected to the PCM bus is interpolated from the sampling frequency of 8 kHz or 16 kHz (for PCM encoded streams) to twice the sampling frequency.
73M1866B/73M1966B Data Sheet DS_1x66B_001 2 Pinout The 73M1906B and the 73M1916 are supplied as 20-pin TSSOP packages and as 32-pin QFN packages. 2.1 73M1906B 20-Pin TSSOP Pinout Figure 2 shows the 73M1906B 20-pin TSSOP pinout. CS 1 20 SCLK VPD 2 19 INT DR 3 18 SDO DX 4 17 SDI FS 5 16 SDIT PCLKO 6 15 RST PCLKI 7 14 VPT VNA/VND 8 13 PRP AOUT 9 12 PRM VPA 10 11 VNT 73M1906B Figure 2: 73M1906B 20-Pin TSSOP Pinout Table 1 describes the pin functions for the device.
DS_1x66B_001 2.2 73M1866B/73M1966B Data Sheet 73M1916 20-Pin TSSOP Pinout Figure 3 shows the 73M1916 20-pin TSSOP pinout. DCI 1 20 DCG RGN 2 19 DCS RGP 3 18 DCD OFH 4 17 TXM VNX 5 16 RXM SCP 6 15 RXP MID 7 14 VPS VPX 8 13 VNS SRE 9 12 ACS SRB 10 11 VBG 73M1916 Figure 3: 73M1916 20-Pin TSSOP Pinout Table 2 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins.
73M1866B/73M1966B Data Sheet 2.3 DS_1x66B_001 73M1906B 32-Pin QFN Pinout GPIO6 DR VPD CS SCLK INT VND GPIO5 32 31 30 29 28 27 26 25 Figure 4 shows the 73M1906B 32-pin QFN pinout.
DS_1x66B_001 Pin Number 17 18 19 20 21 22 23 24 PRM PRP VPT VPD RST SDIT SDI SDO 25 26 27 28 29 30 31 32 Rev. 1.
73M1866B/73M1966B Data Sheet 2.4 DS_1x66B_001 73M1916 32-Pin QFN Pinout GPO GPI VNS/VND RGP RGN DCI DCG DCS 32 31 30 29 28 27 26 25 Figure 5 shows the 73M1916 32-pin QFN pinout. CKO 1 24 DCD OFH 2 23 RST CKI 3 22 TST VNX 4 21 TXM SCP 5 20 SACIN MID 6 19 RXM SCM 7 18 RXP VPX 8 17 16 VNS 13 VNS 15 12 SRB ACS 11 SRE 14 10 BYP VBG 9 RCT 73M1916 VPS Figure 5: 73M1916 32-Pin QFN Pinout Table 4 describes the pin functions for the device.
DS_1x66B_001 73M1866B/73M1966B Data Sheet Pin Number 16 17 18 Pin Name VNS VPS RXP GND PWRO I 19 20 RXM SACIN I I Receive minus – signal input Caller ID mode AC impedance connection 21 22 23 TXM O I I Transmit Minus – transhybrid cancellation output Factory test mode, leave open Resets the control registers to default – weakly pulled high 24 25 26 27 28 29 30 31 32 Rev. 1.
73M1866B/73M1966B Data Sheet 2.5 DS_1x66B_001 73M1866B Pinout RGP RGN DCI DCG DCS 36 35 34 33 32 OFH M20PB 38 37 VNX 39 SCP MID 41 40 VPX 42 Figure 6 shows the 73M1866B 42-pin pinout.
DS_1x66B_001 Pin Number 17 18 19 20 Pin Name Type VND GND O I INT SCLK CS 21 22 23 24 25 26 DR 27 28 29 30 31 32 33 34 35 36 37 VPS 38 39 40 41 42 M20PB 2.
73M1866B/73M1966B Data Sheet DS_1x66B_001 3 Electrical Characteristics and Specifications 3.1 Isolation Barrier Characteristics Table 6 provides the characteristics of the 73M1x66B Isolation Barrier. Table 6: Isolation Barrier Characteristics Parameter Barrier frequency Data transfer rate across the barrier for the sampling rate of 8 kHz Rating 768 kHz 1.536 Mbps When 16 kHz sampling rate is selected, the frequency and data transfer rates are twice those shown above. 3.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 3.2.3 DC Characteristics Table 9 lists the 73M1x66B DC characteristics.
73M1866B/73M1966B Data Sheet 3.3 DS_1x66B_001 Interface Timing Specification There are three interfaces associated with the 73M1x66B: the SPI interface, the PCM highway interface and the line interface. This section provides the timing specification for the SPI interface and the PCM highway interface. 3.3.1 SPI Interface Table 10 lists the characteristics for the SPI interface.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 3.3.
73M1866B/73M1966B Data Sheet DS_1x66B_001 PCLK tifh tifs tpcy FS tird tids tidh DR todh todd todo DX Figure 9: PCM Timing Diagram for Negative Edge Transmit Mode and Positive Edge Receive Mode 3.4 Analog Specifications This section provides the electrical characterizations of the 73M1x66B analog circuitry. 3.4.1 DC Specifications VBG is to be connected to an external bypass capacitor with a minimum value of 0.1 μF. This pin is not intended for any other external use.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 3.4.2 Call Progress Monitor The Call Progress Monitor monitors activities on the line. The audio output contains both transmit and receive data with a configurable level individually set by Register 10h. Figure 10 shows the frequency response of the Call Progress Monitor Filter based upon the characteristics of the device plus the external circuitry as shown. Figure 10: Frequency Response of the Call Progress Monitor Filter C1 0.
73M1866B/73M1966B Data Sheet DS_1x66B_001 Table 15: Call Progress Monitor Specification Parameter AOUT for transmit AOUT transmit THD AOUT for receive AOUT receive THD AOUT output impedance 3.5 Test Condition 1 kHz full swing code (ATX) CMRXG=11 (Mute) Observe AOUT pin CMTXG=00 CMTXG=01 relative to CMTXG=00 CMTXG=10 relative to CMTXG=00 CMTXG=11 (Mute) CMTXG=00 1.0 Vpk, 1 kHz at the line or 0.
DS_1x66B_001 3.6 73M1866B/73M1966B Data Sheet Reference and Regulation Table 17 lists the VBG specifications. VBG should be connected to an external bypass capacitor with a minimum value of 0.1 μF. This pin is not intended for any other external use. The following conditions apply: VPX=5 V; Barrier Powered Mode; Barrier Data Rate across the Barrier=1.5 Mbps; VBG connected to 0.1 μF external cap. Table 17: VBG Specifications Parameter VBG VBG noise VBG PSRR VPS VPS PSRR 3.
73M1866B/73M1966B Data Sheet 3.8 DS_1x66B_001 Transmit Path Table 19 list the transmit path characteristics. A pattern for a sinusoid of 1 kHz, full scale (code word of +/- 32,767) from the 73M1x66B is forced and ACS is measured with R10=174 Ω. Unless stated otherwise, test conditions are: ACZ=0000 (600 Ω termination), THEN=1, ATEN=1, DAA=01, TXBST=0, sample rate=8kHz.
DS_1x66B_001 3.9 73M1866B/73M1966B Data Sheet Receive Path Table 20 lists the receive path characteristics. All test inputs are driven through an AC coupling network shown in Figure 29. The receive bit stream is measured at the DX pin. RXEN=1. Table 20: Receive Path Parameter Differential input resistance Input level Input level Overall sigma-delta ADC modulation gain inclusive of 73M1906B processing Offset voltage Rx gain (See Note 1.
73M1866B/73M1966B Data Sheet DS_1x66B_001 3.10 Transmit Hybrid Cancellation Table 21 lists the transmit hybrid cancellation characteristics. Unless stated otherwise, test conditions are: ACZ[3:0]=0000 (600 Ω termination), THEN=1, ATEN=1, DAA[1:0]=01, TXBST=0. TXM is externally fed back into the 73M1916 to effect cancellation of transmit signal.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 3.12 Detectors This section provides electrical characteristics for the following detectors: • • • • Over-Voltage. Over-Current. Under-Voltage. Over-Load. 3.12.1 Over-Voltage Detector The values in Table 23 were measured between RGP and RGN. Table 23: Over-voltage Detector Parameter Over voltage levels Test Condition OVDTH=0 OVDTH=1 Min 0.52 0.59 Nom 0.6 0.7 Max 0.68 0.77 Unit V V Nom 1.025 Max 1.20 Unit V 3.12.
73M1866B/73M1966B Data Sheet DS_1x66B_001 4 Applications Information This section provides general usage information for the design and implementation of the 73M1x66B. 4.1 Example Schematic of the 73M1966B and 73M1866B Figure 12 shows a typical application schematic for the implementation of the 73M1966B. Figure 13 shows a typical application schematic for the implementation of the 73M1866B.
73M1866B/73M1966B Data Sheet 3 DS_1x66B_001 2 Q5 MMBTA06 R8 52.3K, 1% 1 C37 0.01uF C7 4.7uF, 25V D1 MMSZ4710T1* R9 21K, 1% R6 17.4K, 1% L1 R66 1M, 0805 2 kOhm@100MHz C1 0.022uF, 200V VNS R10 174, 1% C41 C12 0.1uF C38 0.1uF C8 4.7uF R68 1M, 0805 C43 1nF 220pF, 300V C3 0.022uF, 200V C35 + VNS 22 23 24 25 26 27 28 29 30 31 BR1 C45 + C33 3.3uF 0.1uF 2 32 33 34 35 36 37 38 39 40 41 42 Q4 MMBTA92 3 R2 10M C36 3 Q3 MMBTA42 3 1 R12 5.1K 1 C4 C20 1nF C9 0.
73M1866B/73M1966B Data Sheet 4.2 DS_1x66B_001 Bill of Materials Table 27 provides the 73M1x66 bill of materials for the reference schematics provided in Figure 12 and Figure 13.
DS_1x66B_001 4.3 73M1866B/73M1966B Data Sheet Over-Voltage and EMI Protection Over-voltage protection is required to meet worst-case conditions for target countries. UL1950, EN60950, IEC 60950, ITU-T K.20/K.21 and GR-1089-CORE specifications define the protection requirements for many countries. A single design can be implemented to meet all these requirements. Figure 14 shows a recommended protection circuit topology.
73M1866B/73M1966B Data Sheet 4.4 DS_1x66B_001 Isolation Barrier Pulse Transformer The isolation element used by the 73M1x66B is a standard digital pulse transformer. Several vendors supply compatible transformers with up to 6000 V ratings. Since the transformer is the only component crossing the isolation barrier other than EMI capacitors that may be required, it solely determines the isolation between the PSTN and the FXO’s digital interface.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 5 SPI Interface The host accesses the 73M1x66B using an SPI interface to write to control registers and read status registers. The host is the master of the transaction. Four pins orchestrate the communication between the host and the SPI, and a fifth pin is dedicated to support the daisy-chain mode. The signals are as follows: • • • • • SDI SDO SCLK CS SDIT Serial data input driven by the host. Serial data output driven by the 73M1x66B.
73M1866B/73M1966B Data Sheet DS_1x66B_001 CIDin SDI SDO SCLK HOST SCLK CS CS SDI SDO 73M1906B Channel 0 SDITHRU CID=CIDin-1 SDI SCLK CS 73M1906B Channel 1 SDO SDITHRU CID=CIDin-2 ... CID=000 (target) SDI SCLK CS 73M1906B Channel 15 SDO SDITHRU Figure 15: Daisy-Chain Configuration The R/W bit determines whether the host requests a read (1) or a write (0) operation. The second byte of the SPI transaction is the address byte.
DS_1x66B_001 73M1866B/73M1966B Data Sheet CS SCLK SDI CONTROL ADDRESS DATA [7:0] HI-Z SDO DATA [7:0] Figure 17: SPI Read Transaction – 8-bit Mode In 16-bit mode, the first frame of 16 bits contains both the control and address bytes, and the second frame contains the data bytes. Note that the second part of the second frame is irrelevant. Figure 18 and Figure 19 show the write and read transactions in 16-bit mode.
73M1866B/73M1966B Data Sheet • • 36 DS_1x66B_001 In 8-bit mode, if either the control or the address frames do not correspond to a multiple of eight SCLK cycles, the SPI state machine resets and the transaction is aborted. If the data frame is shorter than eight SCLK cycles, the state machine resets and the transaction is aborted. If the data frame is longer than eight SCLK cycles, while not being a multiple of eight cycles, the write/read transaction is performed and the state machine resets.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 6 Control and Status Registers Table 31 shows the 73M1x66B register map of addressable registers. The shaded cells indicate read-only bits and cannot be modified. Reserved bits should be left in their default state. Accessing unspecified registers should be avoided. Each register and bit is described in detail in the following sections.
73M1866B/73M1966B Data Sheet DS_1x66B_001 Throughout this document, type W is read/write, type WO is write only and type R is read only. Registers and bits are defined as 0x16[3:0], where 0x16 is the register address and the numbers in square brackets specify the address bits. The bit order is [msb – lsb] for a field. For example, [3:0] means bits 3 through 0 of a particular field.
DS_1x66B_001 Bit Name LV MASTER MATCH OFH OIDET OLDET OVDET OVDTH PCLKDT PCMEN PCODE PLDM POL7 POL6 POL5 POLL POLVAL PWDN RCS REVHSD REVLSD RGDT RGMON RGTH1/0 RLPNEN RLPNH RNG RPOL RSTLSBI RTS RXBST RXDG RXEN RXG0 RXG1 RXOCEN RXOM SLEEP SLHS SLLS SR SYNL TCS THEN TMEN TPOL TEST TTS TXBST TXDG TXEN UVDET Rev. 1.
73M1866B/73M1966B Data Sheet DS_1x66B_001 While all registers may be read or written to via an SPI operation without error, some registers react differently to read and write operations, as follows: • Read/Write (W) registers change in response to an SPI write transaction and report their correct current value for a read SPI transaction. • Read Only (R) registers do not change in response to an SPI write transaction but report their correct current value for a read SPI transaction.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 7 Hardware Control Functions This section describes the 73M1x66B capabilities with respect to its configuration and hardware pin control. These include features such as Device Revision, Interrupt Management, Power Management, Clock Control, General Purpose Input/Output (GPIO) and control of the Call Progress Monitor. 7.1 Device Revision The 73M1x66B provides the device revision number for the Host-Side Device and the Line-Side Device.
73M1866B/73M1966B Data Sheet 7.3 DS_1x66B_001 Power Management The 73M1x66B supports three modes of power control for the device. Normal mode ENFEH = 0 Sleep mode Power Down The 73M1x66B operates normally. In this mode the Host Side of the Barrier interface is disabled and the line side device is disabled. The Host side continues to operate normally. The device PLL is turned off and PCLK is propagated on the clock tree. The PCM DX and TSC outputs are tri-stated.
DS_1x66B_001 7.5 73M1866B/73M1966B Data Sheet GPIO Registers Three user-defined I/O pins are provided in the 32-pin QFN package of the 73M1966B only. The pins are GPIO7, GPIO6 and GPIO5. GPIO pins are not available on the 20-pin package of the 73M1966B. GPIO pins are not available on the 42-pin package of the 73M1866B. Each pin can be configured independently as either an input or an output by writing to the corresponding I/O Direction (DIR) register.
73M1866B/73M1966B Data Sheet 7.6 DS_1x66B_001 Call Progress Monitor For the purpose of monitoring activities on the line, a Call Progress Monitor is provided in the 73M1x66B. This audio output contains both transmit and receive data with configurable levels. Function Mnemonic CMRXG Register Location 0x10[1:0] Type W Description Receive Path Gain Setting 00 01 10 11 CMTXG 0x10[3:2] W Transmit Path Gain Setting 00 01 10 11 CMVSEL 7.7 0x10[4] W 0 dB (for full swing, AOUT=1.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 8 PCM Highway Interface and Signal Processing The PCM highway is the method by which the 73M1x66B exchanges PCM data with the host or other PCM-enabled devices. The PCM data can be in either 8-bit compressed mode or in 16-bit linear mode. Compression of the received signals from the PSTN line interface is selectable A-law or μ-law, as specified by ITU-T Recommendation G.711. The 73M1x66B is configurable with respect to tuning the clock and time slot relationships.
73M1866B/73M1966B Data Sheet DS_1x66B_001 FS PCLK DX MSB LSB Figure 21: 16-bit Transmission Example Similarly, the 16-bit data sample is received most significant bit first, beginning at the bit slot defined by the RTS and RCS control registers. The reception lasts for 16 consecutive bit slots. SR selects between 8 kHz and 16 kHz sampling rates. However, FS remains constant at 8 kHz.
DS_1x66B_001 8.2 73M1866B/73M1966B Data Sheet PCM Clock Frequencies The 73M1x66B supports the following PCLK input frequencies: • • • • • • • • • • • 256 kHz 512 kHz 768 kHz 1.024 MHz 1.536 MHz 1.544 MHz 2.048 MHz 3.088 MHz 4.096 MHz 6.176 MHz 8.192 MHz The 73M1x66B automatically detects the frequency of PCLK and adjusts its internal PLL parameters accordingly. At startup, the first eight frames are discarded. The next eight frames are used to count the number of PCLK cycles during each frame.
73M1866B/73M1966B Data Sheet 8.5 DS_1x66B_001 Transmit and Receive Levels 8.5.1 A-Law According to the ITU-T Recommendation G.711, A-law assumes +4096 (in sign plus 12 bit) to represent 3.14 dBm. That is, a sinusoid having a peak value of +4095 to correspond to +3.14 dBm or 1.1119 Vrms or 1.5725 Vpk or 3.145 Vpp. Figure 24 shows the mapping implied in the ITU-T Recommendation G.711. Therefore, one least significant bit in 16-bit code is equivalent to: LSB = 1.5725V = 48.
DS_1x66B_001 8.6 73M1866B/73M1966B Data Sheet Transmit Path Signal Processing 8.6.1 General Description In the transmit path, data is first sent by the host DSP through a serial interface to the 73M1x66B then interpolated by an interpolation filter, serialized and transmitted across barrier interface to the Line-Side Device, which is floating relative to the Host-Side Device earth ground.
73M1866B/73M1966B Data Sheet DS_1x66B_001 8.6.3 73M1x66B Transmit Spectrum Figure 28 shows the transmit spectrum observed on the line from dc to 32 kHz for a sample frequency (Fs) of 8 kHz. The transmit signal is band-limited (by default) to Fs/2=4 kHz and is flat (with 0.2 dB ripple) to 3.65 kHz and is marked as Txdb(x) in the figure.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 8.7.2 Total Receive Path Response Figure 29: Overall Frequency Response of the Receive Path Figure 30: Pass-band Response of the Overall Receive Path 8.7.3 Receiver DC Offset Subtraction The 73M1x66B provides a method to improve audio quality by reducing unwanted DC offset from the receiver signal path in A-law or μ-law compression modes. This method requires that a signal path calibration be performed.
73M1866B/73M1966B Data Sheet 8.8 DS_1x66B_001 PCM Control Functions Table 33: PCM Control Functions Function Mnemonic ADJ Register Location 0x22[6] DAA 0x14[6:5] W ENPCLKDT 0x05[4] W LAW 0x23[0] W LIN 0x23[1] W MASTER 0x23[6] W PCLKDT 0x03[4] R PCMEN 0x23[7] W Type Description W Adjacent Time Slot Driver Control Allows LSB of the PCM frame (DX) to be tri-stated during the second half of the clock cycle.
DS_1x66B_001 Function Mnemonic PCODE Register Location 0x23[5:2] 73M1866B/73M1966B Data Sheet Type W Description PCM Clock Code The default state of PCODE out of reset is 0000. In PCM Slave Mode at reset, the device will attempt to automatically detect the correct frequency of PCLK. If the PCLK frequency is different from those listed in the table below or an incorrect PCODE value is written, the PLL will not lock (LOCKDET 0x0D[7] == 0).
73M1866B/73M1966B Data Sheet RXEN 0x16[6] W RXG 0x14[1:0] W RXOCEN 0x17[5] W RXOM 54 0x25[7:0] W RXDG +0.5dB RXDG +0.25dB RXDG +0.125dB Receiver Digital Gain These bits controls the value of the digital gain section of the 73M1x66B receive path. Each bit indicates either a gain or attenuation value. The net value of the gain setting is the linear sum of each attributed value. Reading the RXDG register returns all zeros, regardless of what was written to them.
DS_1x66B_001 73M1866B/73M1966B Data Sheet Function Mnemonic SEL16K Register Location 0x13[0] SR 0x22[7] W TCS 0x22[2:0] W TPOL 0x20[7] W TTS 0x20[6:0] W TXBST 0x14[7] Rev. 1.6 Type W WO Description Sample Rate Mode Configuration Select Configures the 16 kHz mode of operation. See also SR. 0 = 8 kHz sampling rate. (Default) 1 = 16 kHz sampling rate. The 16 kHz mode is enabled by setting SR=1 followed by SEL16K=1. Sampling Rate Mode Enables the 16 kHz mode of operation. See also SEL16K.
73M1866B/73M1966B Data Sheet Examples: 10000000 00100000 00010011 01001000 TXEN 56 0x16[7] WO TXDG +0.5dB TXDG +0.25dB TXDG +0.125dB Transmitter Digital Gain These bits control the value of the digital gain section of the 73M1x66B transmit path. Each bit indicates either a gain or attenuation value. The net value of the gain setting is the linear sum of each attributed value. Reading the TXDG register returns all zeros, regardless of what was written to them.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 8.8.1 Transmit and Receive Level Control Refer to Section 8.5 for information about 73M1x66B levels. 8.8.1.1 Transmit Gain Scaling The first gain stage in the transmit signal path is the digital gain whose value is controlled by writing to Register 0x08 (TXDG). The second gain stages are the analog gains that are controlled by Register 0x14[7] (TXBST) and Register 0x14[6:5] (DAA).
73M1866B/73M1966B Data Sheet TX Level Analog Gain dBm TxBst DAA1 DAA0 -17 0 1 1 -16 0 1 1 -15 0 1 1 -14 0 1 1 -13 0 1 1 -12 0 1 1 -11 0 1 1 -10 0 1 1 -9 0 1 1 -8 0 1 1 -7 0 1 1 -6 0 1 0 -5 0 1 0 -4 0 1 0 -3 0 1 0 -2 1 1 1 -1 0 0 1 0 0 0 1 1 0 0 1 2 1 1 0 3 0 0 0 4 0 0 0 5 1 0 0 6 1 0 0 Note (1) 1 0 0 Note (1) 1 0 0 Note (1) 1 0 0 Note (1) 1 0 0 Note (1) 1 0 0 Note (1) 1 0 0 DS_1x66B_001 dB -8 -8 -8 -8 -8 -8 -8 -8 -8 -8 -8 -4 -4 -4 -4 -2 0 0 0 2 3 3 6 6 6 6 6 6 6 6 Digital Gain TXDG dB 1001_1010 -8.
DS_1x66B_001 73M1866B/73M1966B Data Sheet Table 36 lists the value of Receive Gain for each value of RXG. Table 36: Receive Gain Control RXG1 0x14[1] 0 0 1 1 RXG0 0x14[0] 0 1 0 1 Gain Nom (dB) -6.0 -3.0 0.0 +3.0 The precise values of the digital gain settings are: Bit Gain Gain / Attenuation 7 0.25 -12.04dB 6 0.5 -6.02dB 5 1.5 3.52dB 4 1.25 1.94dB 3 1.125 1.02dB 2 1.0625 0.53dB 0 1 1.015625 1.03125 0.13dB 0.27dB 8.8.1.
73M1866B/73M1966B Data Sheet DS_1x66B_001 9 Barrier Information 9.1 Isolation Barrier The 73M1x66B uses the Teridian MicroDAA proprietary isolation method based upon low-cost pulse transformer coupling. This technique provides several advantages over other methods, including: • • • • Lower BOM cost. Reduced component count. Lower radiated noise (EMI). Improved operation in noisy environments.
DS_1x66B_001 73M1866B/73M1966B Data Sheet Upon power up, the following sequence should be used to ensure barrier synchronization: 1. The 73M1906B starts in Barrier Powered Mode and transmits a preamble to aid the PLL locking of the Line-Side Device. 2. When PLL Lock detect is achieved the Line-Side Device transmits status data to the Host-Side Device. 3. When the Line-Side status Data is detected by the Host-Side Device, the barrier is considered to be in synchronization by the Host-Side Device. 4.
73M1866B/73M1966B Data Sheet Function Mnemonic RSTLSBI Register Location 0x0D[3] SLHS 0x0D[6] R SLLS 0x1E[2] R SYNL 0x03[1] R 62 DS_1x66B_001 Type Description W Reset Line-Side Barrier Interface To reset the Line-Side Barrier Interface, set this bit to 1. 1 = Resets the Line-Side Barrier Interface. The chip sets this bit back to 0 after it has completed resetting the Line-Side Barrier Interface.
DS_1x66B_001 9.6 73M1866B/73M1966B Data Sheet Line-Side Device Operating Modes The architecture of the 73M1x66B is unique in that the isolation barrier device, an inexpensive pulse transformer, is used to provide power and also bidirectional data between the Host-Side Device and the Line-Side Device. When the 73M1x66B is on hook, all the power for the Line-Side Device is provided over the barrier interface.
73M1866B/73M1966B Data Sheet DS_1x66B_001 10 Configurable Direct Access Arrangement (DAA) The 73M1x66B Line-Side Device integrates most of the circuitry to implement a PSTN line interface or DAA that is capable of being globally compliant with a single bill of materials.
DS_1x66B_001 73M1866B/73M1966B Data Sheet The 73M1x66B can: • • Shift the characteristics by setting the turn-on voltage. Enable a current limit of 42 mA. The 73M1x66B meets a wide range of different countries’ requirements under software control. See Section 10.7. There are two operating states for the DC-IV circuits: Hold and Seize.
73M1866B/73M1966B Data Sheet DS_1x66B_001 An example of the use of the Seize state is for Australia, which requires this state for the first 300 ms immediately after going off hook.
DS_1x66B_001 73M1866B/73M1966B Data Sheet Freq Response of IPMF, AZ=01 10 10 9 8 7 F1db( f ⋅ 1000) 6 5 4 3 2 0 1 0 0 0.5 1 1.5 2 0 2.5 3 3.5 4 4.5 f kHz 5 5 Figure 36: Magnitude Response of Impedance Matching Filter, ACZ (3:0)=0010 (ES 203 021-2) 10.4 Billing Tone Rejection Some countries use a large amplitude out-of-band tone to measure call duration and to allow remote central offices to determine the duration of a call for billing purposes.
73M1866B/73M1966B Data Sheet DS_1x66B_001 10.5 Trans-Hybrid Cancellation In order to improve performance, the Trans-hybrid Cancellation option allows a replica of the transmit signal to be created within the 73M1x66B and fed back to the RXM pin via an external circuit at the line interface. With a well matched AC impedance the amount of cancellation achieved is >26 dB. This function can be enabled or disabled. Tx Buf TXM 17.4 kΩ - Rn RXM Rx Buf + Vin - 21 kΩ Rp RXP From the Line Vin+ 52.
DS_1x66B_001 Function Mnemonic ATEN Register Location 0x16[4] DCIV 0x13[7:6] 73M1866B/73M1966B Data Sheet Type W W ENAC 0x12[5] WO ENDC 0x12[6] WO ENFEL 0x12[2] WO Rev. 1.6 Description Active Termination Loop Enable Enables or disables Active Termination Loop. 0 = Disable. (Default) 1 = Enable Active Termination Loop. Note: normal operation requires this bit to be set to always enable a termination circuit.
73M1866B/73M1966B Data Sheet Function Mnemonic ENLVD Register Location 0x12[3] ENNOM 0x12[0] ENSHL IDISPD 0x12[4] 0x13[1] Type Description WO LeV Detection (OVDET, UVDET, OIDET monitors) 0 = Enable LeV detection. (Default) 1 = Disable LeV detection (used in line-powered mode to save power). This bit will be 0 when Line Powered Mode is detected (ENLPW is set in Register 0x02[2]) and set to 1 when an interrupt occurs within the 73M1916.
DS_1x66B_001 Function Mnemonic RLPNH THEN Rev. 1.6 Register Location 0x14[2] 0x15[3] 73M1866B/73M1966B Data Sheet Type W W Description Receive Low Pass Notch 0 = Selects Receive Low Pass Notch (RLPN) at 12 kHz. (Default) 1 = Selects RLPN at 16 kHz. See RLPNEN (Register 0x16[5]) to enable the filter. Enable Transhybrid Circuit The rejection of the transmit signal from the receive signal path. 0 = Transhybrid Circuit disabled. (Default) 1 = Transhybrid Circuit enabled.
73M1866B/73M1966B Data Sheet DS_1x66B_001 10.7 International Register Settings Table for DC and AC Terminations Table 39 lists the recommended ACZ and DCIV register settings for various countries. Other parameters can also be set in addition to the AC and DC termination. These settings along with the reference schematic (see Figure 12) can realize a single design for global usage without country-specific modifications.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 11 Line Sensing and Status The 73M1x66 supports the means to implement several line status functions such as ring detection, Line In Use detection, parallel pickup detection, and line voltage polarity reversals. To support these functions, 73M1x66 is able to measure the line voltage and current characteristics. In conjunction with these measurements, procedures can be implemented in the host to fully support these capabilities in an application. 11.
73M1866B/73M1966B Data Sheet DS_1x66B_001 11.7 Voltage and Current Detection The 73M1x66B is capable of detecting the following circumstances: • • • Under voltage on the line. Over voltage on the line. Over current. These 73M1x66B built-in mechanisms provide protection to both the device itself and the external line circuitry. If enabled, Over Voltage and Over Current detection will cause the 73M1x66B to go on-hook without the intervention of the host.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 11.12 Line Sensing Control Functions These registers contain control information to set up and use the 73M1x66B line sensing functions. Table 40: Line Sensing Control Functions Function Mnemonic CIDM Register Location 0x15[4] RXBST 0x14[3] Type Description W Caller ID Mode 0 = Disable Caller ID Mode. (Default) 1 = Enables Caller ID Mode by coupling the signal from the RGN/RGP pins to the PCM DX pins in the appropriate PCM codec format.
73M1866B/73M1966B Data Sheet Function Mnemonic Register Location Type DS_1x66B_001 Description Auxiliary A/D Converter Status Bits LC 0x1C[7:1] R LV 0x1B[7:1] R Loop Current In DC Path Result of Auxiliary A/D measuring the Loop Current (7-bit resolution, least significant bits only). Note: LC0=1 lsb=1.31/128=~10.23 mV=1.25 mA; magnitude only. The value of the resistor between the rectifier bridge and the DCS pin is assumed to be 8.2 Ω. Example: 0000011 30.7 mV/RE=3.
DS_1x66B_001 Function Mnemonic Register Location 73M1866B/73M1966B Data Sheet Type Description Over-Voltage Detection Control and Status ENOVD 0x15[1] OVDET 0x1E[5] OVDTH 0x13[2] ENOLD 0x15[7] OLDET 0x1E[3] ENOID 0x15[0] OIDET 0x1E[4] Rev. 1.6 WO Enable Over-Voltage Detector On Line-Side Device 0 = Over Voltage Detector not enabled. 1 = Over Voltage Detector enabled (not latched). Over voltage detector is enabled if ENOVD, ENFEL and ENNOM all equal 1.
73M1866B/73M1966B Data Sheet 12 DS_1x66B_001 Loopback and Testing Modes Figure 39 shows the six loop back modes available within the 73M1x66B. 73M1916 73M1906B CTL SPI Interface STA Aux A/D STA Tip Interp. Filter PRP TxD SCP LSBI MSBI DSDM Onchip LIC TBS TxAFE TxA TxData PCMLB RxData PCM Interface DIGLB1 DIGLB2 INTLB1 Decim.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 12.1 Loopback Controls Table 42 describes the registers used for loopback control. Table 42: Loopback Controls Function Mnemonic TMEN DTST Register Location 0x02[7] 0x07[1:0] Type W W Description Test Mode Enable Used to enable the activation of the test loops controlled by the DTST bits (DIGLB1 and INTLB1). 0 = Disables DTST loops. 1 = Enables DTST loops. TMEN has to be set to 1 before the setting of the DTST bits.
73M1866B/73M1966B Data Sheet DS_1x66B_001 13 Performance This section provides an overview of typical performance characteristics measured using 73M1x66B production devices on a Teridian Reference Board. The measurements were made using a Wandel and Goltermann PCM-4 test unit. The tests conform to ITU-T Recommendation G.712 (2001). For more information, see the 73M1966B Performance Characterization. 13.1 Transmit Figure 40 provides performance characteristics for transmit gain tracking.
DS_1x66B_001 73M1866B/73M1966B Data Sheet Figure 41 provides performance characteristics for receive gain variation against frequency. Figure 41: Gain versus Frequency for Digital Input to Analog Output at the Line Figure 42 provides performance characteristics for distortion in the direction of the digital port to analog port. Figure 42: Signal to Total Distortion versus Input Level for Digital Input to Analog Output to the Line Rev. 1.
73M1866B/73M1966B Data Sheet DS_1x66B_001 13.2 Receive Figure 43 provides performance characteristics for receive gain tracking. Figure 43: Variation of Receiver Analog Gain at the Line to the Digital DX Output 82 Rev. 1.
DS_1x66B_001 73M1866B/73M1966B Data Sheet Figure 44 provides performance characteristics for gain variation against frequency. Figure 44: Gain versus Frequency for Analog Input at the Line to the Digital DX Output Figure 45 provides performance characteristics for distortion in the direction of the analog port to digital port. Figure 45: Signal to Total Distortion versus Input Level for Analog at the Line to the Digital DX Output Rev. 1.
73M1866B/73M1966B Data Sheet DS_1x66B_001 Figure 46: Return Loss, @ 80 mA 84 Rev. 1.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 14 Package Layout Figure 47: 20-Pin TSSOP Package Dimensions 0.85 NOM./ 0.9MAX. 5 0.00 / 0.005 2.5 0.20 REF. 1 2.5 2 3 5 SEATING PLANE TOP VIEW SIDE VIEW 0.35 / 0.45 3.0 / 3.75 CHAMFERED 0.30 0.18 / 0.3 1.5 / 1.875 1 2 3 3.0 / 3.75 0.25 1.5 / 1.875 0.5 0.2 MIN. 0.35 / 0.45 0.5 0.25 BOTTOM VIEW Figure 48: 32-Pin QFN Package Dimensions Rev. 1.
73M1866B/73M1966B Data Sheet DS_1x66B_001 Figure 49: 42-Pin QFN Package Dimensions 86 Rev. 1.
DS_1x66B_001 73M1866B/73M1966B Data Sheet 15 Ordering Information Table 43 lists the order numbers and packaging marks used to identify 73M1x66B products.
73M1866B/73M1966B Data Sheet DS_1x66B_001 Revision History Revision Date 1.0 11/7/2007 1.1 1.2 1.3 1.4 5/13/2008 7/30/2008 11/17/2008 7/21/2009 1.5 1.6 10/16/2009 4/2/2010 Description First publication. Replaced Table 16 with a new table. Replaced the schematics in Figure 12 and Figure 13 with new schematics. Moved the steps to enable the calibration of receive DC offset from Section 8.8.3 to the 73M1866B/73M1966B Implementer’s Guide. Corrected the Types (R, W, WO) in Table 32.