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73M1903

Modem Analog Front End

Simplifying System Integration

DATA SHEET

March 2010

DESCRIPTION

The Teridian 73M1903 Analog Front End (AFE) IC

includes fully differential hybrid driver outputs, which

connect to the telephone line interface through a

transformer-based DAA. The receive pins are also

fully differential for maximum flexibility and

performance. This arrangement allows for the

design of a high performance hybrid circuit to

improve signal to noise performance under low

receive level conditions, and compatibility with any

standard transformer intended for PSTN

communications applications.

The device incorporates a programmable sample

rate circuit to support soft modem and DSP based

implementations of all speeds up to V.92 (56 kbps).

The sampling rates supported are from 7.2 kHz to

14.4 kHz by programming pre-scaler NCO and PLL

NCO.

The 73M1903 device incorporates a digital host

interface that is compatible with the serial ports

found on most commercially available DSPs and

processors and exchanges both payload and control

information with the host.

Cost-saving features of the device include an input

reference frequency circuit, which accepts a range

of crystals from 9-27 MHz. It also accepts external

reference clock values between 9-40 MHz

generated by the host processor. In most

applications, this eliminates the need for a dedicated

crystal oscillator and reduces the bill of material

(BOM).

The 73M1903 also supports two analog loop back

and one digital loop back test modes.

Receive

Mux/

Filters

Transmit

Drivers/

Filters

TXAP

TXAN

(HYBRID)

DAA

Controls

RXAP

RXAN

HOOK

Analog

Sigma

Delta

Control

Registers

Ref.

Clocks

Control

Logic

DAC

VBG

Serial

Port

SCLK

SDIN

SDOUT

FSB

Crystal

GPIO

FEATURES

• Up to 56 kbps (V.92) performance

• Programmable sample rates (7.2 - 14.4 kHz)

• Reference clock range of 9-40 MHz

• Crystal frequency range of 9-27 MHz

• Host synchronous serial interface operation

• Pin compatible with 73M2901CL/CE

modems

• Low power modes

• On board line interface drivers

• Fully differential receiver and transmitter

• Drivers for transformer interface

• 3.0 V – 3.6 V operation

• 5 V tolerant I/O

• Industrial temperature range (-40 to +85 °C)

• JATE compliant transmit spectrum

• Package options:

• 32-pin QFN

• 20-pin TSSOP

• RoHS compliant (6/6) lead-free packages

APPLICATIONS

• Set Top Boxes

• Personal Video Recorders (PVR)

• Multifunction Peripherals (MFP)

• Fax Machines

• Internet Appliances

• Game Consoles

• Point of Sale Terminals

• Automatic Teller Machines

• Speaker Phones

• RF Modems

Summary of content (47 pages)

PAGE 1
73M1903 Modem Analog Front End Simplifying System IntegrationTM DATA SHEET March 2010 DESCRIPTION FEATURES The Teridian 73M1903 Analog Front End (AFE) IC includes fully differential hybrid driver outputs, which connect to the telephone line interface through a transformer-based DAA. The receive pins are also fully differential for maximum flexibility and performance.
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73M1903 Data Sheet DS_1903_032 Table of Contents 1 Signal Description ......................................................................................................................... 4 1.1 Serial Interface ........................................................................................................................ 5 2 Control and Status Registers ........................................................................................................ 8 2.1 GPIO ........................
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DS_1903_032 73M1903 Data Sheet Figures Figure 1: Effect of the TYPE (FS mode) pin on FS with SckMode = 0....................................................... 7 Figure 2: Control Frame Position versus SPOS........................................................................................ 7 Figure 3: Serial Port Timing Diagram ....................................................................................................... 9 Figure 4: Analog Block Diagram........................................
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73M1903 Data Sheet DS_1903_032 1 Signal Description The Teridian 73M1903 modem AFE IC is available in a 20-pin TSSOP or 32-pin QFN package with the same pin out. The following table describes the function of each pin. There are two pairs of power supply pins, VPA (analog) and VPD (digital). They should be decoupled separately from the supply source in order to isolate digital noise from the analog circuits internal to the chip.
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DS_1903_032 1.1 73M1903 Data Sheet Serial Interface The serial data port is a bi-directional port that is supported by many DSPs. Although the 73M1903 is a peripheral to the DSP (host controller), the 73M1903 is the master of the serial port. It generates a serial bit clock, Sclk, from a system clock, Sysclk, which is normally an output from an on-chip PLL that is programmed by the user. The serial bit clock is derived by dividing the system clock by 18.
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73M1903 Data Sheet DS_1903_032 The bits transmitted on the SDOUT pin are defined as follows: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 If the Hardware Control bit (bit 0 of register 01h) is set to zero, the 16 bits that are received on the SDIN are defined as follows: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TX15 TX14 TX13 TX12 T
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DS_1903_032 73M1903 Data Sheet 32 Cycles of sclk SCLK FS(mode1) SCLK and FS in mode 1 32 Cycles of sclk SCLK FS(mode0) SCLK and FS in mode 0 Figure 1: Effect of the TYPE (FS mode) pin on FS with SckMode = 0 Figure 2: Control Frame Position versus SPOS Rev. 2.
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73M1903 Data Sheet DS_1903_032 2 Control and Status Registers Table 2 shows the memory map of addressable registers in the 73M1903. Each register and its bits are described in detail in the following sections.
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DS_1903_032 73M1903 Data Sheet SCLK FS(mode1) SDIN TX15 TX14 TX13 TX12 TX11 TX10 SDOUT RX15 RX14 RX13 RX12 RX11 RX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 CTL RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 Data Frame With Early Frame Sync SCLK FS(mode1) SDIN R/W A6 A5 A4 A3 A2 SDOUT zero zero zero zero zero zero A1 A0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 zero zero DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Control Frame With Early Frame Sync SCLK FS(mode0) SDIN
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73M1903 Data Sheet 2.1 DS_1903_032 GPIO The 73M1903 modem AFE device provides 8 user defined I/O pins. Each pin is programmed separately as either an input or an output by a bit in a direction register. If the bit in the direction register is set high, the corresponding pin is an input whose value is read from the GPIO data register. If it is low, the pin will be treated as an output whose value is set by the GPIO data register.
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DS_1903_032 73M1903 Data Sheet Figure 4: Analog Block Diagram Table 3: PLL Loop Filter Settings FL PLLloop Filter Settings 0 R1=32 kΩ,C1=100 pF,C2=2.5 pF 1 R1=16 kΩ, C1=100 pF,C2=2.5 pF 2.2.1 Control Register (CTRL 11): Address 0Bh Reset State 12h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ndvsr6 Ndvsr5 Ndvsr4 Ndvsr3 Ndvsr2 Ndvsr1 Ndvsr0 Ndvsr[6:0] represents the divisor. If Nrst{2:0] =0 this register is ignored. 2.2.
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73M1903 Data Sheet DS_1903_032 2.2.3 Control Register (CTRL 13): Address 0Dh Reset State 48h Bit 7 Bit 6 Bit 5 Bit 4 Xtal1 Xtal0 Reserved Reserved Unused Xtal[1:0] : 00 01 10 11 = Xtal osc. bias current at 120 = Xtal osc. bias current at 180 = Xtal osc. bias current at 270 = Xtal osc. bias current at 450 Bit 3 Bit 2 Bit 1 Bit 0 Nrst2 Nrst1 Nrst0 μA μA μA μA If OSCIN is used as a Clock input, “00” setting should be used to save power(=167 μA at 27.648 MHz).
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DS_1903_032 73M1903 Data Sheet 3 Clock Generation 3.1 Crystal Oscillator and Pre-scaler NCO The crystal oscillator operates over wide choice of crystals (from 9 MHz to 27 MHz) and it is first input to an NCO based pre-scaler (divider) prior to being passed onto an on-chip PLL. The intent of the prescaler is to convert the crystal oscillator frequency, Fxtal, to a convenient frequency to be used as a reference frequency, Fref, for the PLL.
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73M1903 Data Sheet DS_1903_032 Table 5: PLL Power Down Addr. 00h bit 7 ENFE Addr. 0Eh bit 6 PwdnPLL PLL 0 X PLL Power Off 1 0 PLL Power On 1 1 PLL Power Off Table 6: Examples of NCO Settings Fxtal(Mhz)=9.216 Fxtal(Mhz)=24.576 Fxtal(Mhz)=27.0 14 PsSeq(7:0) PsRst =Dnco1 -1 Nnco2 Dnco2 PllSeq(7:0) PllDiv Nnco1 Dnco1 PsDiv Fs (kHz) PllRst =Dnco2 -1 Fvco (Mhz) PPM 7.2 8/125 15 11011010 7 5/96 19 XXX10000 4 33.177600 0 8.0 2.4*8/7*3 =8.22857142858 8.4 9.0 9.6 2.4*10/7*3 =10.
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Fxtal(Mhz)= 25.35 Fxtal(Mhz)=24.000 DS_1903_032 73M1903 Data Sheet 12.8 14.4 7.2 8.0 2.4*8/7*3 =8.22857142858 8.4 9.0 9.6 1/4 1/8 8/125 2/25 2.4*10/7*3 =10.2857142857 2.4*8/7*4 =10.9714285714 11.2 12.0 12.8 2.4*10/7*4 =13.7142857143 14.4 7.2 PsSeq(7:0) PsRst =Dnco1 -1 Nnco2 Dnco2 PllSeq(7:0) PllRst =Dnco2 -1 4 8 15 12 XXXXXXXX XXXXXXXX 11011010 XXXXXX10 0 0 7 1 5/128 5/288 5/108 5/96 25 57 21 19 XXX11010 XXX11010 XXX11010 XXX10000 4 4 4 4 58.982400 66.355200 33.1776 36.
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73M1903 Data Sheet DS_1903_032 Table 8: Clock Generation Register Settings for Fxtal = 24.576 MHz Reg Address Fs (kHz) Ichp Kvco 8h 9h Ah Bh Ch Dh* (μA) [2:0] 7.2 XX 0A 10 0D 02 C1 6 0 8.0 XX 0A 11 0F XX C0 6 1 2.4*8/7*3 0E 68 11 0D 02 C1 =8.22857142858 6 1 8.4 XX 0A 21 0F 0E C3 8 1 9.0 XX 0A 21 10 FE C7 8 1 9.6 XX 0A 22 12 XX C0 8 2 2.4*10/7*3 04 49 23 12 XX C0 =10.2857142857 8 3 2.4*8/7*4 0E 68 23 12 XX C0 =10.9714285714 8 3 11.
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DS_1903_032 73M1903 Data Sheet Table 10: Clock Generation Register Settings for Fxtal = 24.000 MHz Reg Address Ichp (μA) Kvco [2:0] 30 15 1A C4 10 0 2C 31 13 10 C4 10 1 08 72 41 1C 3E C5 12 1 8.4 DA EF 41 19 10 C4 12 1 9.0 08 66 11 0A 1E C4 6 1 9.6 DA EF 42 1C 1E C4 12 2 2.4*10/7*3 =10.2857142857 DA EF 43 1E 7E C6 12 3 2.4*8/7*4 =10.9714285714 3E A9 33 14 76 C6 10 3 11.2 DA EF 53 21 1A C4 14 3 12 08 66 14 0E 14 C4 6 4 12.
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73M1903 Data Sheet DS_1903_032 4 Modem Receiver A differential receive signal applied at the RXAP and RXAN pins or the output signal at TXAP and TXAN pass through a multiplexer, which selects the inputs to the ADC. In normal mode, RXAP/RXAN are selected. In analog loopback mode, TXAP/TXAN are selected. The DC bias for the RXAP/RXAN inputs is supplied from TXAP/TXAN through the external DAA in normal conditions.
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DS_1903_032 73M1903 Data Sheet Figure 6: Overall Receiver Frequency Response Figure 7: Rx Passband Response It is important to keep in mind that the receive signal should not exceed 1.16 Vpk-diff for proper performance for Rxg=11 (0 dB). In particular, if the input level exceeds a value such that one’s density of 3 RBS exceeds 99.5%, sinc filter output will exceed the maximum input range of the decimation filter and consequently the data will be corrupted.
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73M1903 Data Sheet DS_1903_032 Figure 8: RXD Spectrum of 1 kHz Tone Figure 9: RXD Spectrum of 0.5 kHz, 1 kHz, 2 kHz, 3 kHz and 3.5 kHz Tones of Equal Amplitudes 20 Rev. 2.
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DS_1903_032 73M1903 Data Sheet 5 Modem Transmitter The modem transmitter begins with an 48 tap Transmit Interpolation Filter (TIF) that takes in the 16-bit, two’s compliment numbers (TXD) at SDIN pin at Fs=8 kHz rate. It up-samples (interpolates) the data to 16 kHz rate rejecting the images at multiples of 8 kHz that exist in the original TXD data stream and outputs 16-bit, two’s compliment numbers to a digital sigma-delta modulator. The gain of the interpolation filter is 0.640625 (–3.8679 dB) at DC.
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73M1903 Data Sheet 5.1 DS_1903_032 Transmit Levels The 16-bit transmit code word written by the DSP to the Digital Sigma-Delta Modulator (DSDM) (via TIF) has a linear relationship with the analog output signal. So, decreasing a code word by a factor of 0.5 will result in a 0.5 (-6 dB) gain change in the analog output signal.
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DS_1903_032 5.2 73M1903 Data Sheet Transmit Power - dBm To calculate the analog output power, the peak voltage is calculated and the peak to rms ratio (crest factor) must be known. The following formula is used to calculate the output power, in dBm referenced to 600 Ω. Pout (dBm) = 10 * log [ ( Vout (V) / cf )2 / ( 0.001 * 600 ) ] The following example demonstrates the calculation of the analog output power given a 1.2 kHz FSK tone (sine wave) with a peak code word value of 11,878 sent out by the DSP.
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73M1903 Data Sheet 5.4 DS_1903_032 Control Register (CTRL2): Address 01h Reset State 00h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMEN DIGLB ANALB INTLB CkoutEn RXPULL SPOS HC TMEN 1 = Enable test modes. DIGLB 1 = Tie the serial bit stream from the digital transmit filter output to the digital receive filter input. DIGITAL LOOPBACK ANALB 1 = Tie the analog output of the transmitter to the analog input of the receiver.
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DS_1903_032 6 73M1903 Data Sheet Test Modes There are two loop back test modes that affect the configuration of the analog front end. The internal loop back mode connects the serial bit stream generated by the analog receiver to the input of the analog transmitter. This loop back mode is similar to a remote analog loop back mode and can be used to evaluate the operation of the analog circuits. When using this loop back mode, the TXAN/TXAP pins should not be externally coupled to the RXAP/RXAN pins.
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73M1903 Data Sheet DS_1903_032 8 Electrical Specifications 8.1 Absolute Maximum Ratings Operation above maximum rating may permanently damage the device. Parameter Rating Supply Voltage -0.5 V to +4.0 V Pin Input Voltage (except OSCIN) -0.5 V to 6.0 V Pin Input Voltage (OSCIN) -0.5 V to VDD + 0.5 V 8.2 Recommended Operating Conditions Parameter Rating Supply Voltage (VDD) with respect to VSS 3.0 V to 3.6 V Oscillator Frequency 24.
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DS_1903_032 8.3 73M1903 Data Sheet Digital Specifications 8.3.1 DC Characteristics Parameter Symbol Conditions Min Nom Max Unit Input Low Voltage VIL -0.5 0.2 * VDD V Input High Voltage (Except OSCIN) VIH1 0.7 VDD 5.5 V Input High Voltage OSCIN VIH2 0.7 VDD VDD + 5.5 V Output Low Voltage (Except OSCOUT, FS, SCLK, SDOUT) VOL IOL = 4 mA 0.45 V Output Low Voltage OSCOUT VOLOSC IOL = 3.0 mA 0.7 V Output Low Voltage FS,SCLK,SDOUT VOL IOL = 1 mA 0.
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73M1903 Data Sheet DS_1903_032 8.3.2 AC Timing Table 14: Serial I/F Timing Parameter SCLK Period (Tsclk) (Fs=8 kHz) Min – SCLK to FS Delay (td1) – mode1 – 1/2.
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DS_1903_032 8.4 73M1903 Data Sheet Analog Specifications 8.4.1 DC Specifications VREF should be connected to an external bypass capacitor with a minimum value of 0.1 μF. This pin is not intended for any other external use. Table 15: Reference Voltage Specifications Parameter Test Condition VREF VDD= 3.0 V - 3.6 V. VREF Noise 300Hz-3.3 kHz VREF PSRR 300Hz-30 kHz Min Nom Max 1.36 Units V -86 -80 40* dBm600 dB 8.4.
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73M1903 Data Sheet 8.5 DS_1903_032 Performance 8.5.1 Receiver Table 17: Receiver Performance Specifications Parameter Input Impedance Receive Gain Boost Test Conditions Measured at RXAP/N relative to VREF RXPULL=HI Rxgain = 1; 1 kHz; RXAP/N=0.116 Vpk-diff Gain Measured relative to Rxgain=0 RXGAIN=1 for Fs=8 kHz RXGAIN =1 for Fs=12 kHz RXGAIN =1 for Fs=14.4 kHz 17.0 16.2 15.7 18.5 17.4 17.2 64 70 5.8 8.8 11.8 -0.
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DS_1903_032 73M1903 Data Sheet 8.5.2 Transmitter Table 18: Transmitter Performance Specifications Parameter DAC gain (Transmit Path Gain) Test Condition Min Code word of ± 32,767 @1 kHz; TXBST0=0; TXBST1=0 Nom Max Units µv/bit 70 DC offset –Differential Across TXAP and TXAN for Mode DAC input = 0 -100 100 mV DC offset -Common Mode Average of TXAP and TXAN for DAC input = 0; relative to VREF -80 80 mV TXBST0 Gain Code word of ± 32,767 @1 kHz; relative to TXBST0=0; TXBST1=0 1.
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73M1903 Data Sheet DS_1903_032 Parameter Test Condition TXAP/N Output Impedance Differentially (TXDIS=1) TXDIS=1 Measure impedance differentially between TXAP and TXAN. TXAP/N Common Output Offset (TXDIS=1) TXDIS=1 Short TXAP and TXAN. Measure the voltage respect to Vbg. Min Nom Max 160 -20 0 Units kΩ 20 mV Note: TXBST0 and DTMFBS are assumed to have setting 0’s unless they are specified otherwise. 32 Rev. 2.
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DS_1903_032 73M1903 Data Sheet 9 Pinouts SDOUT GPIO7 GPIO6 SDIN SckMode TYPE N/C VPD 32 31 30 29 28 27 26 25 32-Pin QFN Pinout VND 1 24 GPIO5 VPD 2 23 GPIO4 GPIO0 3 22 VND GPIO1 4 21 N/C GPIO2 5 20 VPPLL GPIO3 6 19 OSCIN FS 7 18 OSCOUT SCLK 8 17 VNPLL 9 10 11 12 13 14 15 16 VPA TXAN TXAP VREF RXAN RXAP VNA TERIDIAN 73M1903 RST 9.1 Figure 12: 32-Pin QFN Pinout Table 19: 32-Pin QFN Pin Definitions Rev. 2.
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73M1903 Data Sheet 9.
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DS_1903_032 73M1903 Data Sheet 10 73M1903 Schematic and Bill of Material RESET RESET\ R17 38.3K, 1% R48 210, 1% VCCA SCLK FS\ R49 1 R22 SDI + C7 0.1uF 10uF F1 2 C22 220pF, 250V 1 U2 TLP627 C13 - 38.3K, 1% R23 61.9K, 1% NLV32T-4R7 E1 TISP4350T3BJR Bourns Thy ristor 210, 1% + L1 R9 63K C19 BR1 HD04 TIP L2 NLV32T-4R7 RING 27MHz or other SY SCLK 2 3 C11 0.1uF MF-R015/600 Bourns PTC f use 3 73M1903-20VT U1 VCCD C20 220pF, 3kV 4 R2 20K 4 3.3uF C3 0.15uF C21 0.
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73M1903 Data Sheet DS_1903_032 Table 21: Bill of Materials Item Qty Reference Part Sources 1 1 BR1 400 V, 500 mA Bridge Rectifier Diodes, Inc, On Semi 2 1 C3 0.15 µF 25 V Panasonic, AVX, TDK 3 1 C4 2.2 nF 25 V Panasonic, AVX, TDK 4 1 C7 10 µF 6.3 V Panasonic, AVX, TDK 5 1 C9 3.3 µF 6.3 V Panasonic, AVX, TDK 6 4 C10,C11,C13,C21 0.1 µF 25 V Panasonic, AVX, TDK 7 1 C19 0.
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DS_1903_032 73M1903 Data Sheet 11 Mechanical Specifications 11.1 32-Pin QFN Mechanical Drawings Dimensions in mm. 0.85 NOM./ 0.9MAX. 0.00 / 0.005 0.20 REF. 5 2.5 1 2.5 2 3 5 SEATING PLANE SIDE VIEW TOP VIEW 0.35 / 0.45 3.0 / 3.75 CHAMFERED 0.30 0.18 / 0.3 1.5 / 1.875 1 2 3 3.0 / 3.75 0.25 1.5 / 1.875 0.5 0.2 MIN. 0.35 / 0.45 0.5 0.25 BOTTOM VIEW Figure 15: 32-Pin QFN Mechanical Specifications Rev. 2.
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73M1903 Data Sheet DS_1903_032 11.2 20-Pin TSSOP Mechanical Drawings Dimensions in mm. Figure 16: 20-Pin TSSOP Mechanical Specifications 38 Rev. 2.
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DS_1903_032 73M1903 Data Sheet 12 Ordering Information Table 22: Ordering Information Part Description Order Number 73M1903 32-Lead QFN Lead Free 73M1903-IM/F 73M1903-M 73M1903 32-Lead QFN, Tape and Reel, Lead Free 73M1903-IMR/F 73M1903-M 73M1903 20-Lead TSSOP Lead Free 73M1903-IVT/F 73M190IVT 73M1903-IVTR/F 73M190IVT 73M1903 20-Lead TSSOP, Tape and Reel, Lead Free Rev. 2.
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73M1903 Data Sheet DS_1903_032 Appendix A – 73M1903 DAA Resistor Calculation Guide The following procedure is used to approximate the component values for the DAA. The optimal values will be somewhat different due to the effects of the reactive components in the DAA (this is a DC approximation). Simulations with the reactive components accurately modeled will yield optimal values. The procedures for calculating the component values in the DAA are as follows. First set up R1.
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DS_1903_032 73M1903 Data Sheet 100 K R3 1 Rwtot 600 1200 where Rwtot RW Rohswitch R2 100 K R3 2 .Rbead Use 1% resistors for R1, R2, and R3. To select the value for C1, make the zero at around 10 Hz. 1 10 . . 2 π 100 K .C1 1 C1 . . 2 π 100 K .10 C1 0.15 uF The blocking cap Cblock should also have the same frequency response, but due to the low impedance, its value will be much higher, usually requiring a polarized cap.
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73M1903 Data Sheet DS_1903_032 Appendix B – Crystal Oscillator The crystal oscillator is designed to operate over wide choice of crystals (from 9 MHz to 27 MHz). The crystal oscillator output is input to an NCO based pre-scaler (divider) prior to being passed onto an onchip PLL. The intent of the pre-scaler is to convert the crystal oscillator frequency, Fxtal, to a convenient frequency to be used as a reference frequency, Fref, for the PLL.
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DS_1903_032 73M1903 Data Sheet Example 2: Fxtal = 18.432 MHz, Fref = 2.304 MHz. Pdvsr = Integer [Fxtal/Fref] = 8 = 8h; Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 18.432/2.304 = 8/1; Pseq = {x,x,x,x,x,x,x,x} = xxh Example 3: Fxtal = 24.576 MHz, fref = 2.4576 MHz. Pdvsr = Integer [ Fxtal/Fref] = 10 = Ah; Prst[2:0] = 1- 1 = 0 from Fref/Fxtal = 24.576/2.
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73M1903 Data Sheet DS_1903_032 Example 2: Fs = 8.0 kHz or Fvco = 2 x 2304 x 8 kHz =36.864 MHz, Fref = 2.304 MHz. Ndvsr = Integer [Fvco/Fref] = 16 = 10h; Nrst= 1-1 = 0 from Fvco/Fref = 16/1; Nseq = {x,x,x,x,x,x,x,x} = xxh. Example 3: Fs = 9.6 kHz or Fvco = 2 x 2304 x 9.6 kHz =44.2368 MHz, Fref = 2.4576 MHz. Ndvsr = Integer [Fvco/Fref] = 18 = 16h; Nrst= 1-1 = 0 from Fvco/Fref = 18/1; Nseq = {x,x,x,x,x,x,x,x} = xxh.
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DS_1903_032 73M1903 Data Sheet where Nnco1 and Nnco2 must be < or equal to 8. The ratio, Nnco1/Dnco1 = 1/7, is used to form a divide ratio for the NCO in prescaler and Nnco2/Dnco2 = 1/18 for the NCO in the PLL. Prescaler NCO: From Nnco1/Dnco1 = 1/7, Pdvsr = Integer [ Dnco1/Nnco1 ] = 7; Prst[2:0] = Nnco1 – 1 = 0; this means NO fractional divide. It always does ÷7. Thus Pseq becomes “don’t care” and is ignored. Pseq = {x,x,x,x,x,x,x,x} = xxh.
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73M1903 Data Sheet DS_1903_032 Example 3: Crystal Frequency = 27 MHz; Desired Sampling Rate, Fs = 7.2 kHz Step 1. First compute the required VCO frequency, Fvco, corresponding to Fs = 2.4 kHz x 3 = 7.2 kHz. Fvco = 2 x 2304 x Fs = 2 x 2304 x 2.4 kHz x 3 = 33.1776 MHz. Step 2. Express the required VCO frequency divided by the Crystal Frequency as a ratio of two integers. This is initially given by: = Fvco / Fxtal 2 • 2304 • 2.4kHz • 3 27 MHz .
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DS_1903_032 73M1903 Data Sheet Revision History Rev. # Date Comments 1.0 4/16/2004 First publication. 1.1 12/13/2004 Minor format modification. 1.2 7/15/2005 Company logo change and minor format modification. 1.4 9/14/2006 Corrected QFN pin-out drawing. 1.5 5/23/2007 Added 20-VT package information. 1.6 12/14/2007 Changed 32-QFN from punched to SAWN. Removed the leaded package option. 1.7 1/17/2008 Changed the bottom view package dimension for 32-QFN package. 2.