Simplifying System IntegrationTM 73M1866B/73M1966B Implementer’s Guide March 26, 2010 Rev. 1.
73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 © 2010 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration and MicroPHY are trademarks of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners.
UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Table of Contents 1 Introduction ......................................................................................................................................... 4 1.1 Procedure Conventions ................................................................................................................ 4 1.2 Read-Modify-Write Procedure ......................................................................................................
73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 1 Introduction ® This guide describes how to use the 73M1866B and 73M1966B MicroDAA FXO for Voice-over-IP (VoIP) applications. The guide provides application-specific detail that is not found in the 73M1866B/73M1966B Data Sheet. The guide also includes suggested algorithms that can be followed by users who are developing their own software.
UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide 2 Hardware Requirements 2.1 Reset The reset pin of the 73M1x66B is active low. Following the power-up of the device and the reset pin being de-asserted, the 73M1x66B SPI interface is ready for communicating with the host. Though not explicitly required, it is recommended that the PCM clock and FS be running and stable before reset is de-asserted on the 73M1x66B device. 2.
73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 3 Device Configuration and Initialization 3.1 Host-Side Device (73M1906B) Configuration The Host-side device configuration and initialization includes the following steps: 1. Reset and Disable Interrupts 2. PCLK Clock Recovery and PLL 3. Call Progress Monitor Reset 4. PCM Interface Configuration 3.1.
UG_1x66B_016 3.1.2 73M1866B/73M1966B Implementer’s Guide PCLK Clock Recovery and PLL Lock Detection The 73M1x66B requires that the PLL be locked (to a stable PCLK and FS) to allow access to the line side device. The 73M1x66B does not require the PLL to be locked (nor a stable PCLK and FS) to access the host side device through the SPI interface. It is recommended that the PCLK and FS be stable before releasing the 73M1x66B from reset.
73M1866B/73M1966B Implementer’s Guide 3.1.3 UG_1x66B_016 Call Progress Monitor Reset If used in 16 kHz mode, the call progress monitor (CPM) circuit must be re-initialized by cycling the SLEEP bit.
UG_1x66B_016 3.1.4 73M1866B/73M1966B Implementer’s Guide PCM Interface Configuration The PCM Highway Interface is described in Section 8 of the 73M1866B/73M1966B Data Sheet. The PCM Highway Clock and Frame Sync signals must be stable and running at legal values for the 73M1x66B device to operate properly. After the device has locked to PCLK and FS the user must configure the PCM interface for the specific system it resides on.
73M1866B/73M1966B Implementer’s Guide 3.2 UG_1x66B_016 Line-Side Device (73M1916) Configuration The Line-side device setup includes the following procedures: 1. Barrier Synchronization Recovery 2. Receiver DC Offset Calibration 3. Initial Line State Configuration 3.2.1 Barrier Synchronization Recovery Before the Line-side device can be initialized, the barrier must be in sync and error free. The barrier is designed to power up the line-side device and come into sync automatically upon PLL lock.
UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide CNT == 3? CNT == 2? SLEEP = 1 MASTER=1 PCODE=0 Wait 20 ms READ RG03,RG0D CNT == 1? CNT++ Barrier Sync Yes SYNL == 0? RSTLSBI=1 No Wait 200 ms SLEEP = 0 Wait 10 ms Yes MASTER=0 PCODE=0 LOKDET==0? No Yes SLHS == 1? No Restore Register Settings End The temporary variables defined in this procedure are: CNT1 = Resync Counter. Initial value = 0 Begin : BARRIER CHECK 1. Read RG03. 2. If SYNL == 0 goto RESYNC. 3. Read RG0D. 4.
73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 Begin : RESYNC 1. IF CNT1 !=1 goto 8 2. Write RSTLSBI = 1 (RG0D = xxxx_1xxx). 3. Wait 20 ms. 4. READ RGO3,RG0D 5. Goto BARRIER CHECK 6. IF CNT1 !=2 goto 15 7. Write PCODE=0 MASTER = 1 (RG023 = x100_00xx). 8. Wait 10 ms. 9. Write PCODE=0 MASTER = 0 (RG023 = x000_00xx). 10. Wait 20 ms. 11. READ RGO3,RG0D 12. Goto BARRIER CHECK. 13. IF CNT1 !=3 20 14. Write SLEEP = 1 (RG0F = xx1x_xxxx). 15. Wait 200 ms. 16. Write SLEEP = 0 (RG0F = xx0x_xxxx). 17. Wait 10 ms.
UG_1x66B_016 3.2.2 73M1866B/73M1966B Implementer’s Guide Receiver DC Offset Calibration The effect of residual DC offset caused by the external components to the 73M1x66B can be reduced by a simple procedure in which the magnitude of this DC offset is measured and subtracted from each sample received from the PSTN. This calibration is intended to be performed once after power-on/reset and is done only after the PLL is locked and the barrier is synchronized.
73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 Receiver DC Offset Calibration OFH == 0? No Exit with error Yes ENDC = ENVLD = ENDT = 0 ENAC = ENFEL = 1 THEN = 1 ENUVD = 0 TXEN = ATEN = 0 RXOCEN = 1 Wait 1 sec RXOCEN = 0 OFFSET = RXMON[7:0] OFFSET += 0x08 RXMON[7:0] = OFFSET Exit 14 Rev. 1.
UG_1x66B_016 3.2.3 73M1866B/73M1966B Implementer’s Guide Initial Line State Configuration The default condition of the device is to be on hook after reset and startup.
73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 Initial Line State Configuration ENAPOL = 1 ENSYNL = 1 ENFEL = 1 OFH = ENDC = ENAC = ENSHL = ENLVD = ENDT = ENNOM = 0 ILM = RSVD = PLMD = OVDTH = IDISPD = b0 = 0 DCIV[1:0] = VAL1 THEN = 1 ENOLD = DISNTR = CHPSEN = CIDM = ENUVD = ENOVD = ENOID = 0 TXEN = RXEN = ATEN = 1 RLPNEN = 0 ACZ[3:0] = VAL2 RG17 = 0x00 End 16 Rev. 1.
UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide 4 On-Hook Procedures The on-hook procedures described in this section include: • CID Mode • Off-Hook Request • Ring Detection and Line Voltage Reversal • Line-in-use and Loss of Battery Feed 4.1 CID Mode It is possible (while on hook) to allow the RGP/RGN input, which is AC coupled to the line through high voltage capacitors, to be transmitted on the PCM bus. This allows the host to listen for Caller ID information without going off hook.
73M1866B/73M1966B Implementer’s Guide 4.2 UG_1x66B_016 Off-Hook Request The registers used in the off-hook request procedure are: TXDG -12 TXDG -6 TXDG +3.5 TXDG +2 VAL3 TXDG +1 TXDG +0.5 TXDG +0.25 TXDG +0.125 RXDG -12 RXDG -6 RXDG +3.5 RXDG +2 VAL4 RXDG +1 RXDG +0.5 RXDG +0.25 RXDG +0.
UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Off-Hook Request RXBST =0 CHPSEN = CIDM = 0 ENDC = ENFEL = 1 DCIV[1:0] = VAL1 ACZ[3:0] = VAL2 THEN =1 ENNOM =0 TXEN = RXEN = ATEN =1 Wait for line to settle (~ 350 ms) OFH = 1 If sieze state ENAC =0 Else ENAC =1 ENAC = 1 ENOM = 1 End Rev. 1.
73M1866B/73M1966B Implementer’s Guide 4.3 UG_1x66B_016 Ring Detection and Line Voltage Reversal When the 73M1966 is in on-hook mode, and when the ring detect interrupt is enabled (ENRGDT), a ring signal can be detected. Figure 3 shows the possible scenarios that can be encountered on the line. The threshold voltage for detecting the ring signal is programmable in the 73M1x66B (RGTH[1:0]).
UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide The registers used for Ring Detection and Line Voltage Reversal are: 0x05 Write ENGPIO7 ENGPIO6 ENGPIO5 ENPCLKDT ENAPOL X X X X X ENDET ENSYNL ENRGDT X X 1 0x0E Write FRCVCO X Res Res Res Res Res X X X X X 0x03 Write GPIO7 X GPIO6 GPIO5 PCLKDT RGMON DET X X X X X RGTH1 RGTH0 Threshold SYNL X RGDT ? 1 Set the ring detect threshold voltage (Threshold) in the RGTH[1:0] bits in Register 0x0E.
73M1866B/73M1966B Implementer’s Guide 4.4 UG_1x66B_016 Line-in-use and Loss of Battery Feed When the FXO line is in the on-hook mode, the driver monitors the voltage on the line (typically 48 V in the US) at regular intervals. A loss of battery voltage or a line-in-use event can affect the value of the line voltage. The loss of battery voltage results from disconnecting the phone line or a central office failure. In this case, the line voltage falls to zero volts after a time constant.
UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide 5 Off-Hook Procedures The off-hook procedures described in this section include: • Barrier Synch Loss • On-hook Request • Parallel Pickup Event Detection 5.1 Barrier Synch Loss When in an off-hook state the host must be ready to act in case of a barrier failure. The host should attempt to put the device in an on-hook state and then reset the PLL and barrier so they can resync. The on-hook request procedure is described in Section 5.2.
73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 6 Interrupt Processing During the course of operation the 73M1x66 can be expected to generate interrupts when errors or other events occur that require immediate action. Each interrupt source corresponds to a bit in register 0x03. This section will cover each interrupt and the appropriate actions to process it.
UG_1x66B_016 6.2 73M1866B/73M1966B Implementer’s Guide PCLKDT Interrupt The triggering of the PCLKDT interrupt indicates that the device has detected a PCLK error. When found, it can be assumed that there is a problem with the PCLK. If the error is temporary, the error can be cleared by resetting the PLL. If the error is due to an external clock failure this error will not clear.
73M1866B/73M1966B Implementer’s Guide 6.4 UG_1x66B_016 SYNL Interrupt The triggering of the SYNL interrupt indicates that the device has detected a failure in the barrier between the line and host side device. When found, it can be assumed that there is a problem with the barrier. This failure is usually a problem with the PLL operation, therefore, the recommended way to deal with this interrupt is to reset the device PLL.
UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide 7 Register Summary Address Bit 7 (hex) TMEN 0x02 GPIO7 0x03 DIR7 0x04 ENGPIO7 0x05 0x 06 0x07 0x08 0x09 0x0D 0x0E 0x0F 0x10 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 Rev. 1.
73M1866B/73M1966B Implementer’s Guide UG_1x66B_016 8 Related Documentation The following 73M1x66B documents are available from Teridian Semiconductor Corporation: 73M1866B/73M1966B Data Sheet 73M1866B/73M1966B Demo Board User Manual 73M1866B/73M1966B GUI User Guide 73M1866B/73M1966B Layout Guidelines 73M1x66 Worldwide Design Guide 73M1866B/73M1966B Programming Guidelines 73M1866B/73M1966B Reference Driver User Guide 9 Contact Information For more information about Teridian Semiconductor products or to ch
UG_1x66B_016 73M1866B/73M1966B Implementer’s Guide Revision History Revision Date 1.0 5/21/2009 First publication. 1.1 8/5/2009 Removed the CHPSEN bit. Made RG15 bit 5 “Reserved”. Re-wrote the Barrier Synchronization Recovery procedure. Miscellaneous editorial changes. 1.2 8/20/2009 In Section 3.2.1, changed “SYNL == 0” in the flowchart to “SYNL == 1”. 1.3 3/26/2010 In Section 3.1.3, deleted “The recommended procedure is to toggle SLEEP once before checking LOKDET for the first time.
