Simplifying System IntegrationTM 73M1822/73M1922 Implementer’s Guide August 27, 2009 Rev. 1.
73M1822/73M1922 Implementer’s Guide UG_1x22_052 © 2009 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration and MicroPHY are trademarks of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners.
UG_1x22_052 73M1822/73M1922 Implementer’s Guide Table of Contents 1 2 3 4 5 6 Introduction ................................................................................................................................... 4 1.1 Procedure Conventions ............................................................................................................ 4 1.2 Read-Modify-Write Procedure ..................................................................................................
73M1822/73M1922 Implementer’s Guide UG_1x22_052 1 Introduction ® This guide describes how to use the 73M1822 and 73M1922 MicroDAA for voice band modem applications. The guide provides application-specific detail that is not found in the 73M1822/73M1922 Data Sheet. The guide also includes suggested algorithms that can be followed by users who are developing their own software. The 73M1922 and 73M1822 will be collectively referred to as the 73M1x22 in this document. 1.
UG_1x22_052 73M1822/73M1922 Implementer’s Guide 2 Hardware Requirements 2.1 Reset The 73M1x22 can be initialized to a default state by pulling the RST pin low for 100 ns or longer. The device will be ready within 100 μs after the removal of reset pulse. The M/S pin is used to provide reset in the 73M1822 and 72M1902 20-pin TSSOP packaged parts. The reset signal is also bi-directional and edge triggered, so either a low-to-high or high-to-low transition will generate a reset.
73M1822/73M1922 Implementer’s Guide UG_1x22_052 3 Device Configuration and Initialization 3.1 Host-Side Device (73M1902) Configuration The Host-side device configuration and initialization includes the following steps: 1. 2. 3. 4. Reset First Interrupt MAFE Interface Configuration Clock and Sample Rate Management 3.1.1 Reset Upon reset, the device will power up in the default state. See the 73M1822/73M1922 Data Sheet for exact conditions of the default device state upon reset.
UG_1x22_052 73M1822/73M1922 Implementer’s Guide 3.1.3 MAFE Interface Configuration R/W Write Write ADDR 07 0x01 DYSEN 0x02 TMEN 06 05 NSLAVE[2:0] 04 03 MSIDEN 02 MSID ENLPW 01 SCK32 SPOS 00 HC The MAFE interface must be properly configured by the user before the user can properly access the device. The device is powered up out of reset in a default state that may not match the final desired MAFE interface operating mode.
73M1822/73M1922 Implementer’s Guide 3.2 UG_1x22_052 Line-Side Device (73M1912) Configuration The Line-side device setup includes the following procedures: 1. Barrier Synchronization 2. Initial Line State Configuration 3.2.1 Barrier Synchronization Before the Line-side device can be initialized, the barrier must be in sync and error free. The barrier is designed to power up the line side device and come into sync automatically upon PLL lock.
UG_1x22_052 73M1822/73M1922 Implementer’s Guide CNT == 2? Wait 20 ms READ RG03,RG0D CNT == 1? CNT++ Barrier Sync Yes SLEEP = 1 SYNL == 1? CHNGFS=1 No Wait 10 ms Yes LOKDET==0? No SLEEP = 0 Yes SLHS == 1? No Restore Register Settings End The temporary variables defined in this procedure are: CNT1 = Resync Counter. Initial value = 0 Begin : BARRIER CHECK 1. Read RG03. 2. If SYNL == 0 goto RESYNC. 3. Read RG0D. 4. If LOKDET == 0 goto RESYNC. 5. If SLHS == 1 goto RESYNC. 6.
73M1822/73M1922 Implementer’s Guide UG_1x22_052 Begin : RESYNC 1. IF CNT1 !=1 goto 8 2. Write CHNGFS = 1 (RG0D = xxxx_1xxx). 3. Wait 20 ms. 4. READ RGO3,RG0D 5. Goto BARRIER CHECK 6. IF CNT1 !=2 goto 15 7. Write SLEEP = 1 (RG0F = xx1x_xxxx). 8. Wait 10 ms. 9. Write SLEEP = 0 (RG0F = xx0x_xxxx). 10. Wait 10 ms. 11. READ RGO3,RG0D 12. Goto BARRIER CHECK 13. Resync Failed. Report to user and reset or power down entire device. End 10 Rev. 1.
UG_1x22_052 73M1822/73M1922 Implementer’s Guide 3.2.2 Initial Line State Configuration The default condition of the device is to be on hook after reset and startup.
73M1822/73M1922 Implementer’s Guide UG_1x22_052 Initial Line State Configuration ENAPOL = 1 ENSYNL = 1 ENFEL = 1 OFH = ENDC = ENAC = ENSHL = ENLVD = ENDT = ENNOM = 0 ILM = RSVD = PLMD = OVDTH = IDISPD = 0 DCIV[1:0] = VAL1 THEN = 1 ENOLD = DISNTR = CHPSEN = CIDM = ENUVD = ENOVD = ENOID = 0 TXEN = RXEN = ATEN = 1 RLPNEN = 0 FSCTR[3:0] = VAL3 RG17[4:3]= VAL2 End 12 Rev. 1.
UG_1x22_052 73M1822/73M1922 Implementer’s Guide 4 On-Hook Procedures The on-hook procedures described in this section include: • • • • CID Mode Off-Hook Request Ring Detection and Line Voltage Reversal Line-in-use and Loss of Battery Feed 4.1 CID Mode It is possible (while on hook) to allow the RGP/RGN input, which is AC coupled to the line through high voltage capacitors, to be transmitted on the MAFE interface. This allows the host to listen for Caller ID information without going off hook.
73M1822/73M1922 Implementer’s Guide 4.
UG_1x22_052 73M1822/73M1922 Implementer’s Guide Off-hook Request RXBST =0 CHPSEN = CIDM = 0 ENDC = ENFEL = 1 DCIV[1:0] = VAL1 ACZ[3:0] = VAL2 THEN =1 ENNOM =0 TXEN = RXEN = ATEN =1 Wait for line to settle (~ 350 ms) OFH = 1 If sieze state ENAC =0 Else ENAC =1 ENAC = 1 ENOM = 1 End Rev. 1.
73M1822/73M1922 Implementer’s Guide 4.3 UG_1x22_052 Ring Detection and Line Voltage Reversal When the 73M1922 is in on-hook mode, and when the ring detect interrupt is enabled (ENRGDT), a ring signal can be detected. Figure 1 shows the possible scenarios that can be encountered on the line. The threshold voltage for detecting the ring signal is programmable in the 73M1x22 (RGTH[1:0]).
UG_1x22_052 73M1822/73M1922 Implementer’s Guide If the line voltage does not exceed the threshold within the 25 ms period, RGMON becomes de-asserted, as illustrated by “6” and “9” in Figure 1. Upon the first reception of the first RGDT interrupt, if no other ring interrupt was received during a sufficiently long period then it can be assumed that a Line Polarity Reversal has occurred.
73M1822/73M1922 Implementer’s Guide UG_1x22_052 Begin @ ring_timer expires @ ring_timer expires 1. If (ring_last - ring_first) < 150 ms Polarity Reversal Event 2. Else Ring Burst a. ring_duration = ring_last – ring_first TRUE b. ring_frequency – 2* ring_count / ring_duration) If(ring_last – ring_first) < 150ms End Polarity Reversal RING_BURST End 18 Rev. 1.
UG_1x22_052 4.4 73M1822/73M1922 Implementer’s Guide Line-in-use and Loss of Battery Feed When the FXO line is in the on-hook mode, the driver monitors the voltage on the line (typically 48 V in the US) at regular intervals. A loss of battery voltage or a line-in-use event can affect the value of the line voltage. The loss of battery voltage results from disconnecting the phone line or a central office failure. In this case, the line voltage falls to zero volts after a time constant.
73M1822/73M1922 Implementer’s Guide UG_1x22_052 5 Off-Hook Procedures The off-hook procedures described in this section include: • • • Barrier Synch Loss On-hook Request Parallel Pickup Event Detection 5.1 Barrier Synch Loss When in an off hook state the host must be ready to act in case of a barrier failure. The host should attempt to put the device in an on-hook state and then reset the PLL and barrier so they can resync. The on-hook request procedure is described in Section 5.2.
UG_1x22_052 73M1822/73M1922 Implementer’s Guide 6 Interrupt Processing During the course of operation the 73M1x22 can be expected to generate interrupts when errors or other events occur that require immediate action. Each interrupt source corresponds to a bit in register 0x03. This section will cover each interrupt and the appropriate actions to process it.
73M1822/73M1922 Implementer’s Guide 6.2 UG_1x22_052 DET Interrupt The triggering of the DET interrupt indicates that the device has detected one of several line condition errors. When found, it can be assumed that there is a problem with the line status. The general corrective action is for the line side device to go on hook. These interrupts are only valid when the device is in an off hook condition.
UG_1x22_052 6.4 73M1822/73M1922 Implementer’s Guide RGDT and RGMON Interrupts The triggering of an RGDT or RGMON interrupt indicates that the device has detected an AC signal on the line greater than the threshold programmed through the RGTH register.
73M1822/73M1922 Implementer’s Guide UG_1x22_052 7 Register Summary Address Default (hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 01 00h/9Ch DSYEN NSLAVE2 NSLAVE1 NSLAVE0 MSIDEN MSID SCK32 Reserved 02 00h TMEN Reserved Reserved Reserved Reserved ENLPW SPOS HC 03 F0h GPIO7 GPIO6 GPIO5 GPIO4 RGMON DET SYNL RGDT 04 F7h DIR7 DIR6 DIR5 DIR4 05 0Bh ENGPIO7 ENGPIO6 ENGPIO5 ENGPIO4 ENAPOL ENDET ENSYNL ENRGDT 06 00h POL7 POL6 POL5 POL4 Reserved R
UG_1x22_052 73M1822/73M1922 Implementer’s Guide 8 Related Documentation The following 73M1x22 documents are available from Teridian Semiconductor Corporation: 73M1822/73M1922 Data Sheet 73M1822/73M1922 Demo Board User Manual 73M1822/73M1922 GUI User Guide 73M1822/73M1922 Layout Guidelines 73M1x22 Worldwide Design Guide 73M1822/73M1922 Programming Guidelines 73M1822/73M1922 Reference Driver User Guide 9 Contact Information For more information about Teridian Semiconductor products or to check the availabi
73M1822/73M1922 Implementer’s Guide UG_1x22_052 Revision History Revision 1.0 26 Date 8/27/2009 Description First publication. Rev. 1.
