71M6543F/71M6543G Energy Meter ICs GENERAL DESCRIPTION FEATURES The 71M6543F/71M6543G are 4th-generation polyphase metering systems-on-chips (SoCs) with a 5MHz 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver.
71M6543F/71M6543G Data Sheet Table of Contents 1 2 3 2 Introduction ....................................................................................................................................... 10 Hardware Description ....................................................................................................................... 11 2.1 Hardware Overview ................................................................................................................... 11 2.
71M6543F/71M6543G Data Sheet 4 5 v2 3.2.2 LCD Mode ...................................................................................................................... 77 3.2.3 SLP Mode ...................................................................................................................... 78 3.3 Fault and Reset Behavior .......................................................................................................... 79 3.3.1 Events at Power-Down ................................
71M6543F/71M6543G Data Sheet 6 71M6543 Specifications.................................................................................................................. 130 6.1 Absolute Maximum Ratings ..................................................................................................... 130 6.2 Recommended External Components ..................................................................................... 131 6.3 Recommended Operating Conditions .........................................
71M6543F/71M6543G Data Sheet Figures Figure 1: IC Functional Block Diagram ......................................................................................................... 9 Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes) ......................................................... 12 Figure 3. AFE Block Diagram (Four CTs) ................................................................................................... 13 Figure 4: States in a Multiplexer Frame (MUX_DIV[3:0] = 6) ..
71M6543F/71M6543G Data Sheet Tables Table 1. Required CE Code and Settings for 1-Local / 3-Remotes ............................................................ 15 Table 2. Required CE Code and Settings for CT Sensors ......................................................................... 16 Table 3: Multiplexer and ADC Configuration Bits........................................................................................ 19 Table 4. RCMD[4:0] Bits .....................................................
1M6543F/71M6543G Data Sheet Table 49: Data/Direction Registers for SEGDIO32 to SEGDIO45.............................................................. 60 Table 50: Data/Direction Registers for SEGDIO51 to SEGDIO55.............................................................. 61 Table 51: LCD_VMODE Configurations ...................................................................................................... 61 Table 52: LCD Configurations ...............................................................
71M6543F/71M6543G Data Sheet Table 99: PLL Performance Specifications ............................................................................................... 137 Table 100: LCD Drivers Performance Specifications ............................................................................... 137 Table 101: VLCD Generator Specifications .............................................................................................. 138 Table 102: 71M6543 VREF Performance Specifications .................
71M6543F/71M6543G Data Sheet VREF IADC0 IADC1 IADC2 IADC3 IADC4 IADC5 IADC6 IADC7 VADC8 (VA) VADC9 (VB) VADC10 (VC) V3P3A GNDA GNDD VLCD V3P3SYS ∆Σ_ AD CONVERTER VBIAS MUX and PREAMP VBIAS V3P3A VLCD Voltage Boost FIR - V3P3D + VREF VREF MUX MUX CTRL VBAT CROSS Voltage Regulator CK32 XIN XOUT MCK PLL RTCLK (32KHz) Oscillator CK32 32KHz 32 KHz DIV ADC 4.9 MHZ CKADC 4.9 MHz 22 CK_4X CLOCK GEN 2.
71M6543F/71M6543G Data Sheet 1 Introduction This data sheet covers the 71M6543F (64KB) and 71M6543G (128KB) 4th-generation polyphase energy measurement system-on-chips (SoCs). The term “71M6543” is used when discussing a device feature or behavior that is applicable to all four part numbers. The specific part numbers are used when discussing those features that apply only to specific part numbers. This data sheet also covers details about the companion 71M6xx3 isolated current sensor device.
71M6543F/71M6543G Data Sheet 2 Hardware Description 2.1 Hardware Overview The 71M6543 single-chip energy meter integrates all primary functional blocks required to implement a solid-state electricity meter.
71M6543F/71M6543G Data Sheet number of LCD segments and DIO pins can be implemented in software to accommodate various requirements. In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on metrology and RTC accuracy (i.e., to meet the requirements of ANSI and IEC standards).
71M6543F/71M6543G Data Sheet The 71M6543 AFE can also be directly interfaced to Current Transformers (CTs), as seen in Figure 3. In this case, all voltage and current channels are multiplexed into a single second-order sigma-delta ADC in the 71M6543 and the 71M6xx3 remote isolated sensors are not used. The fourth CT and the measurement of Neutral current via the IADC0-IADC1 current channel are optional. See Figure 32 for the meter wiring configuration corresponding to Figure 3.
71M6543F/71M6543G Data Sheet Pins IADC0-IADC1 can be programmed individually to be differential or single-ended as determined by the DIFF0_E (I/O RAM 0x210C[4]) control bit. However, for most applications, IADC0-IADC1 are configured as a differential input to work with a resistive shunt or CT directly interfaced to the IADC0IADC1 differential input with the appropriate external signal conditioning components.
71M6543F/71M6543G Data Sheet Table 1. Required CE Code and Settings for 1-Local / 3-Remotes I/O RAM I/O RAM I/O RAM Setting Comments Mnemonic Location FIR_LEN[1:0] 210C[2:1] 1 288 cycles ADC_DIV 2200[5] 0 Fast PLL_FAST 2200[4] 1 19.
71M6543F/71M6543G Data Sheet Table 2. Required CE Code and Settings for CT Sensors I/O RAM I/O RAM I/O RAM Setting Comments Mnemonic Location (Hex) FIR_LEN[1:0] 210C[2:1] 1 288 cycles ADC_DIV 2200[5] 0 Fast PLL_FAST 2200[4] 1 19.
71M6543F/71M6543G Data Sheet Using settings for the I/O RAM Mnemonics listed in Table 1 and Table 2 that do not match those required by the corresponding CE code being used may result in undesirable side effects and must not be selected by the MPU. Consult your local Maxim representative to obtain the correct CE code and AFE / MUX settings corresponding to the application.
71M6543F/71M6543G Data Sheet Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally, MUX_CTRL launches each pass of the CE through its code. MUX_CTRL is clocked by CK32, the 32768 Hz clock from the PLL block.
71M6543F/71M6543G Data Sheet Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0], MUXn_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code. Refer to Table 1 and Table 2 for the settings that are applicable to the 71M6543. Table 3 summarizes the I/O RAM registers used for configuring the multiplexer, signals pins, and ADC. All listed registers are 0 after reset and wake from battery modes, and are readable and writable.
71M6543F/71M6543G Data Sheet The recommended ADC multiplexer sequence samples the current first, immediately followed by sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle Ф relative to the current. The delay compensation implemented in the CE aligns the voltage samples with their corresponding current samples by first delaying the current samples by one full sample interval (i.e.
71M6543F/71M6543G Data Sheet A Vinp B A Vinn B A + G - B A B Voutp Voutn CROSS Figure 6: General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input.
71M6543F/71M6543G Data Sheet 2.2.8 8 71M6xx3 Isolated Sensor Interface 2.2.8.1 General Description Non-isolating sensors, such as shunt resistors, can be connected to the inputs of the 71M6543 via a combination of a pulse transformer and a 71M6xx3 IC (a top-level block diagram of this sensor interface is shown in Figure 31). The 71M6xx3 receives power directly from the 71M6543 via a pulse transformer and does not require a dedicated power supply circuit.
8 71M6543F/71M6543G Data Sheet Table 4. RCMD[4:0] Bits Phase Selector RCMD[1:0] 00 Invalid IADC2-IADC3 01 IADC4-IADC5 10 IADC6-IADC7 11 Command Associated TMUXRn RCMD[4:2] Control Field --000 Invalid 001 Command 1 TMUXR2[2:0] 010 Command 2 TMUXR4[2:0] 011 Reserved TMUXR6[2:0] 100 Reserved 101 Invalid 110 Reserved 111 Reserved Notes: 1. Only two codes of RCMD[4:2] (SFR 0xFC[4:2]) are relevant for normal operation. These are RCMD[4:2] = 001 and 010. Codes 000 and 101 are invalid and will be ignored if used.
71M6543F/71M6543G Data Sheet 8 Table 6: I/O RAM Control Bits for Isolated Sensor Name Address RST WAKE Default Default R/W Description RCMD[4:0] SFR FC[4:0] 0 0 R/W PERR_RD PERR_WR SFR FC[6] SFR FC[5] 0 0 R/W CHOPR[1:0] 2709[7:6] 00 00 R/W TMUXR2[2:0] TMUXR4[2:0] TMUXR6[2:0] RMT_RD[15:8] RMT_RD[7:0] 270A[2:0] 270A[6:4] 2709[2:0] 2602[7:0] 2603[7:0] 000 000 000 000 000 000 R/W R/W R/W 0 0 R When the MPU writes a non-zero value to RCMD, the 71M6543 issues a command to the correspo
71M6543F/71M6543G Data Sheet 2.3 Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include: • • • • • • • • Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when multiplied by the constant sample time).
71M6543F/71M6543G Data Sheet 2.3.4 Meter Equations The 71M6543 provides hardware assistance to the CE in order to support various meter equations. This assistance is controlled through I/O RAM field EQU[2:0] (equation assist, I/O RAM 0x2106[7:5]). The Compute Engine (CE) firmware configurations can implement the equations listed in Table 7. EQU[2:0] specifies the equation to be used based on the meter configuration and on the number of phases used for metering.
71M6543F/71M6543G Data Sheet A common use of the zero-crossing pulses is to generate interrupts in order to drive real-time clock software in places where the mains frequency is sufficiently accurate to do so and also to adjust for crystal aging. A common use for the SAG pulse is to generate an interrupt that alerts the MPU when mains power is about to fail, so that the MPU code can store accumulated energy and other data to EEPROM before the V3P3SYS supply voltage actually drops. 2.3.6.
71M6543F/71M6543G Data Sheet The WPULSE and VPULSE pulse generator outputs are available on pins SEGDIO0/WPULSE and SEGDIO1/VPULSE, respectively (pins 45 and 44). The pulses can also be output on OPT_TX pin 53 (see OPT_TXE[1:0], I/O RAM 0x2456[3:2] for details).
71M6543F/71M6543G Data Sheet VB IB IC VA VC ID IA 61.04 µs 61.04 µs Multiplexer Frame (15 x 30.518 µs = 457.8 µs) 61.04 µs 61.04 µs 30.5 µs MUX_DIV = 7 Conversions Settle CK32 (32768 Hz) MUX STATE S 0 1 2 3 4 5 6 S Figure 10: Samples from Multiplexer Cycle (Frame) The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
71M6543F/71M6543G Data Sheet 2.4 80515 MPU Core The 71M6543 include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed in a single machine cycle (MPU clock cycle).
71M6543F/71M6543G Data Sheet The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (PDATA, SFR 0xBF, provides the upper 8 bytes for the MOVX A,@Ri instruction). Internal and External Memory Map Table 9 shows the address, type, use and size of the various memory components.
71M6543F/71M6543G Data Sheet An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction MOVX A,@Ri or MOVX @Ri,A. Internal Data Memory Map and Access The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory address is always 1 byte wide. Table 10 shows the internal data memory map.
71M6543F/71M6543G Data Sheet 2.4.3 Generic 80515 Special Function Registers Table 12 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional descriptions of the registers can be found at the page numbers listed in the table.
71M6543F/71M6543G Data Sheet Accumulator (ACC, A, SFR 0x E0): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC. B Register (SFR 0xF0): The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data.
71M6543F/71M6543G Data Sheet Table 14: Port Registers (SEGDIO0-15) SFR Name SFR Address P0 P1 P2 P3 80 90 A0 B0 D7 D6 D5 D4 D3 DIO_DIR[3:0] DIO_DIR[7:4] DIO_DIR[11:8] DIO_DIR[15:12] D2 D1 D0 DIO[3:0] DIO[7:4] DIO[11:8] DIO[15:11] All DIO ports on the chip are bi-directional. Each of them consists of a latch (SFR P0 to P3), an output driver and an input buffer, therefore the MPU can output or read data through any of these ports.
71M6543F/71M6543G Data Sheet • • UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first. UART0 TX: This pin is used to output the serial data. The bytes are output LSB first. The 71M6543 has several UART-related registers for the control and buffering of serial data. A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0 and S1BUF, SFR 0x9C for UART1).
71M6543F/71M6543G Data Sheet th addressing the slave, the host outputs the rest of the message with the 9 bit set to 0, so no additional serial port receive interrupts is generated. UART Control Registers: The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON and S1CON shown in Table 18 and Table 19, respectively, and the PCON register shown in Table 20.
71M6543F/71M6543G Data Sheet Table 20: PCON Register Bit Description (SFR 0x87) Bit PCON[7] 2.4.6 Symbol Function SMOD The SMOD bit doubles the baud rate when set Timers and Counters The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle, i.e. it counts up once for every 12 periods of the MPU clock.
71M6543F/71M6543G Data Sheet Table 23: TMOD Register Bit Description (SFR 0x89) Bit Symbol Timer/Counter 1: TMOD[7] Gate TMOD[6] If TMOD[7] is set, external input signal control is enabled for Counter 1. The TR0 bit in the TCON register (SFR 0x88) must also be set in order for Counter 0 to increment. With these settings, Counter 0 increments on every falling edge of the logic signal applied to one or more of the SEGDIO2-11 pins, as specified by the contents of the DIO_R2 through DIO_R11 registers.
71M6543F/71M6543G Data Sheet Referring to Figure 12, interrupt sources can originate from within the 80515 MPU core (referred to as Internal Sources) or can originate from other parts of the 71M6543 SoC (referred to as External Sources). There are seven external interrupt sources, as seen in the leftmost part of Figure 12, and in Table 25 and Table 26 (i.e., EX0-EX6). Interrupt Overview When an interrupt occurs, the MPU vectors to the predetermined address as shown in Table 37.
71M6543F/71M6543G Data Sheet Table 27: The IEN2 Bit Functions (SFR 0x9A) Bit Symbol IEN2[0] ES1 Function ES1 = 0 disables the serial channel 1 interrupt. Table 28: TCON Bit Functions (SFR 0x88) Bit TCON[7] TCON[6] TCON[5] TCON[4] TCON[3] TCON[2] Symbol TF1 TR1 TF0 TR0 IE1 IT1 TCON[1] TCON[0] IE0 IT0 Function Timer 1 overflow flag. Not used for interrupt control. Timer 0 overflow flag. Not used for interrupt control. External interrupt 1 flag.
71M6543F/71M6543G Data Sheet External MPU Interrupts The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6543, for example the CE, DIO, RTC, or EEPROM interface. The external interrupts are connected as shown in Table 31. The polarity of interrupts 2 and 3 is programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be programmed for falling sensitivity (I3FR = I2FR = 0).
71M6543F/71M6543G Data Sheet Interrupt Enable Name EX_RTC1M EX_RTCT EX_SPI EX_EEX EX_XPULSE EX_YPULSE EX_WPULSE EX_VPULSE Interrupt Flag Location Name Location 2700[2] 2700[4] 2701[7] 2700[7] 2700[6] 2700[5] 2701[6] 2701[5] IE_RTC1M IE_RTCT IE_SPI IE_EEX IE_XPULSE IE_YPULSE IE_WPULSE IE_VPULSE SFR E8[2] SFR E8[4] SFR F8[7] SFR E8[7] SFR E8[6] SFR E8[5] SFR F8[6] SFR F8[5] Interrupt Description RTC_1MIN interrupt (int 6) RTC_T interrupt (int 6) SPI interrupt EEPROM interrupt CE_Xpulse interrupt (int
71M6543F/71M6543G Data Sheet External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 External interrupt 6 Polling sequence Table 36: Interrupt Polling Sequence Interrupt Sources and Vectors Table 37 shows the interrupts with their associated flags and vector addresses.
71M6543F/71M6543G Data Sheet Figure 12: Interrupt Structure V2 45
71M6543F/71M6543G Data Sheet 2.5 On-Chip Resources 2.5.1 Physical Memory 2.5.1.1 Flash Memory The device includes 64 KB (71M6543F) or 128 KB (71M6543G) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations. Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB).
71M6543F/71M6543G Data Sheet The page erase sequence is: • • Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:2]). Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94). Bank-Switching in the 71M6543G The 128 KB program memory in the 71M6543G consists of a fixed lower bank of 32 KB, addressable at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF.
71M6543F/71M6543G Data Sheet FLSH_UNLOCK[3:0]. FLSH_UNLOCK[3:0] is not automatically reset. It should be cleared when the SPI or ICE has finished changing the Flash. Table 40 summarizes the I/O RAM registers used for flash security. Table 40: Flash Security Name FLSH_UNLOCK[3:0] Location Rst Wk Dir 2702[7:4] 0 0 R/W SECURE SFR B2[6] 0 0 R/W Description Must be a 2 to enable any flash modification. See the description of Flash security for more details.
71M6543F/71M6543G Data Sheet Although the oscillator may appear to work when VBAT is not connected, this mode of operation is not recommended. If VBAT_RTC is connected to a drained battery or disconnected, a battery test that sets TEMP_BAT may drain the supply connected to VBAT_RTC and cause the oscillator to stop. A stopped oscillator may force the device to reset. Therefore, an unexpected reset during a battery test should be interpreted as a battery failure. 2.5.
71M6543F/71M6543G Data Sheet 2.5.4.2 Accessing the RTC Two bits, RTC_RD (I/O RAM 0x2890[6]) and RTC_WR (I/O RAM 0x2890[7]), control the behavior of the shadow register. When RTC_RD is low, the shadow register is updated by the RTC after each two milliseconds. When RTC_RD is high, this update is halted and the shadow register contents become stationary and are suitable to be read by the MPU.
71M6543F/71M6543G Data Sheet 2.5.4.3 RTC Rate Control The 71M6543 has two rate adjustment mechanisms: • • The first rate adjustment mechanism is an analog rate adjustment, using the I/O RAM register RTCA_ADJ[6:0], that trims the crystal load capacitance. The second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency is processed in the RTC. Setting RTCA_ADJ[6:0] to 00 minimizes the load capacitance, maximizing the oscillator frequency.
71M6543F/71M6543G Data Sheet 2.5.4.4 RTC Temperature Compensation The 71M6543 can be configured to regularly measure die temperature, including in SLP and LCD modes and while the MPU is halted. If enabled by OSC_COMP, this temperature information is automatically used to correct for the temperature variation of the crystal. A table lookup method is used. Table 43 shows I/O RAM registers involved in automatic RTC temperature compensation.
71M6543F/71M6543G Data Sheet For proper operation, the MPU has to load the lookup table with values that reflect the crystal properties with respect to temperature, which is typically done once during initialization. Since the lookup table is not directly addressable, the MPU uses the following procedure to load the NV RAM table: 1. Set the LKPAUTOI bit (I/O RAM 0x2887[7]) to enable address auto-increment. 2. Write zero into the I/O RAM register LKPADDR[6:0] (I/O RAM 0x2887[6:0]). 3.
71M6543F/71M6543G Data Sheet read and properly combined to form the STEMP[10:0] 11-bit value (see STEMP in Table 45). The resulting 11-bit value is in 2’s complement form and ranges from -1024 to +1023 (decimal). The equations below are used to calculate the sensed temperature. The first equation applies when the 71M6543F and 71M6543G are in MSN mode and TEMP_PWR = 1.
71M6543F/71M6543G Data Sheet If TEMP_PWR selects VBAT_RTC when the battery is nearly discharged, the temperature measurement may not finish. In this case, firmware may complete the measurement by selecting V3P3D (TEMP_PWR = 1).
71M6543F/71M6543G Data Sheet 2.5.6 71M6xx3 Temperature Sensor The 71M6xx3 includes an on-chip temperature sensor for determining the temperature of its bandgap reference. The primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system for the compensation of the current measurement performed by the71M6xx3. See the 71M6xxx Data Sheet for the equation to calculate temperature from the 71M6xx3 STEMP[10:0] reading. Also, see 4.
71M6543F/71M6543G Data Sheet When not needed for UART1, OPT_TX can alternatively be configured as SEGDIO51. Configuration is via the OPT_TXE[1:0] (I/O RAM 0x2456[3:2]) field and LCD_MAP[51] (I/O RAM 0x2405[0]). The OPT_TXE[1:0] field allows the MPU to select VPULSE, WPULSE, SEGDIO51 or the output of the pulse modulator to be sourced onto the OPT_TX pin. Likewise, the OPT_RX pin can alternately be configured as SEGDIO55, and its control is OPT_RXDIS (I/O RAM 0x2457[2]) and LCD_MAP[55] (I/O RAM 0x2405[4]).
71M6543F/71M6543G Data Sheet registers LCD_MAPn (0x2405 – 0x240B). Setting the bit corresponding to the pin in LCD_MAPn to 1 configures the pin for LCD, setting LCD_MAPn to 0 configures it for DIO. After reset or power up, pins SEGDIO0 through SEGDIO15 are initially DIO outputs, but are disabled by PORT_E = 0 (I/O RAM 0x270C[5]) to avoid unwanted pulses during reset. After configuring pins SEGDIO0 through SEGDIO15 the MPU must enable these pins by setting PORT_E.
71M6543F/71M6543G Data Sheet MISSION LCD/SLEEP BROWNOUT V3P3SYS MISSION LCD/SLEEP BROWNOUT VBAT V3P3D HIGH HIGH-Z LOW DIO VBAT V3P3D HIGH HIGH-Z LOW GNDD Not recommended V3P3SYS DIO GNDD Recommended Figure 16: Connecting an External Load to DIO Pins 2.5.10.2 Combined DIO and SEG Pins A total of 51 combined DIO/LCD pins are available.
71M6543F/71M6543G Data Sheet Table 47: Data/Direction Registers and Internal Resources for SEGDIO0 to SEGDIO15 SEGDIO 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin # 45 44 43 42 41 39 38 37 36 35 34 33 32 31 30 29 0 Configuration: 0 = DIO, 1 = LCD SEG Data Register DIO Data Register Direction Register: 0 = input, 1 = output Internal Resources Configurable (see Table 46) 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 LCD_MAP[7:0] (I/O RAM 0x240B) LCD_MAP[15:8] (I/O RAM 0x240A) 10 11 12 13 14 1
71M6543F/71M6543G Data Sheet Table 50: Data/Direction Registers for SEGDIO51 to SEGDIO55 SEGDIO 51 52 53 54 55 Pin # 53 52 51 47 46 3 4 5 Configuration: 0 = DIO, 1 = LCD SEG Data Register DIO Data Register Direction Register: 0 = input, 1 = output – – – 6 7 – – – LCD_MAP[55:48] (I/O RAM 0x2405) 51 52 53 54 55 – – – LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0] (I/O RAM 0x2443[5:0] to 0x2447[5:0]) 51 52 53 54 55 – – – LCD_SEGDIO51[0] to LCD_SEGDIO55[0] (I/O RAM 0x2443[0] to 0x2447[0]) 51 52 53 5
71M6543F/71M6543G Data Sheet When using the VLCD boost circuit, use care when setting the LCD_DAC[4:0] (I/O RAM 0x240D[4:0]) value to ensure that the LCD manufacturer’s recommended operating voltage specification is not exceeded. The voltage doubler is active in all LCD modes including the LCD mode when LCD_BSTE = 1. Current dissipation in LCD mode can be reduced if the boost circuit is disabled and the LCD system is operated directly from VBAT.
71M6543F/71M6543G Data Sheet Table 52: LCD Configurations Name Location Rst Wk Dir LCD_ALLCOM 2400[3] 0 – R/W LCD_BAT 2402[7] 0 – R/W LCD_E 2400[7] 0 – R/W LCD_ON LCD_BLANK 240C[0] 240C[1] 0 0 – – R/W R/W LCD_RST 240C[2] 0 – R/W LCD_DAC[4:0] 240D[4:0] 0 – R/W LCD_CLK[1:0] 2400[1:0] 0 – R/W LCD_MODE[2:0] 2400[6:4] 0 – Description Configures all 6 SEG/COM pins as COM. Has no effect on pins whose LCD_MAP bit is zero. Connects the LCD power supply to VBAT in all modes.
71M6543F/71M6543G Data Sheet The LCD bias may be compensated for temperature using the LCD_DAC[4:0] field (I/O RAM 0x240D[4:0]). The bias may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in MSN mode and VBAT in BRN and LCD modes). When the LCD_DAC[4:0] field is set to 000, the DAC is bypassed and powered down. This setting can be used to reduce current in LCD mode.
71M6543F/71M6543G Data Sheet For example, if LCD_MAP[46] = 1, then pin 93 (TMUX2OUT/SEG46) is configured as SEG46, and if LCD_MAP[46]=0, then pin 93 is configured as TMUX2OUT. The SEG pins with alternate ICE interface function (see pins 56-58 in Figure 42) are forced to their alternate ICE interface function (i.e., E_RXTX, E_TCLK and E_RST) if the ICE_E pin (pin 59) is driven high, and in this case, the bits LCD_MAP[50:48] (I/O RAM 0x2405[2:0]) bits are “don’t care” bits.
71M6543F/71M6543G Data Sheet 2.5.11.2 Three-Wire (µ-Wire) EEPROM Interface with Single Data Pin A 500 kHz three-wire interface, using SDATA, SDCK, and a DIO pin for CS is available. The interface is selected by setting DIO_EEX[1:0] = 10. The EECTRL bits when the three-wire interface is selected are shown in Table 55. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM or read from the EEPROM, depending on the values of the EECTRL bits. 2.5.11.
71M6543F/71M6543G Data Sheet EECTRL Byte Written INT5 CNT Cycles (6 shown) Write -- With HiZ SCLK (output) SDATA (output) D7 D6 D5 SDATA output Z D4 D3 D2 (LoZ) (HiZ) BUSY (bit) Figure 19: 3-wire Interface. Write Command, HiZ=1 EECTRL Byte Written INT5 CNT Cycles (8 shown) READ SCLK (output) SDATA (input) D7 D5 D6 SDATA output Z D4 D3 D2 D1 D0 (HiZ) BUSY (bit) Figure 20: 3-wire Interface. Read Command.
71M6543F/71M6543G Data Sheet 1) An external host reads data from CE locations to obtain metering information. This can be used in applications where the 71M6543 function as a smart front-end with preprocessing capability. Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, I/O RAM, but not SFRs or the 80515-internal register bank.
71M6543F/71M6543G Data Sheet SPI Safe Mode Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte transfer region at address 0x400 to 0x40F.
71M6543F/71M6543G Data Sheet Name SPI_SAFE SPI_STAT Location Rst Wk Dir 270C[3] 0 0 R/W 2708[7:0] 0 0 R Description Limits SPI writes to SPI_CMD and a 16 byte region in DRAM when set. No other write operations are permitted. SPI_STAT contains the status results from the previous SPI transaction Bit 7 - 71M6543 ready error: the 71M6543 was not ready to read or write as directed by the previous command.
M6543F/71M6543G Data Sheet The I/O RAM registers SFMM (I/O RAM 0x2080) and SFMS (I/O RAM 0x2081) are used to invoke SFM. Only the SPI interface has access to these two registers. This eliminates an indirect path from the MPU for disabling the watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This sequential write process prevents inadvertent entering of SFM. The sequence for invoking SFM is: • First, write to SFMM (I/O RAM 0x2080) register.
71M6543F/71M6543G Data Sheet 2.5.14 Test Ports (TMUXOUT and TMUX2OUT Pins) Two independent multiplexers allow the selection of internal analog and digital signals for the TMUXOUT and TMUX2OUT pins. These pins are multiplexed with the SEG47 and SEG46 function. In order to function as test pins, LCD_MAP[46] (I/O RAM 0x2406[6]) and LCD_MAP[47] (I/O RAM 0x2406[7]) must be 0. One of the digital or analog signals listed in Table 60 can be selected to be output on the TMUXOUT pin.
71M6543F/71M6543G Data Sheet Table 60: TMUX2[4:0] Selections Signal Name Description 0 WD_OVF 1 PULSE_1S 2 PULSE_4S 3 A RTCLK SPARE[1] bit – I/O RAM 0x2704[1] SPARE[2] bit – I/O RAM 0x2704[2] WAKE B MUX_SYNC C E 12 13 14 15 16 17 18 1F MCK GNDD INT0 – DIG I/O INT1 – DIG I/O INT2 – CE_PULSE INT3 – CE_BUSY INT4 - VSTAT INT5 – EEPROM/SPI INT6 – XFER, RTC RTM_CK (flash) Indicates when the watchdog timer has expired (overflowed). One second pulse with 25% Duty Cycle.
71M6543F/71M6543G Data Sheet 3 Functional Description 3.
71M6543F/71M6543G Data Sheet When system power is not available, the 71M6543 is in one of three battery modes: • • • BRN mode (brownout mode) LCD mode (LCD-only mode) SLP mode (sleep mode). An internal comparator monitors the voltage at the V3P3SYS pin (note that V3P3SYS and V3P3A are typically connected together at the PCB level). When the V3P3SYS dc voltage drops below 2.8 VDC, the comparator resets an internal power status bit called V3OK .
71M6543F/71M6543G Data Sheet Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events: Wake-up timer timeout. Pushbutton (PB) is activated. A rising edge on SEGDIO4, or a high logic level on SEGDIO52 or SEGDIO55. Activity on the RX or OPT_RX pins. • • • • The MPU has access to a variety of registers that signal the event that caused the wake up. See 3.4 Wake-Up Behavior for details. Table 61 shows the circuit functions available in each operating mode.
71M6543F/71M6543G Data Sheet 3.2.1 BRN Mode In BRN mode, most non-metering digital functions are active (as shown in Table 61) including ICE, UART, EEPROM, LCD and RTC. In BRN mode, the PLL continues to function at the same frequency as MSN mode. It is up to the MPU to scale down the PLL (using PLL_FAST, I/O RAM 0x2200[4]) or the MPU frequency (using MPU_DIV[2:0], I/O RAM 0x2200[2:0]) in order to save power. From BRN mode, the MPU can choose to enter LCD or SLP modes.
71M6543F/71M6543G Data Sheet 3.2.3 SLP Mode The SLP mode may be commanded by the MPU whenever main system power is absent by asserting the SLEEP bit (I/O RAM 0x28B2[7]). The purpose of the SLP mode is to consume the least power while still maintaining the RTC, temperature compensation of the RTC, and the non-volatile portions of the I/O RAM. In SLP mode, the V3P3D pin is disconnected, removing all sources of leakage from VBAT and V3P3SYS.
71M6543F/71M6543G Data Sheet 3.3 Fault and Reset Behavior 3.3.1 Events at Power-Down Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and also monitor the internally generated VDD pin voltage (2.5 VDC). The V3P3SYS and V3P3A pins must be tied together at the PCB level, so that the comparators, which are internally connected only to the V3P3A pin, are able to simultaneously monitor the common V3P3SYS and V3P3A pin voltage.
71M6543F/71M6543G Data Sheet 3.3.2 IC Behavior at Low Battery Voltage When system power is not present, the 71M6543 relies on the VBAT pin for power. If the VBAT voltage is not sufficient to maintain VDD at 2.0 VDC or greater, the MPU cannot operate reliably. Low VBAT voltage can occur while the part is operating in BRN mode, or while it is dormant in SLP or LCD mode.
71M6543F/71M6543G Data Sheet In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit I/O RAM 0x28B4[7]). The watchdog timer is also reset when the 71M6543 wakes from LCD or SLP mode, and when ICE_E=1. 3.4 Wake-Up Behavior As described above, the part always wakes up in MSN mode when system power is restored. As stated in 3.
71M6543F/71M6543G Data Sheet Wake Enable Name Location Always Enabled Wake Flag Name Location WF_OVF 28B0[4] De-bounce Description No Wake after WD reset. Wake after cold start - the first WF_CSTART Always Enabled 28B0[7] No application of power. Wake after insufficient VBAT WF_BADVDD Always Enabled 28B0[2] No voltage. *This pin is sampled every 2 ms and must remain high for 64 ms to be declared a valid high level. This pin is highlevel sensitive.
71M6543F/71M6543G Data Sheet Table 65: Clear Events for WAKE flags Flag Wake on: Clear Events WF_TMR Timer expiration WF_PB PB pin high level WAKE falls WF_RX Either edge RX pin WAKE falls WF_DIO4 SEGDIO4 rising edge WAKE falls WF_DIO52 SEGDIO52 high level If OPT_RXDIS = 1 (I/O RAM 0x2457[2]), wake on SEGDIO55 high If OPT_RXDIS = 0 wake on either edge of OPT_RX WAKE falls RESET pin driven high WAKE falls, WF_CSTART, WF_RSTBIT, WF_OVF, WF_BADVDD RESET bit is set (I/O RAM 0x2200[3]) WAKE f
71M6543F/71M6543G Data Sheet 2 2 active power (Wh), reactive power (VARh), A h, and V h for four-quadrant metering. These measurements are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU. Both the CE and multiplexer are controlled by the MPU via shared registers in the I/O RAM and in RAM. The CE outputs a total of six discrete signals to the MPU.
71M6543F/71M6543G Data Sheet 4 Application Information 4.1 Connecting 5 V Devices All digital input pins of the 71M6543 are compatible with external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V devices. 4.
71M6543F/71M6543G Data Sheet 4.3 Systems Using 71M6xx3 Isolated Sensors and Current Shunts Figure 31 shows a typical connection for current shunt sensors; using the 71M6xx3 (polyphase) isolated sensors. Note that one shunt current sensor is connected without isolation, which is the neutral current sensor in this example (connected to pins IADC0-IADC1). Each 71M6xx3 device is electrically isolated by a low-cost pulse transformer.
71M6543F/71M6543G Data Sheet 4.4 System Using Current Transformers Figure 32 shows a polyphase system using four current transformers to support optional Neutral current sensing for anti-tamper purposes. The Neutral current sensing CT can be omitted if Neutral current sensing is not required. The system is referenced to Neutral (i.e., the Neutral rail is tied to V3P3A and V3P3SYS).
71M6543F/71M6543G Data Sheet 4.5 Metrology Temperature Compensation 4.5.1 Temperature Compensation Since the VREF band-gap amplifier is chopper-stabilized, as set by the CHOP_E[1:0] (I/O RAM 0x2106[3:2]) control field, the dc offset voltage, which is the most significant long-term drift mechanism in the voltage references (VREF), is automatically removed by the chopper circuit. Both the 71M6543 and the 71M6xx3 feature chopper circuits for their respective VREF voltage reference.
71M6543F/71M6543G Data Sheet 4.5.3 Temperature Coefficients for the 71M6xx3 Refer to the 71M6xxx Data sheet for the equations that are applicable to each 71M6xx3 part number and the corresponding temperature coefficients. 4.5.4 Temperature Compensation for VREF and Shunt Sensors This section discusses metrology temperature compensation for the meter designs where current shunt sensors are used in conjunction with the 71M6xx3 remote isolated sensors, as shown in Figure 31.
71M6543F/71M6543G Data Sheet Table 66: GAIN_ADJn Compensation Channels (Figure 2, Figure 31, Table 1) Gain Adjustment Output CE RAM Address GAIN_ADJ0 0x40 GAIN_ADJ1 0x41 GAIN_ADJ2 0x42 GAIN_ADJ3 0x43 GAIN_ADJ4 0x44 Sensor Channel(s) (pin names) VADC8 (VA) VADC9 (VB) VADC10 (VC) IADC0-IADC1 IADC2-IADC3 IADC4-IADC5 IADC6-IADC7 Compensation For: VREF in 71M6543 and Voltage Divider Resistors VREF in 71M6543 and Shunt (Neutral Current) VREF in 71M6xx3 and Shunt (Phase A) VREF in 71M6xx3 and Shunt (P
71M6543F/71M6543G Data Sheet differential signal conditioning circuit, as shown in Figure 29, to connect the CTs to the 71M6543. Current transformers may also require temperature compensation. The copper wire winding in the CT has dc resistance with a temperature coefficient, which makes the voltage delivered to the burden resistor temperature dependent, and the burden resistor also has a temperature coefficient.
71M6543F/71M6543G Data Sheet corresponding sensor circuit (i.e., the CT and burden resistor for current channels or the resistor divider network for the voltage channels). In the 71M6543F and 71M6543G, the required VREF compensation coefficients PPMC and PPMC2 are calculated from readable on-chip non-volatile fuses (see 4.5.2Temperature Coefficients for the 71M6543F). These coefficients are designed to achieve ±40 ppm/°C for VREF. 4.
71M6543F/71M6543G Data Sheet 4.9 Optical Interface (UART1) The OPT_TX and OPT_RX pins can be used for a regular serial interface (by connecting a RS_232 transceiver for example), or they can be used to directly operate optical components (for example, an infrared diode and phototransistor implementing a FLAG interface). Figure 35 shows the basic connections for UART1. The OPT_TX pin becomes active when the control field OPT_TXE (I/O RAM 0x2456[3:2]) is set to 01.
71M6543F/71M6543G Data Sheet VBAT/ V3P3D 71M6543 71M6543 V3P3D R2 1k Ω Reset Switch RESET 10k Ω R1 0.1µF GNDD Figure 36: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) 4.11 Connecting the Emulator Port Pins Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection from EMI as illustrated in Figure 37. Production boards should have the ICE_E pin connected to ground.
71M6543F/71M6543G Data Sheet 4.14 Crystal Oscillator The oscillator of the 71M6543 drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached to the VBAT_RTC pin. Board layouts with minimum capacitance from XIN to XOUT require less battery current.
71M6543F/71M6543G Data Sheet 5 Firmware Interface 5.1 I/O RAM Map –Functional Order In Table 68 and Table 69, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’. Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits are identified with an ‘R’, and must always be written with a zero.
71M6543F/71M6543G Data Sheet Name Addr Bit 7 LCD_BAT Bit 6 R Bit 5 Bit 4 Bit 3 Bit 2 LCD_BLNKMAP22[5:0] LCD_MAP[55:48] LCD_MAP[47:40] LCD_MAP[39:32] LCD_MAP[31:24] LCD_MAP[23:16] LCD_MAP[15:8] LCD_MAP[7:0] U U U DIO_R11[2:0] U DIO_R9[2:0] U DIO_R7[2:0] U DIO_R5[2:0] U DIO_R3[2:0] U U U OPT_TXE[1:0] OPT_FDC[1:0] U OPT_RXDIS U U U U EX_YPULSE EX_RTCT U EX_RTC1M EX_VPULSE EW_RX EW_PB EW_DIO4 SFMM[7:0]* SFMS[7:0]* LCD2 2013 LCD_MAP6 2014 LCD_MAP5 2015 LCD_MAP4 2016 LCD_MAP3 2017 LCD_MAP2 2018 LCD_MAP1 20
71M6543F/71M6543G Data Sheet Table 69 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits have a darker gray background.
71M6543F/71M6543G Data Sheet Name Addr Bit 7 Bit 6 Bit 5 LCD_MAP2 LCD_MAP1 LCD_MAP0 LCD4 LCD_DAC SEGDIO0 … SEGDIO15 SEGDIO16 … SEGDIO45 SEGDIO46 … SEGDIO50 SEGDIO51 … SEGDIO55 2409 240A 240B 240C 240D 2410 … 241F 2420 … 243D 243E … 2442 2443 … 2447 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U DIO_R5 2450 DIO_R4 2451 DIO_R3 2452 DIO_R2 2453 DIO_R1 2454 DIO_R0 2455 DIO0 2456 DIO1 2457 DIO2 2458 NV BITS SPARENV 2500 FOVRD 2501 TMUX 2502 TMUX2 2503 RTC1 2504 71M6xx3 Interface v2 U R U
71M6543F/71M6543G Data Sheet Name Addr REMOTE2 2602 REMOTE1 2603 RBITS INT1_E 2700 INT2_E 2701 SECURE 2702 Analog0 2704 VERSION 2706 INTBITS 2707 FLAG0 SFR E8 FLAG1 SFR F8 STAT SFR F9 REMOTE0 SFR FC SPI1 SFR FD SPI0 2708 RCE0 2709 RTMUX 270A DIO3 270C NV RAM and RTC 2800NVRAMxx 287F WAKE 2880 STEMP1 2881 STEMP0 2882 BSENSE 2885 LKPADDR 2887 LKPDATA 2888 LKPCTRL 2889 RTC0 2890 RTC2 2892 RTC3 2893 RTC4 2894 RTC5 2895 100 Bit 7 EX_EEX EX_SPI VREF_CAL U IE_EEX IE_SPI U U Bit 6 Bit 4 Bit 3 RMT_RD[15:8] RMT
71M6543F/71M6543G Data Sheet Name Addr Bit 7 U U U RTC6 2896 RTC7 2897 RTC8 2898 RTC9 2899 U RTC10 289B RTC11 289C RTC12 289D U RTC13 289E U RTC14 289F TEMP_BSEL TEMP 28A0 WF1 28B0 WF_CSTART U WF2 28B1 SLEEP MISC 28B2 U WAKE_E 28B3 WD_RST WDRST 28B4 MPU PORTS PORT3 SFR B0 PORT2 SFR A0 PORT1 SFR 90 PORT0 SFR 80 FLASH ERASE SFR 94 FLSHCTL SFR B2 PREBOOT U FL_BANK SFR B6 PGADR SFR B7 2 IC EEDATA SFR 9E EECTRL SFR 9F v2 Bit 6 U U U Bit 5 U U U Bit 4 U Bit 3 U Bit 2 Bit 1 RTC_DAY[2:0] Bit 0 RTC_DATE[
71M6543F/71M6543G Data Sheet 5.2 I/O RAM Map – Alphabetical Order Table 70 lists I/O RAM bits and registers in alphabetical order. Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to the address space 0x2XXX.
71M6543F/71M6543G Data Sheet Name CHOPR[1:0] DIFF0_E DIFF2_E DIFF4_E DIFF6_E DIO_R2[2:0] DIO_R3[2:0] DIO_R4[2:0] DIO_R5[2:0] DIO_R6[2:0] DIO_R7[2:0] DIO_R8[2:0] DIO_R9[2:0] DIO_R10[2:0] DIO_R11[2:0] DIO_RPB[2:0] v2 Location Rst Wk Dir 2709[7:6] 00 00 R/W 210C[4] 210C[5] 210C[6] 210C[7] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W 2455[2:0] 2455[6:4] 2454[2:0] 2454[6:4] 2453[2:0] 2453[6:4] 2452[2:0] 2452[6:4] 2451[2:0] 2451[6:4] 2450[2:0] 0 0 0 0 0 0 0 0 0 0 0 – R/W DIO_DIR[15:12] DIO_DIR[11:8] DIO_DIR[7:4]
71M6543F/71M6543G Data Sheet Name Location Rst Wk Dir DIO_EEX[1:0] 2456[7:6] 0 – R/W DIO_PV DIO_PW DIO_PX DIO_PY EEDATA[7:0] 2457[6] 2457[7] 2458[7] 2458[6] SFR 9E 0 0 0 0 0 – – – – 0 R/W R/W R/W R/W R/W EECTRL[7:0] SFR 9F 0 0 R/W Description When set, converts SEGDIO3 and SEGDIO2 to interface with external EEPROM. SEGDIO2 becomes SDCK and SEGDIO3 becomes bi-directional SDATA, but only if LCD_MAP[2] and LCD_MAP[3] are cleared.
71M6543F/71M6543G Data Sheet Name EX_XFER EX_RTC1S EX_RTC1M EX_RTCT EX_SPI EX_EEX EX_XPULSE EX_YPULSE EX_WPULSE EX_VPULSE 2700[0] 2700[1] 2700[2] 2700[3] 2701[7] 2700[7] 2700[6] 2700[5] 2701[6] 2701[5] 0 0 R/W EW_DIO4 28B3[2] 0 – R/W EW_DIO52 28B3[1] 0 – R/W EW_DIO55 28B3[0] 0 – R/W EW_PB 28B3[3] 0 – R/W EW_RX 28B3[4] 0 – R/W 210C[2:1] 0 0 R/W FIR_LEN[1:0] v2 Location Rst Wk Dir Description Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, etc.
71M6543F/71M6543G Data Sheet Name Location Rst Wk Dir FL_BANK[1:0] SFR B6[1:0] 01 01 R/W FLSH_ERASE[7:0] SFR 94[7:0] 0 0 W FLSH_MEEN SFR B2[1] 0 0 W FLSH_PEND SFR B2[3] 0 0 R SFR B7[7:2] 0 0 W 0 R/W FLSH_PGADR[5:0] FLSH_PSTWR 106 SFR B2[2] 0 Description Flash Bank Selection (71M6543G only) The program memory of the 71M6543G consists of a fixed lower bank of 32 KB, addressable at 0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF.
71M6543F/71M6543G Data Sheet Name v2 Location Rst Wk Dir FLSH_PWE SFR B2[0] 0 0 R/W FLSH_RDE 2702[2] – – R FLSH_UNLOCK[3:0] 2702[7:4] 0 0 R/W FLSH_WRE IE_XFER IE_RTC1S IE_RTC1M IE_RTCT IE_SPI IE_EEX IE_XPULSE IE_YPULSE IE_WPULSE IE_VPULSE 2702[1] SFR E8[0] SFR E8[1] SFR E8[2] SFR E8[3] SFR F8[7] SFR E8[7] SFR E8[6] SFR E8[5] SFR F8[6] SFR F8[5] – – R 0 0 R/W INTBITS 2707[6:0] – – R LCD_ALLCOM LCD_BAT LCD_BLNKMAP23[5:0] 0 0 – – R/W R/W LCD_BLNKMAP22[5:0] 2400[3] 2402[7] 24
71M6543F/71M6543G Data Sheet Name LCD_DAC[4:0] LCD_E LCD_MAP[55:48] LCD_MAP[47:40] LCD_MAP[39:32] LCD_MAP[31:24] LCD_MAP[23:16] LCD_MAP[15:8] LCD_MAP[7:0] Location Rst Wk Dir 240D[4:0] 0 – R/W 2400[7] 0 – R/W 2405[7:0] 2406[7:0] 2407[7:0] 2408[7:0] 2409[7:0] 240A[7:0] 240B[7:0] 0 0 0 0 0 0 0 – – – – – – – R/W R/W R/W R/W R/W R/W R/W Description The LCD contrast DAC. This DAC controls the VLCD voltage and has an output range of 2.65 V to 5.3 V. The VLCD voltage is VLCD = 2.65 + 2.
71M6543F/71M6543G Data Sheet Name LCD_SEG46[5:0] to LCD_SEG50[5:0] LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0] Location Rst Wk Dir Description 243E[5:0] 0 to 2442[5:0] – R/W SEG data for SEG46 through SEG50. These pins cannot be configured as DIO. 2443[5:0] to 0 2447[5:0] – R/W SEG and DIO data for SEGDIO51 through SEGDIO55. If configured as DIO, bit 1 is direction (1 is output, 0 is input), bit 0 is data, and the other bits are ignored. Specifies how VLCD is generated. See 2.5.10.
71M6543F/71M6543G Data Sheet Name MUX8_SEL[3:0] MUX9_SEL[3:0] MUX10_SEL[3:0] Location Rst Wk Dir Description 2101[3:0] 2101[7:4] 2100[3:0] 0 0 0 0 0 0 R/W R/W R/W MUX_DIV[3:0] 2100[7:4] 0 0 R/W 2457[0] 0 – R/W 2457[5:4] 0 – R/W Selects which ADC input is to be converted during time slot 8. Selects which ADC input is to be converted during time slot 9. Selects which ADC input is to be converted during time slot 10. MUX_DIV[3:0] is the number of ADC time slots in each MUX frame.
71M6543F/71M6543G Data Sheet Name PLL_OK PLL_FAST Description SFR F9[4] 0 0 R 2200[4] 0 0 R/W Indicates that the clock generation PLL is settled. Controls the speed of the PLL and MCK. 1 = 19.66 MHz (XTAL * 600) 0 = 6.29 MHz (XTAL * 192) PLS_MAXWIDTH[7:0] determines the maximum width of the pulse (low-going pulse if PLS_INV=0 or high-going pulse if PLS_INV=1). The maximum pulse width is (2*PLS_MAXWIDTH[7:0] + 1)*TI. Where TI is PLS_INTERVAL[7:0] in units of CK_FIR clock cycles.
71M6543F/71M6543G Data Sheet Name RMT2_E RMT4_E RMT6_E RMT_RD[15:8] RMT_RD[7:0] RTCA_ADJ[6:0] RTC_FAIL Location Rst Wk Dir 2709[3] 2709[4] 2709[5] 2602[7:0] 2603[7:0] 2504[6:0] 0 0 R/W 0 0 R 40 – R/W 2890[4] 0 0 R RTC_P[16:14] RTC_P[13:6] RTC_P[5:0] 289B[2:0] 289C[7:0] 289D[7:2] 4 0 0 4 0 0 R/W RTC_Q[1:0] 289D[1:0] 0 0 R/W 2890[6] 0 0 R/W RTC_SBSC[7:0] RTC_TMIN[5:0] 2892[7:0] 289E[5:0] – 0 – – R R/W RTC_THR[4:0] 289F[4:0] 0 – R/W 2890[7] 0 0 R/W 2893[5:0] 2894[5:0]
71M6543F/71M6543G Data Sheet Name RTM0[9:8] RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] Location Rst Wk Dir Description 210D[1:0] 210E[7:0] 210F[7:0] 2110[7:0] 2111[7:0] 0 0 0 0 0 0 0 0 0 0 R/W Four RTM probes. Before each CE code pass, the values of these registers are serially output on the RTM pin. The RTM registers are ignored when RTM_E = 0. Note that RTM0 is 10 bits wide. The others assume the upper two bits are 00.
71M6543F/71M6543G Data Sheet Name TEMP_BAT TEMP_BSEL Location Rst Wk Dir 28A0[4] 0 – R/W 28A0[7] 0 – R/W Description Causes VBAT to be measured whenever a temperature measurement is performed. Selects which battery is monitored by the temperature sensor: 1 = VBAT, 0 = VBAT_RTC Sets the period between temperature measurements. Automatic measurements can be enabled in any mode (MSN, BRN, LCD, or SLP).
71M6543F/71M6543G Data Sheet Name Location Rst Wk Dir Description This word describes the source of power and the status of the VDD. VSTAT[2:0] 000 001 VSTAT[2:0] SFR F9[2:0] – – R 010 011 101 v2 Description System Power OK. V3P3A>3.0v. Analog modules are functional and accurate. [V3AOK,V3OK]=11 System Power Low. 2.8v2.25v. Full digital functionality.
71M6543F/71M6543G Data Sheet 5.3 CE Interface Description 5.3.1 CE Program The CE performs the precision computations necessary to accurately measure power. These computations include offset cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag detection and voltage phase measurement. All data computed by the CE is dependent on the selected meter equation as given by EQU[2:0] (I/O RAM 0x2106[7:5]).
71M6543F/71M6543G Data Sheet 5.3.4 Environment Before starting the CE using the CE_E bit (I/O RAM 0x2106[0]), the MPU has to establish the proper environment for the CE by implementing the following steps: Locate the CE code in Flash memory using CE_LCTN[5:0] (I/O RAM 0x2109[5:0]) in the 71M6543F and CE_LCTN[6:0] (I/O RAM 0x2109[6:0]) in the 71M6543G. Load the CE data into RAM. Establish the equation to be applied in EQU[2:0] (I/O RAM 0x2106[7:5]).
71M6543F/71M6543G Data Sheet 5.3.6 CE Front-End Data (Raw Data) Access to the raw data provided by the AFE is possible by reading CE RAM addresses 0 through A, as shown in Table 72. In the expression MUXn_SEL[3:0] = x, ‘n’ refers to the multiplexer frame time slot number and ‘x’ refers to the desired ADC input number or ADC handle (i.e., IADC0 to VADC10, or simply 0 to 10 decimal). The 71M6543 can support up to eleven sensor inputs, when all the current sensors are configured as single-ended inputs.
71M6543F/71M6543G Data Sheet 5.3.7 CE Status and Control The CE Status Word is useful for generating early warnings to the MPU (Table 73). It contains sag warnings for phase A, B, and C, as well as F0, the derived clock operating at the fundamental input frequency. The MPU can read the CE status word at every CE_BUSY interrupt. Since the CE_BUSY interrupt occurs at the sample rate (i.e., 2520.6 Hz for MUX_DIV[3:0]=6 or 2184.
71M6543F/71M6543G Data Sheet Table 76: CECONFIG Bit Definitions (CE RAM 0x20) CECONFIG bit Name Default 23 Reserved 0 22 EXT_TEMP 0 21 EDGE_INT 1 20 SAG_INT 1 19:8 SAG_CNT 218 (0xDA) Description Reserved (can be used by the MPU to indicate that the 71M6x03 is being used; CE does not use this). When 1, the MPU controls temperature compensation via the GAIN_ADJn (CE RAM 0x40-0x42), when 0, the CE is in control.
71M6543F/71M6543G Data Sheet The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by the MPU if the EXT_PULSE bit = 1 (CE RAM 0x20[5]). In this case, the MPU controls the pulse rate (external pulse generation) by placing values into APULSEW and APULSER (CE RAM 0x45 and 0x49). By setting EXT_PULSE = 0, the CE controls the pulse rate based on WSUM_X (CE RAM 0x84) and VARSUM_X (CE RAM 0x88).
71M6543F/71M6543G Data Sheet Table 79: CE Transfer Variables (with CTs) CE Address Name 0x84 0x85 0x86 0x87 0x88 WSUM_X W0SUM_X W1SUM_X W2SUM_X VARSUM_X The signed sum: W0SUM_X+W1SUM_X+W2SUM_X. 0x89 0x8A 0x8B VAR0SUM_X VAR1SUM_X VAR2SUM_X The sum of VARh samples from each wattmeter element. -12 LSBW = 1.0856*10 VMAX IMAX VARh. Configuration Description The sum of Wh samples from each wattmeter element. -12 LSBW = 1.0856*10 VMAX IMAX Wh.
71M6543F/71M6543G Data Sheet The RMS values can be computed by the MPU from the squared current and voltage samples as follows: Ix RMS = IxSQSUM ⋅ LSBI ⋅ 3600 ⋅ FS N ACC VxRMS = VxSQSUM ⋅ LSBV ⋅ 3600 ⋅ FS N ACC Other transfer variables include those available for frequency and phase measurement, and those reflecting the count of the zero-crossings of the mains voltage and the battery voltage. These transfer variables are listed in Table 82.
71M6543F/71M6543G Data Sheet 1Wh/pulse, a power applied to the meter of 120 V and 30 A results in one pulse per second. If the load is 240 V at 150 A, ten pulses per second are generated. Control is transferred to the MPU for pulse generation if EXT_PULSE = 1 (CE RAM 0x20[5]). In this case, the pulse rate is determined by APULSEW and APULSER (CE RAM 0x45 and 0x49). The MPU has to load the source for pulse generation in APULSEW and APULSER to generate pulses.
71M6543F/71M6543G Data Sheet Table 83: CE Pulse Generation Parameters CE Address Name Default 0x21 WRATE 227 0x22 KVAR 6444 0x23 SUM_PRE 2184 0x45 APULSEW 0 0x46 WPULSE_CTR 0 0x47 WPULSE_ FRAC 0 0x48 0x49 0x4A WSUM_ ACCUM APULSER VPULSE_CTR 0 0 0 0x4B VPULSE_ FRAC 0 0x4C VSUM_ACCUM 0 Description Kh = VMAX*IMAX*K / (WRATE*NACC*X) Wh/pulse where: K = 76.3594 when used with local sensors (CT or shunt) K = 54.
71M6543F/71M6543G Data Sheet Table 84: CE Parameters for Noise Suppression and Code Version CE Address Name Default 0x26 0x27 0x28 0x2A 0x2B 0x2C 0x2E 0x2F 0x30 QUANT_IA QUANT_WA QUANT_VARA QUANT_IB QUANT_WB QUANT_VARB QUANT_IC QUANT_WC QUANT_VARC 0 0 0 0 0 0 0 0 0 Description Compensation factors for truncation and noise in current, real energy and reactive energy for phase A. Compensation factors for truncation and noise in current, real energy and reactive energy for phase B.
71M6543F/71M6543G Data Sheet 5.3.10 CE Calibration Parameters Table 85 lists the parameters that are typically entered to effect calibration of meter accuracy. Table 85: CE Calibration Parameters CE Address Name Default Description 0x10 0x11 0x13 0x14 0x16 0x17 0x19 CAL_IA CAL_VA CAL_IB CAL_VB CAL_IC CAL_VC CAL_ID 16384 16384 16384 16384 16384 16384 16384 These constants control the gain of their respective channels. The 14 nominal value for each parameter is 2 = 16384.
71M6543F/71M6543G Data Sheet 5.3.11 CE Flow Diagrams Figure 38 through Figure 40 show the data flow through the CE in simplified form. Functions not shown include delay compensation, sample interpolation, scaling and the processing of meter equations.
71M6543F/71M6543G Data Sheet SUM WA WB WC VARA VARB VARC WASUM_X WBSUM_X WCSUM_X VARASUM_X VARBSUM_X VARCSUM_X Σ Σ I2 V2 IASQ IBSQ ICSQ VASQ VBSQ VCSQ IDSQ F0 SUM Σ Σ v SQUARE IA IB IC VA VB VC ID MPU SUM_SAMPS = 2184 IASQSUM_X IBSQSUM_X ICSQSUM_X VASQSUM_X VBSQSUM_X VCSQSUM_X IDSQSUM_X F0 Figure 40: CE Data Flow: Squaring and Summation Stages v2 129
71M6543F/71M6543G Data Sheet 6 71M6543 Specifications This section provides the electrical specifications for the 71M6543. Please refer to the 71M6xxx Data Sheet for the 71M6xx3 electrical specifications, pin-out and package mechanical data. 6.1 Absolute Maximum Ratings Table 86 shows the absolute maximum ratings for the device. Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device.
71M6543F/71M6543G Data Sheet 6.2 Recommended External Components Table 87: Recommended External Components Name From To C1 V3P3A GNDA C2 V3P3D GNDD Function Value Unit Bypass capacitor for 3.3 V supply ≥0.1 ±20% µF Bypass capacitor for 3.3 V output 0.1 ±20% µF CSYS V3P3SYS GNDD Bypass capacitor for V3P3SYS ≥1.0 ±30% µF CVDD VDD GNDD Bypass capacitor for VDD 0.1 ±20% µF CVLCD VLCD GNDD Bypass capacitor for VLCD pin ≥0.1 ±20% µF XTAL XIN XOUT 32.
71M6543F/71M6543G Data Sheet 6.4 Performance Specifications 6.4.1 Input Logic Levels Table 89: Input Logic Levels Parameter Condition Min 1 Digital high-level input voltage , VIH 1 Digital low-level input voltage , VIL Input pullup current, IIL E_RXTX, E_RST, E_TCLK OPT_RX, OPT_TX SPI_CSZ (SEGDIO36) Other digital inputs Input pull down current, IIH ICE_E, RESET, TEST Other digital inputs Typ Max Unit 0.8 V V µA µA µA µA µA µA 2 VIN=0 V, ICE_E=3.
71M6543F/71M6543G Data Sheet 6.4.3 Battery Monitor Table 91: Battery Monitor Performance Specifications (TEMP_BAT = 1) Parameter BV: Battery Voltage (definition) Measurement Error BV 100 ⋅ − 1 VBAT Input impedance in continuous measurement, MSN mode. V(VBAT_RTC)/I(VBAT_RTC) Load applied with BCURR IBAT(BCURR=1) - IBAT(BCURR=0) v2 Condition MSN mode, TEMP_PWR = 1 BRN mode, TEMP_PWR=TEMP_BSEL VBAT = 2.0 V 2.5 V 3.0 V 4.0 V V3P3 = 3.3 V, TEMP_BSEL = 0, TEMP_PER = 111, VBAT_RTC = 3.
71M6543F/71M6543G Data Sheet 6.4.4 Temperature Monitor Table 92: Temperature Monitor Parameter Condition Temperature Measurement Equation for 71M6543F and 71M6543G (see notes 2 and 3) In MSN, TEMP_PWR=1: Temperature Error (71M6543) (see note 1) VBAT_RTC charge per measurement Min Max 𝑇𝑒𝑚𝑝 = 0.325 ∙ 𝑆𝑇𝐸𝑀𝑃 + 22 𝑇𝑒𝑚𝑝 = 0.325 ∙ 𝑆𝑇𝐸𝑀𝑃 + 0.00218 ∙ 𝐵𝑆𝐸𝑁𝑆𝐸 2 − 0.609 ∙ 𝐵𝑆𝐸𝑁𝑆𝐸 + 64.4 TA = 22⁰C -2 TEMP_BSEL = 0, TEMP_PWR=0, SLP Mode, VBAT_RTC = 3.
71M6543F/71M6543G Data Sheet 6.4.5 Supply Current The supply currents provided in Table 93 below include only the current consumed by the 71M6543. Refer to the 71M6xxx Data Sheet for additional current required when using a 71M6x03 remote sensor. Table 93: Supply Current Performance Specifications Parameter Condition I1: V3P3A + V3P3SYS current, Normal Operation Polyphase: 4 Currents, 3 Voltages V3P3A = V3P3SYS = 3.
71M6543F/71M6543G Data Sheet 6.4.6 V3P3D Switch Table 94: V3P3D Switch Performance Specifications Parameter Condition On resistance – V3P3SYS to V3P3D On resistance – VBAT to V3P3D | IV3P3D | ≤ 1 mA | IV3P3D | ≤ 1 mA, VBAT>2.5V V3P3SYS = 3V V3P3D = 2.9V VBAT = 2.6V V3P3D = 2.5V V3P3D IOH, MSN V3P3D IOH, BRN 6.4.
71M6543F/71M6543G Data Sheet 6.4.9 2.5 V Voltage Regulator – Battery Power Table 97: Low-Power Voltage Regulator Performance Specifications Parameter Condition V2P5 V2P5 load regulation Voltage Overhead 2V − VBAT-VDD VBAT = 3.0 V - 3.8 V, V3P3 = 0 V, ILOAD = 0 mA VBAT = 3.3 V, V3P3 = 0 V, ILOAD = 0 mA to 1 mA ILOAD = 0ma, VBAT = 2.0 V, V3P3 = 0 V. Min Typ Max Unit 2.55 2.65 2.75 V 40 mV 200 mV Max Unit 1 μW 3 pF 6.4.
71M6543F/71M6543G Data Sheet 6.4.13 VLCD Generator Table 101: VLCD Generator Specifications Parameter Condition VSYS to VLCD switch impedance VBAT to VLCD switch impedance LCD Boost Frequency VLCD IOH current (VLCD(0)-VLCD(IOH)<0.25) V3P3 = 3.3 V, RVLCD=removed, LCD_BAT=0, LCD_VMODE[1:0]=0, ∆ILCD=10 µA V3P3 = 0 V, VBAT = 2.
71M6543F/71M6543G Data Sheet Parameter Condition Min Typ Max Unit LCD_DAC Error. VLCD-VLCDnom LCD_VMODE = 01, LCD_DAC[4:0] = 0, Zero Scale, no Boost LCD_CLK[1:0]=2, -0.15 0.15 V V3P3 = 3.6 V LCD_MODE[2:0]=6 -0.15 0.15 V V3P3 = 3.0 V -0.15 0.15 V VBAT = 4.0 V, V3P3 = 0 V, BRN Mode -0.45 0.15 V VBAT = 2.5 V, V3P3 = 0 V, BRN Mode LCD_DAC Error. VLCD-VLCDnom LCD_VMODE = 1, LCD_DAC[4:0] = 1F, Full Scale, with Boost, LCD mode LCD_CLK[1:0]=2, -0.15 0.15 V VBAT = 4.0 V, V3P3 = 0 V LCD_MODE[2:0]=6 -1.3 V VBAT = 2.
71M6543F/71M6543G Data Sheet 6.4.14 71M6543 VREF Table 102 shows the performance specifications for the 71M6543 ADC reference voltage (VREF). Table 102: 71M6543 VREF Performance Specifications Parameter VREF output voltage, VREF(22) VREF output voltage, VREF(22) Condition TA = 22 ºC Min Typ Max Unit 1.193 1.195 1.197 V PLL_FAST=0 1.195 V VREF chop step, trimmed VREF(CHOP=01) − VREF(CHOP=10) -10 10 mV VREF power supply sensitivity ΔVREF / ΔV3P3A V3P3A = 3.0 to 3.6 V -1.5 1.
71M6543F/71M6543G Data Sheet 6.4.15 ADC Converter Table 103: ADC Converter Performance Specifications Parameter Condition Recommended Input Range (Vin - V3P3A) Voltage to Current Crosstalk 6 10 *Vcrosstalk cos(∠Vin − ∠Vcrosstalk ) Vin (see note 1) Input Impedance, no pre-amp ADC Gain Error vs %Power Supply Variation 10 6 ∆Nout PK 357nV / VIN 100 ∆V 3P3 A / 3.
71M6543F/71M6543G Data Sheet Parameter Condition Min Typ Max Unit Note: 1. Guaranteed by design; not production tested. 2. Unless stated otherwise, the following test conditions apply to all the parameters provided in this table: FIR_LEN[1:0]=1, VREF_DIS=0, PLL_FAST=1, ADC_DIV=0, MUX_DIV=6, LSB values do not include the 9-bit left shift at CE input. 6.4.
71M6543F/71M6543G Data Sheet 6.5 Timing Specifications 6.5.1 Flash Memory Table 105: Flash Memory Timing Specifications Parameter Condition Flash write cycles Flash data retention -40 °C to +85 °C 25 °C 85 °C Min Typ Max 20,000 100 10 Cycles Years Flash byte writes between page or mass erase operations Write Time per Byte Page Erase (1024 bytes) Mass Erase 6.5.2 Unit 2 Cycles 21 21 21 µs ms ms SPI Slave Table 106.
71M6543F/71M6543G Data Sheet 6.5.4 RESET Pin Table 108: RESET Pin Timing Parameter Condition Reset pulse width Reset pulse fall time (see note 1) Note: 1. Guaranteed by design; not production tested. 6.5.
71M6543F/71M6543G Data Sheet 6.6 100-Pin LQFP Package Outline Drawing Controlling dimensions are in mm. 15.7(0.618) 16.3(0.641) 1 15.7(0.618) 16.3(0.641) Top View 14.000 +/- 0.200 MAX. 1.600 1.50 +/- 0.10 0.225 +/- 0.045 0.50 TYP. 0.10 +/- 0.10 Side View 0.
71M6543F/71M6543G Data Sheet 71M6543 Pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 71M6543F 71M6543G 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 XIN NC NC GNDA VBAT_RTC VBAT V3P3SYS IADC2 IADC3 IADC4 IADC5 IADC6 IADC7 GNDD V3P3D VDD ICE_E E_RXTX/SEG48 E_TCLK/SEG49 E_RST/SEG50 RX TX OPT_TX/SEGDIO51 SEGDIO52 SEGDIO53 NC SEGDIO17 SEGDIO16 SEGDIO15 SEGDIO14 SEGDIO13 SEGDIO12 SEGDIO11 SEGDIO10 SEGDIO9 SEGDIO8/DI SEGDIO7/YPULSE SEGDIO6/XPULSE SEGDIO5
71M6543F/71M6543G Data Sheet 6.8 71M6543 Pin Descriptions 6.8.1 71M6543 Power and Ground Pins Pin types: P = Power, O = Output, I = Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified under Section 6.8.4 I/O Equivalent Circuits.
71M6543F/71M6543G Data Sheet 6.8.2 71M6543 Analog Pins Pin types: P = Power, O = Output, I = Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified in Section 6.8.4. Table 111: 71M6543 Analog Pins Pin Name 87 86 IADC0 IADC1 68 67 IADC2 IADC3 Type IADC4 IADC5 64 63 IADC6 IADC7 84 VADC8 (VA) 83 VADC9 (VB) 82 VADC10 (VC) 88 VREF 75 76 148 XIN XOUT Function Differential or Single-Ended Analog Line Current Sense Inputs.
71M6543F/71M6543G Data Sheet 6.8.3 71M6543 Digital Pins Pin types: P = Power, O = Output, I = Input, I/O = Input/Output, N/C = no connect. The circuit number denotes the equivalent circuit, as specified in Section 6.8.4.
71M6543F/71M6543G Data Sheet Pin Name Type Circuit 91 RESET I 2 55 RX I 3 54 TX O 4 81 TEST I 7 90 PB I 3 26, 40, 48, 49, 50, 73, 74, 77, 78, 79 NC N/C — 150 Function Chip Reset. This input pin is used to reset the chip into a known state. For normal operation, this pin is pulled low. To reset the chip, this pin should be pulled high. This pin has an internal 30 μA (nominal) current source pulldown. No external reset circuitry is necessary. UART0 Input.
71M6543F/71M6543G Data Sheet 6.8.
71M6543F/71M6543G Data Sheet 7 Ordering Information 7.1 71M6543 Ordering Guide Refer to the 71M6xxx data sheet for the 71M6xx3 ordering guide information. Table 113. 71M6543 Ordering Guide Part Part Description (Package, TYP Accuracy) 100-pin LQFP Lead(Pb)-Free, 0.1% 100-pin LQFP 71M6543F Lead(Pb)-Free, 0.1% 100-pin LQFP 71M6543G Lead(Pb)-Free, 0.1% 100-pin LQFP 71M6543G Lead(Pb)-Free, 0.
71M6543F/71M6543G Data Sheet Appendix A: Acronyms AFE AMR ANSI CE DIO DSP FIR 2 IC ICE IEC MPU PLL RMS SFR SoC SPI TOU UART v2 Analog Front-End Automatic Meter Reading American National Standards Institute Compute Engine Digital I /O Digital Signal Processor Finite Impulse Response Inter-IC Bus In-Circuit Emulator International Electrotechnical Commission Microprocessor Unit (CPU) Phase-Locked Loop Root Mean Square Special Function Register System-on-Chip Serial Peripheral Interface Time of Use Universal
71M6543F/71M6543G Data Sheet Appendix B: Revision History REVISION NUMBER 1.0 1.1 REVISION DATE 1/11 3/11 1.2 4/11 2 10/13 DESCRIPTION Initial release Added the 71M6543G, 71M6543GH Removed the 17mW typ consumption at 3.
