71M6531D/F, 71M6532D/F Energy Meter IC Simplifying System Integration TM DATA SHEET 19-5374; Rev 1; 4/13 GENERAL DESCRIPTION FEATURES The 71M6531D/F and 71M6532D/F are highly integrated SOCs with an MPU core, RTC, FLASH and LCD driver.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Table of Contents 1 Hardware Description ....................................................................................................................... 10 1.1 Hardware Overview ................................................................................................................... 10 1.2 Analog Front End (AFE)............................................................................................................. 10 1.2.
FDS 6531/6532 005 2 3 4 Data Sheet 71M6531D/F-71M6532D/F Functional Description ..................................................................................................................... 54 2.1 Theory of Operation ................................................................................................................... 54 2.2 System Timing Summary ........................................................................................................... 55 2.3 Battery Modes .........
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 4.3.10 Other CE Parameters .................................................................................................... 95 4.3.11 CE Flow Diagrams ......................................................................................................... 95 5 Electrical Specifications................................................................................................................... 98 5.1 Absolute Maximum Ratings ....................
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Figures Figure 1: 71M6531D/F IC Functional Block Diagram ................................................................................... 8 Figure 2: 71M6532D/F IC Functional Block Diagram ................................................................................... 9 Figure 3: General Topology of a Chopped Amplifier ..................................................................................
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Tables Table 1: Inputs Selected in Regular and Alternate Multiplexer Cycles ....................................................... 11 Table 2: ADC Resolution............................................................................................................................. 12 Table 3: ADC RAM Locations .....................................................................................................................
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Table 53: I/O RAM Map in Functional Order............................................................................................... 72 Table 54: I/O RAM Description - Alphabetical ............................................................................................ 77 Table 55: CE EQU[2:0] Equations and Element Input Mapping ................................................................. 89 Table 56: CESTATUS (CE RAM 0x80) Bit Definitions ..
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Figure 1: 71M6531D/F IC Functional Block Diagram 8 Rev 2
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Figure 2: 71M6532D/F IC Functional Block Diagram Rev 2 9
Data Sheet 71M6531D/F-71M6532D/F 1 Hardware Description 1.1 Hardware Overview FDS 6531/6532 005 The 71M6531D/F and 71M6532D/F single-chip energy meters integrates all primary functional blocks required to implement a solid-state electricity meter.
FDS 6531/6532 005 1.2.2 Data Sheet 71M6531D/F-71M6532D/F Input Multiplexer The input multiplexer supports up to four input signals that are applied to pins IA (IAP/IAN), VA, IB (IBP/IBN), and VB of the device. Additionally, using the alternate multiplexer selection, it has the ability to select temperature and the battery voltage. The multiplexer can be operated in two modes: • • During a normal multiplexer cycle, the signals from the IA (IAP/IAN), IB (IBP/IBN), VA and VB pins are selected.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 The duration of each multiplexer state depends on the number of ADC samples processed by the FIR, which is set by FIR_LEN[1:0]. Each multiplexer state will start on the rising edge of CK32. The MUX_CTRL signal sends an FIR_START command to begin the calculation of a sample value from the ADC bit stream by the FIR.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F A Vinp B A Vinn A + G - B B A B Voutp Voutn CROSS Figure 3: General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 the number of multiplexer frames in an accumulation interval is always even. Operation with CHOP_E[1:0] = 00 does not require control of the chopping mechanism by the MPU while eliminating the offset for temperature measurement. In the second toggle state, CHOP_E[1:0] = 11, no ALT frame is forced during the last multiplexer cycle in an accumulation interval and CROSS always toggles near the end of each multiplexer frame.
FDS 6531/6532 005 1.3 Data Sheet 71M6531D/F-71M6532D/F Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include: • • • • • • • • Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when multiplied with the constant sample time).
Data Sheet 71M6531D/F-71M6532D/F 1.3.1 FDS 6531/6532 005 Meter Equations The 71M6531D/F and 71M6532D/F provide hardware assistance to the CE in order to support various meter equations. This assistance is controlled through I/O RAM location EQU[2:0] (equation assist). The Compute Engine (CE) firmware for residential configurations implements the equations listed in Table 5. EQU[2:0] specifies the equation to be used based on the number of phases used for metering.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Since the FIFO resets at the beginning of each MUX frame, the user must specify PLS_INTERVAL so that all of the pulse updates are output before the MUX frame completes. For instance, if the CE code outputs 5 updates per MUX interval and if the MUX interval is 1950 cycles long, the ideal value for the interval is 1950/5/4 = 97.5. If PLS_INTERVAL = 98, the fifth output will occur too late and be lost. In this case, the proper value for PLS_INTERVAL is 97.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 For example, PRE_SAMPS[1:0] = 42 and SUM_CYCLES[5:0] = 50 will establish 2100 samples per accumulation cycle. PRE_SAMPS[1:0] = 100 and SUM_CYCLES[5:0] = 21 will result in the exact same accumulation cycle of 2100 samples or 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available.
FDS 6531/6532 005 1.4 Data Sheet 71M6531D/F-71M6532D/F 80515 MPU Core The 71M6531D/F and 71M6532D/F include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 10-MHz clock results in a processing throughput of 10 MIPS. The 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (SFR PDATA provides the upper 8 bytes for the MOVX A,@Ri instruction). Internal and External Memory Map Table 7 shows the address, type, use and size of the various memory components. Only the memory ranges shown in Table 7 contain physical memory.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction MOVX A,@Ri or MOVX @Ri,A. Internal Data Memory Map and Access The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory address is always 1 byte wide. Table 8 shows the internal data memory map.
Data Sheet 71M6531D/F-71M6532D/F 1.4.3 FDS 6531/6532 005 Generic 80515 Special Function Registers Table 10 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional descriptions of the registers can be found at the page numbers listed in the table.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Accumulator (ACC, A, SFR 0xE0): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC. B Register (SFR 0xF0): The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Table 12: Port Registers Register P0 DIR0 P1 DIR1 P2 DIR2 SFR R/W Description Address 0x80 R/W Register for port 0 read and write operations. 0xA2 R/W Data direction register for port 0. Setting a bit to 1 indicates that the corresponding pin is an output. 0x90 R/W Register for port 1 read and write operations. 0x91 R/W Data direction register for port 1. 0xA0 R/W Register for port 2 read and write operations. 0xA1 R/W Data direction register for port 2.
FDS 6531/6532 005 Register (Alternate Name) ERASE (FLSH_ERASE) FL_BANK PGADDR (FLSH_PGADR[5:0]) FLSHCRL IFLAGS Data Sheet 71M6531D/F-71M6532D/F SFR Address R/W 0x94 W 0xB6[2:0] R/W 0xB7 R/W 0xB2[0] FLSH_PWE 0xB2[1] FLSH_MEEN 0xB2[6] SECURE 0xB2[7] PREBOOT R 0xE8[0] IE_XFER R/W 0xE8[1] IE_RTC R/W 0xE8[2] FWCOL1 R/W 0xE8[3] FWCOL0 R/W 0xE8[4] IE_PB R/W 0xE8[5] IE_WAKE R/W 0xE8[6] PLL_RISE R/W 0xE8[7] PLL_FALL R/W 0xF8[6:0] INTBITS (INT0 … INT6) Bit Field Name 0xF8
Data Sheet 71M6531D/F-71M6532D/F 1.4.5 FDS 6531/6532 005 Instruction Set All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set and of the associated op-codes is contained in the 71M653X Software User’s Guide (SUG). 1.4.6 UARTs The 71M6531D/F and 71M6532D/F include a UART (UART0) that can be programmed to communicate with a variety of AMR modules. A second UART (UART1) is connected to the optical port, as described in Section 1.5.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals for inter-processor communication in multi-processor systems. In this case, the slave processors have bit SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs th the slave’s address, it sets the 9 bit to 1, causing a serial port receive interrupt in all the slaves.
Data Sheet 71M6531D/F-71M6532D/F Bit Symbol S1CON[2] RB81 S1CON[1] TI1 S1CON[0] RI1 FDS 6531/6532 005 Function th In Modes A and B, it is the 9 data bit received. In Mode B, if SM21 is 0, RB81 is the stop bit. Must be cleared by software Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Table 21: Allowed Timer/Counter Mode Combinations Timer 1 Timer 0 - mode 0 Timer 0 - mode 1 Timer 0 - mode 2 Mode 0 Mode 1 Mode 2 Yes Yes Not allowed Yes Yes Not allowed Yes Yes Yes Table 22: TMOD Register Bit Description (SFR 0x89) Bit Symbol Timer/Counter 1: TMOD[7] Gate TMOD[6] C/T TMOD[5:4] M1:M0 Timer/Counter 0: TMOD[3] Gate TMOD[2] C/T TMOD[1:0] M1:M0 Function If TMOD[7] is set, external input signal control is enabled for Counter
Data Sheet 71M6531D/F-71M6532D/F 1.4.8 FDS 6531/6532 005 WD Timer (Software Watchdog Timer) There is no internal software watchdog timer. Use the standard watchdog timer instead (see 1.5.16 Hardware Watchdog Timer). 1.4.9 Interrupts The 80515 MPU provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special function register (TCON, IRCON and SCON).
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Table 25: The IEN1 Bit Functions (SFR 0xB8) Bit IEN1[7] Symbol – Function Not used. IEN1[6] – Not used.
Data Sheet 71M6531D/F-71M6532D/F IRCON[1] IRCON[0] IEX2 – FDS 6531/6532 005 1 = External interrupt 2 occurred and has not been cleared. Not used. TF0 and TF1 (Timer 0 and Timer 1 overflow flags) will be automatically cleared by hardware when the service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service routine is called). External MPU Interrupts The seven external interrupts are the interrupts external to the 80515 core, i.e.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Interrupt Enable Name Location EX4 EX5 EX6 EX_XFER EX_RTC IEN_WD_NROVF IEN_SPI SFR B8[3] SFR B8[4] SFR B8[5] 2002[0] 2002[1] 20B0[0] 20B0[4] EX_FWCOL 2007[4] EX_PLL 2007[5] Interrupt Flag Name Location IEX4 IEX5 IEX6 IE_XFER IE_RTC WD_NROVF_FLAG SPI_FLAG IE_FWCOL0 IE_FWCOL1 IE_PLLRISE IE_PLLFALL IE_WAKE IE_PB SFR C0[3] SFR C0[4] SFR C0[5] SFR E8[0] SFR E8[1] 20B1[0] 20B1[4] SFR E8[3] SFR E8[2] SFR E8[6] SFR E8[7] SFR E8[5] SFR E8[4] Interrupt Desc
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Table 34: Interrupt Priority Registers (IP0 and IP1) Register Address Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 SFR 0xA9 Bit 7 (MSB) – – IP0[5] IP0[4] IP0[3] IP0[2] IP0[1] Bit 0 (LSB) IP0[0] IP0 IP1 SFR 0xB9 – – IP1[5] IP1[4] IP1[3] IP1[2] IP1[1] IP1[0] External interrupt 0 Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F External Source Internal Source 0 DIO DIO status changed UART1 (optical) Timer 0 SPI I/F 2 flash write busy DIO 3 CE_BUSY PLL status changed 4 TCON.1 (IE0) S1CON.0 (RI1) S1CON.1 (TI1) TCON.5 (TF0) SPI_FLAG Write attempt, CE Flash busy Write CE code start, Collision 1 Individual Flags DIO status changed IE_FWCOL0 IE_FWCOL1 TCON.3 (IE1) Timer 1 TCON.7 (TF1) IE_PLLRISE PLL OK IE_PLLFALL S0CON.0 (RI0) S0CON.
Data Sheet 71M6531D/F-71M6532D/F 1.5 On-Chip Resources 1.5.1 Oscillator FDS 6531/6532 005 The oscillator of the 71M6531D/F and 71M6532D/F drives a standard 32.768 kHz watch crystal. These crystals are accurate and do not require a high-current oscillator circuit. The oscillator of the 71M6531D/F and 71M6532D/F has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F The PLL generates a 2x emulator clock which is controlled by the ECK_DIS bit. Since clock noise from this feature may disturb the ADC, it is recommended that this option be avoided when possible. The MPU clock frequency CKMPU is determined by another divider controlled by the I/O RAM field (MPU_DIV+2) Hz where MPU_DIV[2:0] varies from 0 to 6. The circuit MPU_DIV[2:0] and can be set to MCK/2 also generates the 2 x CKMPU clock for use by the emulator.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 To adjust the clock rate using the digital rate adjust, the appropriate values must be written to PREG[16:0] and QREG[1:0]. The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency by ∆ ppm, calculate PREG[16:0] and QREG[1:0] using the following equation: 32768 ⋅ 8 4 ⋅ PREG + QREG = floor + 0.5 −6 1 + ∆ ⋅ 10 For example, for a shift of -988 ppm, 4⋅PREG + QREG = 262403 = 0x40103.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F The MPU cannot write to flash while the CE is executing its code from flash. Two interrupts warn of collisions between the MPU firmware and the CE timing. If a flash write operation is attempted while the CE is busy, the flash write will not execute and the FWCOL0 interrupt will be issued.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Table 38: Bank Switching with FL_BANK[2:0] 71M6531D FL_BANK [1:0] 000 001 010 011 71M653XF FL_BANK [2:0] 000 001 010 011 100 101 110 111 Address Range for Lower Bank (0x000-0x7FFF) 0x0000-0x7FFF Address Range for Upper Bank (0x8000-0xFFFF) 0x0000-0x7FFF 0x8000-0xFFFF 0x10000-0x17FFF 0x18000-0x1FFFF 0x20000-0x217FF 0x28000-0x2FFFF 0x30000-0x37FFF 0x38000-0x3FFFF Program Security When enabled, the security feature limits the ICE to global flash erase o
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F VARPULSE 3 2 1 WPULSE from OPT_TX UART MOD A OPT_TXINV OPT_TXMOD OPT_FDC DIO2 B EN DUTY 2 OPT_TXMOD = 0 A A B B V3P3 Internal OPT_TX 0 OPT_TXE[1:0] OPT_TXMOD = 1, OPT_FDC = 2 (25%) 1/38kHz Figure 9: Optical Interface 1.5.7 Digital I/O – 71M6531D/F The 71M6531D/F includes up to 22 pins of general-purpose digital I/O. These pins are compatible with 5 V inputs (no current limiting resistors are needed).
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Table 39: Data/Direction Registers and Internal Resources for DIO 1-15 (71M6531D/F) DIO PB 1 2 – 4 5 6 7 8 9 10 11 12 13 14 15 LCD Segment – – – – 24 25 26 27 28 29 30 31 32 33 34 35 Pin number 65 60 3 – 39 40 41 42 43 44 45 46 68 30 21 22 – – – – 0 1 – – – Y Y Configuration (DIO or LCD segment) 0 Data Register Direction Register Internal Resources Configurable – – 2 3 4 5 6 7 0 1 2 3 LCD_B
FDS 6531/6532 005 1.5.8 Data Sheet 71M6531D/F-71M6532D/F Digital I/O – 71M6532D/F The 71M6532D/F includes up to 43 pins of general-purpose digital I/O. These pins are compatible with 5 V inputs (no current limiting resistors are needed).
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Table 44: Data/Direction Registers and Internal Resources for DIO 40-51 (71M6532D/F) 68 69 70 71 Pin number 95 97 98 40 31 38 – 22 23 24 25 50 0 1 – 3 4 5 LCD_BITMAP[71:64] 6 7 Configuration (DIO or LCD segment) 4 5 6 7 LCD_BITMAP[63:56] Data Register Direction Register 0 = input, 1 = output – LCD_SEG71[0] 67 – LCD_SEG71[3] – LCD_SEG70[0] 65 LCD_SEG70[3] 64 LCD_SEG69[0] 63 LCD_SEG69[3] 62 LCD_SEG68[0] 61 LCD_SEG68
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Additionally, if DIO6 and DIO7 are configured as DIO and defined as outputs, they can be used as dedicated pulse outputs (WPULSE = DIO6, VARPULSE = DIO7) using the DIO_PW and DIO_PV bits. In this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5 can be configured to implement the EEPROM Interface. The PB pin is a dedicated digital input.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Section 4.1 I/O RAM and SFR Map – Functional Order. The LCD drivers are supported by the four common pins (COM0 – COM3). 1.5.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Two-Pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is multiplexed onto the DIO4 (SCK) and DIO5 (SDA) pins and is selected by setting DIO_EEX[1:0] = 01. The MPU communicates with the interface through the SFR registers EEDATA and EECTRL. If the MPU wishes to write a byte of data to the EEPROM, it places the data in EEDATA and then writes the Transmit code to EECTRL.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Table 48: EECTRL Bits for the 3-Wire Interface Control Bit 7 6 5 4 3:0 Read/ Description Write WFR W Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed until a rising edge is seen on the data line. This bit can be used during the last byte of a Write command to cause the INT5 interrupt to occur when the EEPROM has finished its internal write sequence. This bit is ignored if HiZ = 0.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F EECTRL Byte Written INT5 CNT Cycles (8 shown) READ SCLK (output) SDATA (input) D7 D6 SDATA output Z D5 D4 D3 D2 D1 D0 (HiZ) BUSY (bit) Figure 13: 3-Wire Interface. Read Command.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Table 49: SPI Command Description Command 11xx xxxx ADDR Byte0 ... ByteN 10xx xxxx ADDR Byte0 ... ByteN Description Read data starting at ADDR. The ADDR will auto-increment until PCSZ is raised. Upon completion: SP__CMD=11xx xxxx, SP_ADDR=ADDR+N+1. No MPU interrupt is generated if the command is 1100 0000. Otherwise, an SPI interrupt is generated. Write data starting at ADDR. The ADDR will auto-increment until PCSZ is raised.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Name SPI0 SPI1 VERSION CHIP_ID TRIMSEL TRIMX TRIM SERIAL READ Address (hex) 20B0 20B1 20C8 20C9 20FD 20FE 20FF 8 bit CMD Bit Range 4, 0 4, 0 7:0 7:0 4:0 0 7:0 Read/Write RW R R R RW RW RW DATA[ADDR] 16 bit Address DATA[ADDR+1] PCSZ Extended Read . . .
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 1.5.16 Hardware Watchdog Timer V1 V3P3 V3P3 - 10mV WDT disabled V3P3 400mV Normal operation, WDT enabled VBIAS Battery modes An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6531D/F and 71M6532D/F. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1.5 seconds.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F 1.5.17 Test Ports (TMUXOUT pin) One of the digital or analog signals listed in Table 51 can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled with the I/O RAM field TMUX[4:0] (0x20AA[4:0]), as shown in Table 51.
Data Sheet 71M6531D/F-71M6532D/F 2 Functional Description 2.
FDS 6531/6532 005 2.2 Data Sheet 71M6531D/F-71M6532D/F System Timing Summary Figure 19 summarizes the timing relationships between the input MUX states, the CE_BUSY signal and the two serial output streams. In this example, MUX_DIV[3:0] = 4 and FIR_LEN[1:0] = 2 (384 CE cycles, 3 CK32 cycles per conversion), resulting in 13 CK32 cycles per multiplexer frame.
Data Sheet 71M6531D/F-71M6532D/F 2.3 FDS 6531/6532 005 Battery Modes Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode means that the part is operating with system power and that the internal PLL is stable. This mode is the normal operation mode where the part is capable of measuring energy. When system power is not available (i.e. when V1
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F To facilitate transition to SLEEP mode, which is useful when an unprogrammed IC is mounted on a PCB with a battery installed, the production test programs the following six-byte sequence into the flash location starting at address 0x00000: 0x74 - 0x40 - 0x90 - 0x20 - 0xA9 - 0xF0.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 can voluntarily enter LCD or SLEEP modes. When system power is restored, the part will automatically transition from any of the battery modes to MISSION mode, once the PLL has settled. The MPU will run at 7/8 of the crystal clock rate. This permits the UARTs to be operated at 300 bd. In this mode, the MPU clock has substantial short-term jitter. The value of MPU_DIV[2:0] will be remembered (not changed) as the part enters and exits BROWNOUT.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns Figure 23: Power-Up Timing with V3P3SYS and VBAT tied together Rev 2 59
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Figure 24: Power-Up Timing with VBAT only 2.4 Fault and Reset Behavior 2.4.1 Reset Mode When the RESET pin is pulled high, all digital activity stops. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are set to their default states. As long as V1, the input voltage at the power fault block, is greater than VBIAS, the internal 2.5 V regulator will continue to provide power to the digital section.
FDS 6531/6532 005 2.5 Data Sheet 71M6531D/F-71M6532D/F Wake-Up Behavior As described above, the part will always wake up in MISSION mode when system power is restored. Additionally, the part will wake up in BROWNOUT mode when PB rises (push button is pressed) or when a timeout of the wake-up timer occurs. 2.5.1 Wake on PB If the part is in SLEEP or LCD mode, it can be awakened by a rising edge on the PB pin. This pin is normally pulled to GND and can be pulled high by a push button depression.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Figure 26 illustrates the CE/MPU data flow. Pulses IRQ Samples CE PreProcessor Processed Metering Data MPU Data Post Processor I/O RAM (Configuration RAM) Figure 26: MPU/CE Data Flow 2.7 CE/MPU Communication Figure 27 shows the functional relationships between the CE and the MPU. The CE is controlled by the MPU via shared registers in the I/O RAM and in RAM.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F 3 Application Information 3.1 Connection of Sensors Figure 28 through Figure 30 show how resistive dividers, current transformers, Rogowski coils and resistive shunts are connected to the voltage and current inputs of the 71M6531. The analog input pins of the 71M65XX are designed for sensors with low source impedance. RC filters with resistance values higher than those implemented in the Demo Boards should be avoided.
Data Sheet 71M6531D/F-71M6532D/F 3.3 FDS 6531/6532 005 Temperature Measurement Measurement of absolute temperature uses the on-chip temperature sensor and applying the following formula: T= ( N (T ) − N n ) + Tn Sn In the above formula, T is the temperature in °C, N(T) is the ADC count at temperature T, Nn is the ADC count at 25°C, Sn is the sensitivity in LSB/°C as stated in the Electrical Specifications and Tn is +25 °C.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Figure 31: Error Band for VREF over Temperature 3.4.2 Temperature Compensation for VREF The bandgap temperature is used to digitally compensate the power outputs for the temperature dependence of VREF, using the CE register GAIN_ADJ. Since the band gap amplifier is chopper-stabilized, the most significant long-term drift mechanism in the voltage reference is removed. The following formula is used to determine the GAIN_ADJ value of the CE.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 to the meter. 3.5 Connecting LCDs The 71M6531D/F and 71M6532D/F have an on-chip LCD controller capable of controlling static or multiplexed LCDs. Figure 32 shows the basic connection for an LCD. The following dedicated and multi-use pins can be assigned as LCD segment pins for the 71M6531D/F: • • • 12 dedicated LCD segment pins: SEG0 to SEG2, SEG7, SEG8, SEG12 to SEG18.
FDS 6531/6532 005 3.7 Data Sheet 71M6531D/F-71M6532D/F Connecting Three-Wire EEPROMs µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as shown in Figure 34 and described below: • • • • • DIO5 connects to both the DI and DO pins of the three-wire device. The CS pin must be connected to a vacant DIO pin of the 71M6531. In order to prevent bus contention, a 10 kΩ to resistor is used to separate the DI and DO signals.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 The polarity of the OPT_TX and OPT_RX pins can be inverted with the configuration bits, OPT_TXINV and OPT_RXINV, respectively. The OPT_TX output may be modulated at 38 kHz when system power is present. Modulation is not available in BROWNOUT mode. The OPT_TXMOD bit enables modulation. The duty cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5% and 6.25% duty cycle. A 6.25% duty cycle means OPT_TX is low for 6.25% of the period.
FDS 6531/6532 005 3.11 Data Sheet 71M6531D/F-71M6532D/F Connecting the Reset Pin Even though a functional meter will not necessarily need a reset switch, it is useful to have a reset pushbutton for prototyping as shown in Figure 38, left side. The RESET signal may be sourced from V3P3SYS (functional in MISSION mode only), V3P3D (MISSION and BROWNOUT modes), or VBAT (all modes, if a battery is present), or from a combination of these sources, depending on the application.
Data Sheet 71M6531D/F-71M6532D/F Power Supply FDS 6531/6532 005 V3P3SYS V3P3A DIO Battery or Super-Cap + - VBAT 71M6531/71M6532 Figure 40: Connecting a Battery As mentioned in section 2.3, meters equipped with batteries need to contain code that transitions the chip to SLEEP mode as soon as the battery is attached in production. Otherwise, remaining in BROWNOUT mode would add unnecessary drain to the battery. 3.
FDS 6531/6532 005 3.17 Data Sheet 71M6531D/F-71M6532D/F Meter Calibration Once the 71M6531D/F or 71M6532D/F energy meter device has been installed in a meter system, it must be calibrated. A complete calibration includes the following: • • • • Calibration of the metrology section, i.e. calibration for tolerances of the current sensors, voltage dividers and signal conditioning components as well as of the internal reference voltage (VREF). Establishment of the reference temperature (Section 3.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 4 Firmware Interface 4.1 I/O RAM and SFR Map – Functional Order In Table 54, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits have no memory storage, writing them has no effect, and reading them always returns zero. Reserved bits may be in use and should not be changed from the values given in parentheses.
FDS 6531/6532 005 Name Digital I/O: Addr Data Sheet 71M6531D/F-71M6532D/F Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DIO_RRX[2:0] 20AF U DIO0 DIO_EEX[1:0] OPT_RXDIS OPT_RXINV DIO_PW DIO_PV OPT_TXMOD OPT_TXINV 2008 DIO1 DIO_R1[2:0]† DI_RPB[2:0] 2009 U U DIO2 DIO_R2[2:0] 200A U U U DIO3 DIO_R5[2:0] DIO_R4[2:0] 200B U U DIO4 DIO_R7[2:0] DIO_R6[2:0] 200C U U DIO5 DIO_R9[2:0] DIO_R8[2:0] 200D U U DIO6 DIO_R11[2:0] DIO_R10[2:0] 200E U U DIO_PX DIO_PY 200F R(0) R (0) U U DIO7 DIO_0[7:1] DIO_0[0]† SF
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Name Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCD Display Interface: MUX_SYNC_E LCDX BME 2020 R (0) R (0) U LCDY LCD_Y LCD_E LCD_MODE[2:0] LCD_CLK[1:0] 2021 U LCD_MAP0 2023 LCD_BITMAP[31:24] LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_MAP1 2024 [39]‡ [38]‡ [37] [36]‡ [35] [34] [33] [32] LCD_MAP2 2025 LCD_BITMAP[47:40]‡ LCD_BITMAP LCD_BITMAP LCD_BITMAP LCD_MAP3 2026 U [50]‡ [49] [48]† LCD_BITMAP L
FDS 6531/6532 005 Name Addr LCD27 204B LCD28 204C LCD29 204D LCD30 204E … … LCD33 2053 LCD36 2054 LCD37 2055 LCD38 2056 … … LCD41 2059 LCD_BLNK 205A RTM: RTM0H 2060 RTM0L 2061 RTM1H 2062 RTM1L 2063 RTM2H 2064 RTM2L 2065 RTM3H 2066 RTM3L 2067 SPI Interface: SPI… 2070 SP_CMD 2071 SP_ADH 2072 SP_ADL 2073 Pulse Generator: PLS_W 2080 PLS_I 2081 ADC MUX: SLOT0 2090 SLOT1 2091 SLOT2 2092 SLOT3 2093 SLOT4 2094 Rev 2 Data Sheet 71M6531D/F-71M6532D/F Bit 7 Bit 6 Bit 5 LCD_SEG69[3:0]‡ LCD_SEG70[3:0]‡ LCD_SEG71[3:0]‡
Data Sheet 71M6531D/F-71M6532D/F Name Addr Bit 7 Bit 6 Bit 5 SLOT5 SLOT1_ALTSEL 2096 SLOT6 SLOT3_ALTSEL 2097 SLOT7 2098 R SLOT8 2099 R SLOT9 209A R SPI Interrupt: SPI0 20B0 U SPI1 20B1 U General-Purpose Nonvolatile Registers: GP0 20C0 … … GP7 20C7 VERSION 20C8 Serial EEPROM: EEDATA SFR 9E EECTRL SFR 9F FDS 6531/6532 005 Bit 4 Bit 3 IEN_SPI SPI_FLAG Bit 2 Bit 1 SLOT0_ALTSEL SLOT2_ALTSEL R R R U U Bit 0 IEN_WD_NROVF WD_NROVF_FLAG GPO[7:0] … GP7[7:0] VERSION[7:0] EEDATA[7:0] EECTRL[7:0] † 71M6531D/F on
FDS 6531/6532 005 4.2 Data Sheet 71M6531D/F-71M6532D/F I/O RAM Description – Alphabetical Order The following conventions apply to the descriptions in this table: • • • • Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining bits are mapped to 2xxx.
Data Sheet 71M6531D/F-71M6532D/F Name Location FDS 6531/6532 005 Reset Wake Dir CKOUT_E 2004[4] 0 0 R/W COMPSTAT DI_RPB[2:0] DIO_R1[2:0] DIO_R2[2:0] DIO_R4[2:0] DIO_R5[2:0] DIO_R6[2:0] DIO_R7[2:0] DIO_R8[2:0] DIO_R9[2:0] DIO_R10[2:0] DIO_R11[2:0] DIO_RRX[2:0] 2003[0] 2009[2:0] 2009[6:4] 200A[2:0] 200B[2:0] 200B[6:4] 200C[2:0] 200C[6:4] 200D[2:0] 200D[6:4] 200E[2:0] 200E[6:4] 20AF[2:0] – 0 0 0 0 0 0 0 0 0 0 0 0 – 0 0 0 0 0 0 0 0 0 0 0 0 R R/W DIO_DIR0[7:1] SFR A2 [7:1] 0 – R/W DIO_DIR1[7
FDS 6531/6532 005 Name Data Sheet 71M6531D/F-71M6532D/F Location Reset Wake Dir DIO_EEX[1:0] 2008[7:6] 0 0 R/W DIO_PV DIO_PW DIO_PX DIO_PY EEDATA[7:0] EECTRL[7:0] 2008[2] 2008[3] 200F[3] 200F[2] SFR 9E SFR 9F 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W ECK_DIS 2005[5] 0 0 R/W EQU[2:0] EX_XFR EX_RTC EX_FWCOL EX_PLL 2000[7:5] 2002[0] 2002[1] 2007[4] 2007[5] 0 0 0 0 0 0 0 0 0 0 R/W R/W Description When set, converts DIO4 and DIO5 to interface with external EEPROM.
Data Sheet 71M6531D/F-71M6532D/F Name FDS 6531/6532 005 Location Reset Wake Dir FLSH_ERASE [7:0] SFR 94[7:0] 0 0 W FLSH_MEEN SFR B2[1] 0 0 W FLSH_PGADR [5:0] SFR B7 [7:2] 0 0 W FLSH_PWE SFR B2[0] 0 0 R/W GP0 … GP7 IE_FWCOL0 IE_FWCOL1 20C0 … 20C7 SFR E8[2] SFR E8[3] 0 … 0 0 0 NV … NV 0 0 R/W R/W R/W IE_PB SFR E8[4] 0 – R/W IE_PLLRISE SFR E8[6] 0 0 R/W IE_PLLFALL SFR E8[7] 0 0 R/W IEN_SPI 20B0[4] 0 – R/W 80 Description Flash Erase Initiate. (Default = 0x00).
FDS 6531/6532 005 Name Location IEN_WD_NROVF 20B0[0] IE_XFER SFR E8[0] IE_RTC SFR E8[1] Data Sheet 71M6531D/F-71M6532D/F Reset 0 0 0 Wake 0 0 0 Dir R/W R/W IE_WAKE SFR E8[5] 0 – R/W INTBITS SFR F8[6:0] – – R/W LCD_BITMAP [31:24] 2023 0 L R/W LCD_BITMAP [39:32] 2024 0 L R/W LCD_BITMAP [55:48] 2026 0 L R/W LCD_BITMAP [63:56] 2027 0 L R/W LCD_BITMAP [71:64] 2028 0 L R/W 0 L R/W LCD_BLKMAP19 205A[7:4] [3:0] LCD_BLKMAP18 205A[3:0] [3:0] LCD_CLK[1:0] Rev 2 2021[1:0] 0
Data Sheet 71M6531D/F-71M6532D/F Name Location Reset FDS 6531/6532 005 Wake Dir LCD_DAC[2:0] 20AB[3:1] 0 L R/W LCD_E 2021[5] 0 L R/W Description LCD contrast control DAC. Adjusts the LCD voltage in steps of 0.2 V from V3P3SYS (mission mode) or VBAT (BROWNOUT/LCD modes). LCD_DAC[2:0] 000 001 010 011 100 101 110 111 Resulting LCD Voltage V3P3 or VBAT V3P3 or VBAT – 0.2V V3P3 or VBAT – 0.4V V3P3 or VBAT – 0.6V V3P3 or VBAT – 0.8V V3P3 or VBAT – 1.0V V3P3 or VBAT – 1.2V V3P3 or VBAT – 1.
FDS 6531/6532 005 Name LCD_SEG33[3:0] … LCD_SEG35[3:0] LCD_SEG37[3:0] LCD_SEG39[3:0] … LCD_SEG41[3:0] Data Sheet 71M6531D/F-71M6532D/F LCD_SEG48[7:4] … LCD_SEG49[7:4] Location 2051[3:0] … 2053[3:0] 2055[3:0] 2057[3:0] … 2059[3:0] 2036[7:4] … 2037[7:4] LCD_SEG63[7:4] … LCD_SEG66[7:4] 2045[7:4] … 2048[7:4] LCD_SEG71[7:4] … LCD_SEG73[7:4] 204D[7:4] … 204F[7:4] LCD_Y 2021[6] 0 L R/W M26MHZ M40MHZ 2005[4] 2005[0] 0 0 0 0 R/W R/W MPU_DIV[2:0] Rev 2 2004[2:0] Reset 0 … 0 0 0 … 0 0 … 0 0 … 0 0
Data Sheet 71M6531D/F-71M6532D/F Name Location FDS 6531/6532 005 Reset Wake Dir MUX_ALT 2005[2] 0 0 R/W MUX_DIV[3:0] MUX_SYNC_E 209D[3:0] 2020[7] 0 0 0 0 R/W R/W OPT_FDC[1:0] 2007[1:0] 0 0 R/W OPT_RXDIS 2008[5] 0 0 R/W OPT_RXINV 2008[4] 0 0 R/W OPT_TXE[1:0] 2007[7:6] 00 00 R/W OPT_TXINV 2008[0] 0 0 R/W OPT_TXMOD 2008[1] 0 0 R/W PLL_OK 2003[6] 0 0 R FF FF R/W 0 0 R/W PLS_MAXWIDTH 2080[7:0] [7:0] PLS_INTERVAL [7:0] 84 2081[7:0] Description The MPU as
FDS 6531/6532 005 Name Data Sheet 71M6531D/F-71M6532D/F Location Reset Wake Dir PLS_INV 2004[6] 0 0 R/W PREBOOT SFRB2[7] – – R PREG[16:0] 201C[2:0] 201D[7:0] 201E[7:2] 4 0 0 NV NV NV R/W R/W R/W PRE_SAMPS[1:0] 2001[7:6] 0 0 R/W QREG[1:0] RST_SUBSEC RTCA_ADJ[6:0] 201E[1:0] 2010[0] 2011[6:0] 0 0 40 0 0 – R/W R/W R/W RTC_SEC[5:0 RTC_MIN[5:0] RTC_HR[4:0] RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] RTC_YR[7:0] 2015 2016 2017 2018 2019 201A 201B * * * * * * * NV NV NV NV NV NV NV RTM_E
Data Sheet 71M6531D/F-71M6532D/F Name Location FDS 6531/6532 005 Reset Wake Dir SECURE SFRB2[6] 0 – R/W SEL_IAN 20AC[1] 0 0 R/W SEL_IBN 20AC[5] 0 0 R/W SLEEP 20A9[6] 0 0 W SLOT0_SEL[3:0] SLOT1_SEL[3:0] SLOT2_SEL[3:0] SLOT3_SEL[3:0] SLOT0_ALTSEL [3:0] SLOT1_ALTSEL [3:0] SLOT2_ALTSEL [3:0] SLOT3_ALTSEL [3:0] SP_ADDR[15:8] SP_ADDR[7:0] SP_CMD SPE 2090[3:0] 2090[7:4] 2091[3:0] 2091[7:4] 2096[3:0] 0 1 2 3 A 0 1 2 3 A 2096[7:4] 1 1 2097[3:0] 2 B 2097[7:4] 3 3 2072[7:0] 2073[
FDS 6531/6532 005 Name Data Sheet 71M6531D/F-71M6532D/F Location Reset Wake Dir TRIMSEL[3:0] 20FD[3:0] 0 0 R/W VERSION[7:0] 2006 20C8 – – – – R R Description Selects the trim fuse to be read with the TRIM register: TRIMSEL[3:0] 1 2004[7] 2004[3] 0 0 0 0 R/W R/W WAKE_ARM 20A9[7] 0 – W WAKE_PRD WAKE_RES WD_NROVF_ FLAG 20A9[2:0] 20A9[3] 20B1[0] 001 0 – – – 0 R/W R/W R/W WD_RST SFR F8[7] 0 0 W WD_OVF 2002[2] 0 0 R/W WE 201F[7:0] – – W WRPROT_BT SFR B2[5] 0 0 WRPR
Data Sheet 71M6531D/F-71M6532D/F 4.3 CE Interface Description 4.3.1 CE Program FDS 6531/6532 005 The CE performs the precision computations necessary to accurately measure energy. Different code variations are used for EQU[2:0] = 0 and EQU[2:0] = 1 or 2. The computations include offset cancellation, products, product smoothing, product summation, frequency detection, VAR calculation, sag detection, peak detection and voltage phase measurement.
FDS 6531/6532 005 • • • • Data Sheet 71M6531D/F-71M6532D/F Select the values for SLOT0_SEL[3:0] = 0, SLOT1_SEL[3:0] = 1, SLOT2_SEL[3:0] = 2, SLOT3_SEL[3:0] =3 Select the values for SLOT0_ALTSEL[3:0] = 0x0A, SLOT1_ALTSEL[3:0] = 1, SLOT2_ALTSEL[3:0] = 0x0B, SLOT3_ALTSEL[3:0] = 3. Set CHOP_E[1:0] = 00. Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or a power failure detection interrupt. When different CE codes are used, a different set of environment parameters needs to be established.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Table 57: CESTATUS (CE RAM 0x80) Bit Definitions CESTATUS [bit] 31:29 Name Not Used 28 F0 27 Reserved 26 SAG_B 25 SAG_A 24:0 Not Used Description These unused bits will always be zero. F0 is a square wave at the exact fundamental frequency for the phase selected with the FREQSELn bits in CECONFIG. Normally zero. Becomes one when VB remains below SAG_THR for SAG_CNT samples. Will not return to zero until VB rises above SAG_THR. Normally zero.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Table 58: CECONFIG Bit Definitions CECONFG [bit] [19] [18] Name Default Description SAG_MASK1 SAG_MASK0 0 0 [17] SAG_INT 0 [16] EXT_TEMP 0 [15:8] SAG_CNT 80 (0x50) [7] FREQSEL1 0 [6] FREQSEL0 0 [5] EXT_PULSE 1 [4] – 0 Sets the sag control of phase B. Sets the sag control of phase A. If more than one sag mask is set, a sag interrupt will only be generated when all phases enabled for the interrupt sag.
Data Sheet 71M6531D/F-71M6532D/F 4.3.7 FDS 6531/6532 005 CE Transfer Variables When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout each accumulation interval. In this data sheet, the names of CE transfer variables always end with _X. The transfer variables can be categorized as: 1.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F 0x90 0x93 I1SQSUM_X V0SQSUM_X 0x94 0x45 0x46 V1SQSUM_X WSUM_ACCUM VSUM_ACCUM 0x47 0x48 0x99 0x9A SUM3_ACCUM SUM4_ACCUM I0SQRES_X I1SQRES_X -13 LSBI = 6.6952*10 2 2 2 IMAX / In_8 A h The sum of squared voltage samples from each element. -13 2 2 LSBV= 6.6952*10 VMAX V h These registers contain roll-over accumulators for WPULSE and VPULSE respectively.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 The maximum time jitter is 67 µs and is independent of the number of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is 67 ppm. After 10 seconds, the peak jitter is 6.7 ppm. The average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum rate, it will simply output at its maximum rate without exhibiting any rollover characteristics.
FDS 6531/6532 005 CE Address Data Sheet 71M6531D/F-71M6532D/F Name Default Description PHADJ _ X = 2 20 0x19 PHADJ_B 0 0.02229 ⋅ TANΦ at 60Hz 0.1487 − 0.0131 ⋅ TANΦ 0.0155 ⋅ TANΦ at 50Hz 0.1241 − 0.009695 ⋅ TANΦ This register contains the reference point for the temperature measurement. At calibration temperature, the value read at TEMP_RAW_X should be written to TEMP_NOM. The CE will calculate the chip temperature TEMP_X relative to the reference temperature.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Figure 41: CE Data Flow: Multiplexer and ADC Figure 42: CE Data Flow: Scaling, Gain Control, Intermediate Variables 96 Rev 2
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Figure 43: CE Data Flow: Squaring and Summation Stages Rev 2 97
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 5 Electrical Specifications 5.1 Absolute Maximum Ratings Table 67 shows the absolute maximum ranges for the device. Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions (Section 5.3) is not implied.
FDS 6531/6532 005 5.2 Data Sheet 71M6531D/F-71M6532D/F Recommended External Components Table 68: Recommended External Components Name C1 From V3P3A To AGND Function Value Bypass capacitor for 3.3 V supply Unit ≥0.1 ±20% † µF † µF C2 V3P3D GNDD Bypass capacitor for 3.3 V output 0.1 ±20% CSYS V3P3SYS GNDD Bypass capacitor for V3P3SYS ≥1.0 ±30% µF C2P5 V2P5 GNDD Bypass capacitor for V2P5 0.1 ±20% µF XTAL XIN XOUT 32.
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 5.4 Performance Specifications 5.4.1 Input Logic Levels Table 70: Input Logic Levels Parameter a Digital high-level input voltage , VIH a Digital low-level input voltage , VIL Input pull-up current, IIL E_RXTX, E_RST, CKTEST Other digital inputs Input pull down current, IIH ICE_E RESET PB Other digital inputs a Condition Min 2 VIN=0 V, ICE_E=1 Typ 10 10 -1 VIN = V3P3D 10 10 -1 -1 Max 0.
FDS 6531/6532 005 5.4.5 Data Sheet 71M6531D/F-71M6532D/F Supply Current Table 74: Supply Current Performance Specifications Parameter VBAT current Condition Normal Operation, V3P3A = V3P3SYS = 3.3 V CKMPU = 614 kHz No Flash Memory write RTM_E=0, ECK_DIS=1, ADC_E=1, ICE_E=0 V3P3SYS current, Write Flash Normal Operation as above, except write Flash at maximum rate, CE_E = 0, ADC_ E = 0 VBAT current VBAT=3.
Data Sheet 71M6531D/F-71M6532D/F 5.4.9 FDS 6531/6532 005 Crystal Oscillator Table 78: Crystal Oscillator Performance Specifications Parameter 4 Maximum Output Power to Crystal 1 XIN to XOUT Capacitance 1 Capacitance to GNDD XIN XOUT Condition Crystal connected Min Typ Max 1 3 Unit μW pF 5 5 pF pF Max Unit +10 % RTCA_ADJ[6:0] = 0 5.4.10 LCD DAC Table 79: LCD DAC Performance Specifications Parameter VLCD Voltage Condition VLCD = V3P3 ⋅ (1 − 0.059 ⋅ LCD_DAC) − 0.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F 5.4.13 Temperature Sensor Table 82 shows the performance for the temperature sensor. The LSB values do not include the 8-bit left shift at CE input. Table 82: Temperature Sensor Performance Specifications Parameter Condition Nominal relationship: N(T) = Sn*(T-Tn) + Nn, Tn = 25ºC FIR_LEN[1:0]=0 Nominal Sensi2 (L=138) tivity (Sn) [M40MHZ, M26MH] = FIR_LEN[1:0]=1 3 L (L=288) S n = −0.
Data Sheet 71M6531D/F-71M6532D/F Parameter FDS 6531/6532 005 Condition CAL =1, ILOAD = 10 µA, -10 µA VREF output impedance Min VNOM temperature coefficients: TC1 TC2 VREF(T) deviation from VNOM(T) VREF (T ) − VNOM (T ) 10 6 max( T − 22 ,40) VNOM (T ) Unit 2.5 kΩ 3.18·(52.46-TRIMT) -0.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F ADC Gain Error versus %Power Supply Variation 10 6 ∆Nout PK 357 nV / VIN 100 ∆V 3P3 A / 3.3 Vin=200 mV pk, 65 Hz V3P3A=3.0 V, 3.6 V Input Offset (Vin-V3P3A) 1 -10 50 ppm/% 10 mV Guaranteed by design; not production tested.
Data Sheet 71M6531D/F-71M6532D/F 5.5 Timing Specifications 5.5.1 Flash Memory FDS 6531/6532 005 Table 85: Flash Memory Timing Specifications Parameter Flash Read Pulse Width Flash write cycles Flash data retention Flash data retention Flash byte write operations between page or mass erase operations Write Time per Byte Page Erase (1024 bytes) Mass Erase 5.5.
FDS 6531/6532 005 5.5.5 Data Sheet 71M6531D/F-71M6532D/F SPI Slave Port (MISSION Mode) Table 88: SPI Slave Port (MISSION Mode) Timing Parameter tSPIcyc PCLK cycle time tSPILead Enable lead time tSPILag Enable lag time tSPIW PCLK pulse width: High Low tSPISCK PCSZ to first PCLK fall tSPIDIS tSPIEV tSPISU tSPIH Condition Min 1 15 0 Ignore if PCLK is low when PCSZ falls.
Data Sheet 71M6531D/F-71M6532D/F 5.6 Typical Performance Data 5.6.1 Accuracy over Current FDS 6531/6532 005 Figure 45 shows accuracy over current for various load angles at room temperature. Figure 45: Wh Accuracy, 0.1 A to 200 A at 240 V/50 Hz and Room Temperature 5.6.2 Accuracy over Temperature With digital temperature compensation enabled, the temperature characteristics of the reference voltage (VREF) are compensated to within ±40 PPM/°C (see section 3.4 for details).
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F 5.7 71M6531D/F Package 5.7.1 Package Outline 68 8.000 ±0.050 1 2 PIN #1 DOT BY MARKING 8.000 ±0.050 TOP VIEW 0.850 ±0.050 0.000 ±0.050 SIDE VIEW 0.203 REF Figure 46: QFN-68 Package Outline, Top and Side View 6.300 ±0.100 Exp. pad 0.400 ±0.050 0.400 BSC 6.300 ±0.100 Exp. pad 0.200 ±0.050 2 1 PIN #1 ID R0.20, or CHAMFER 0.500 x 45° 68 6.400 REF. BOTTOM VIEW Figure 47: QFN-68 Package Outline, Bottom View * Pin length is nominally 0.
Data Sheet 71M6531D/F-71M6532D/F 5.7.
FDS 6531/6532 005 5.7.3 Data Sheet 71M6531D/F-71M6532D/F Recommended PCB Land Pattern for the QFN-68 Package Figure 49: PCB Land Pattern for QFN 68 Package Table 89: Recommended PCB Land Pattern Dimensions Symbol e x y d A G Description Lead pitch Pad width Pad length, see note 3 See note 1 Typical Dimension 0.4mm 0.23mm 0.8mm 6.3mm 6.63mm 7.2mm Notes: 1. Do not place unmasked vias in the region denoted by dimension d. 2. Soldering of bottom internal pad is not required for proper operation. 3.
Data Sheet 71M6531D/F-71M6532D/F 5.8 71M6532D/F Package 5.8.
FDS 6531/6532 005 5.8.2 Data Sheet 71M6531D/F-71M6532D/F LQFP-100 Mechanical Drawing 15.7(0.618) 16.3(0.641) 1 15.7(0.618) 16.3(0.641) Top View 14.000 +/- 0.200 MAX. 1.600 1.50 +/- 0.10 0.225 +/- 0.045 0.50 TYP. 0.10 +/- 0.10 Side View 0.60 TYP> Figure 51: LQFP-100 Package, Mechanical Drawing (Dimensions are in mm.
Data Sheet 71M6531D/F-71M6532D/F 5.9 FDS 6531/6532 005 Pin Descriptions Pin types: P = Power, O = Output, I = Input, I/O = Input/Output The circuit number denotes the equivalent circuit, as specified under Section 5.9.4 I/O Equivalent Circuits. 5.9.1 Power and Ground Pins Table 90: Power and Ground Pins Name Type Circuit GNDA P – GNDD P – V3P3A P – V3P3SYS P – V3P3D O 13 VBAT P 12 V2P5 O 10 5.9.
FDS 6531/6532 005 5.9.3 Data Sheet 71M6531D/F-71M6532D/F Digital Pins Table 92: Digital Pins Name COM3,COM2, COM1,COM0 SEG0…SEG2, SEG7, SEG8 SEG12…SEG18 SEG20…SEG23 SEG24/DIO4… SEG35/DIO15, SEG37/DIO17, SEG48/DIO28, SEG49/DIO29, SEG63/DIO43… SEG66/DIO46 SEG3/PCLK SEG4/PSDO SEG5/PCSZ SEG6/PSDI E_RXTX/SEG9 E_RST/SEG11 E_TCLK/SEG10 Type Circuit Description LCD Common Outputs: These 4 pins provide the select signals for the LCD display. O 5 O 5 Dedicated LCD Segment Output pins.
Data Sheet 71M6531D/F-71M6532D/F 5.9.
FDS 6531/6532 005 6 Data Sheet 71M6531D/F-71M6532D/F Ordering Information Part 71M6531D 71M6531D 71M6531F 71M6531F 71M6532D 71M6532D 71M6532F 71M6532F 7 Part Description (Package) 68-pin QFN, lead free 100-pin LQFP, lead free Flash Size 128 KB 128 KB 256 KB 256 KB Bulk Tape and reel Bulk Tape and reel 71M6531D-IM/F 71M6531D-IMR/F 71M6531F-IM/F 71M6531F-IMR/F Package Marking 71M6531D-IM 71M6531D-IM 71M6531F-IM 71M6531F-IM 128 KB 128 KB Bulk Tape and reel 71M6532D-IGT/F 71M6532D-IGTR/F 71M6532D
Data Sheet 71M6531D/F-71M6532D/F FDS 6531/6532 005 Appendix A: Acronyms AFE AMR ANSI CE DIO DSP FIR 2 IC ICE IEC MPU PLL RMS SFR SOC SPI TOU UART 118 Analog Front End Automatic Meter Reading American National Standards Institute Compute Engine Digital I /O Digital Signal Processor Finite Impulse Response Inter-IC Bus In-Circuit Emulator International Electrotechnical Commission Microprocessor Unit (CPU) Phase-locked loop Root Mean Square Special Function Register System on Chip Serial Peripheral Interfa
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F Appendix B: Revision History Revision 2 1.3 Rev 2 Date March 26, 2013 June 9, 2010 Description 1) Added Guaranteed By Design notes to the Electrical Specifications (Section 5). 2) Added explanation on NV properties of RTCA_ADJ[ ] and PREG/QREG[ ] (Section 1.5.3) and corrected entries in Table 55. 3) Added note that transitions to BROWNOUT mode must be avoided during page erase operations (Section 1.5.5). 4) Added note in Application Section 3.
Data Sheet 71M6531D/F-71M6532D/F 120 1.2 October 21, 2009 1.1 July 27, 2009 1.0 February 27, 2009 FDS 6531/6532 005 access via the SPI interface. Added Table 50. 9) 2.3 Battery Modes (page 56, 57): Added details on software precautions for switching between modes and factory programming of the first 6 flash addresses. 10) 3.1 Connection of Sensors (page 63): Added note concerning analog input pins requiring sensors with low source impedance. 11) 3.
FDS 6531/6532 005 Data Sheet 71M6531D/F-71M6532D/F 9) Removed access to I/O RAM from SPI Port description. 10) Updated numerous parameters in Electrical Specification (temperature sensor, supply current for mission and battery modes). 11) Corrected number of pre-boot cycles in Flash Memory Section. 12) Updated entries in I/O RAM table under “Wake” column. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product.
