L710HG Hardware Design IoT Module Series Version： V1.
L710HG Hardware Design Version History Date Version Description of change Author 2019-07-31 V1.0 Initial g.zhong 2019-11-01 V1.1 Update RF function discription Yw.ling 2020-02-13 V1.2 1. 15PN is changed to UIM_PRESENT for USIM hot-plug detection 2. 38PN is changed to RESERVED for later development 3, 1-4pn add UART reuse instructions 4. 34PN is changed to RESERVED 5. VBAT_BB and VBAT_RF are unified into VBAT 6. Add PCM reuse I2S function 7. The working range of ADC1 is changed to 0-1.875V g.
L710HG Hardware Design Contents 1 ABOUT THIS DOCUMENT ...................................... 5 1.1Applicable scope ....................................................................................................................................... 5 1.2 Writing purpose ....................................................................................................................................... 5 1.3 Support and reference documents list ...........................................................
L710HG Hardware Design 3.9 Power on/off and reset interface ........................................................................................................... 30 3.9.1 3.9.2 3.9.3 3.9.4 3.9.5 3.9.6 Pin definition ......................................................... Power on sequence ...................................................... Power off sequence ..................................................... Force PSM mode Out .....................................................
L710HG Hardware Design 6 MANUFACTURERS ........................................... 48 6.1 Steel mesh design ................................................................................................................................... 48 6.2 Temperature curve................................................................................................................................. 49 6.3 Device moisture-sensitivity level (MSL).......................................................................
L710HG Hardware Design 1 About this document 1.1Applicable scope This document describes the L710HG series NB-IOT/LTE-CATM LCC Module (here in after referred to as L710HG), the basic specifications, product electrical characteristics, design guidance and hardware interface development guidance. Users need to follow this documentation requirements and guidance for design. This document applies only to L710HG products in the application development. 1.
L710HG Hardware Design 8 《L710HG_V1_DECAL.PCB》 1.
L710HG Hardware Design TDD Time Division Duplexing DPCH Dedicated Physical Channel DPCH_Ec Average energy per PN chip for DPCH.
L710HG Hardware Design 2 Product Overview L710HG is a series of LTE CAT NB1 module and special design for global IOT market, and it’s have integrated rich peripheral interface. User can choose the module based on the wireless network configuration. In this document, the supported radio band is described in the following items.
L710HG Hardware Design TOP VIEW BOTTOM VIEW Figure 2-1 Product Physical Map SIDE VIEW 2.1 Package Dimensions The product module is 64-PIN LCC package module. The size of L710HG is extremely small, it is only 21.5.0 x 25.0 x 2.4 mm with LCC package, It is cost competitive and high integrated which make it convenient for customer to design their own application products.
L710HG Hardware Design (c)Bottom Dimensions (Unit mm) Note: For information regarding Footprint and Paste Mask recommended for the application of L710HG DEF Figure 2-2 Module Dimensions 10
L710HG Hardware Design 2.2 Product Function Outline 2.2.1 Hardware Diagram This product mainly includes the following signal group：USB Interface signal、USIM card Interface signal、I2C Interface signal、UART Interface signal、PCM Interface signal、SPI interface、Module startup、Module control signal、Power supply and ground. The global architecture of the L710HG module is described in the figure below.
L710HG Hardware Design 2.2.3 Antenna information Type: Single-stage sub-antenna GSM 850:Gain: 3.5dBi GSM 1900:Gain: 2dBi NB&CAT-M B2:2dBi NB&CAT-M B4/12/13/26（814-824）:4dBi NB&CAT-M B5/26（824-849）:3.
L710HG Hardware Design 3 Interface Description 3.1 PIN Definition 3.1.1 Pin I/O parameter definition The I/O parameter definition of the product is shown in table 3-1.
UART_RX UART_RTS GND 51 50 UART_TX 54 UART_CTS UART_RI 55 52 UART_DCD 56 53 UART_DTR 57 GND 60 STATUS PCM_OUT 61 FORCE_USB_BO OT PCM_IN 62 59 PCM_SYNC 63 58# PCM_CLK 64 L710HG Hardware Design 1 49 PCM_MCLK SPI_MOSI 2 48 FLIGHTMODE SPI_MISO 3 47 WAKEUP_OUT SPI_CLK 4 46 WAKEUP_IN GND 5 45 GND USB_HS_DM 6 44 I2C_SDA USB_HS_DP 7 43 I2C_SCL GND 8 42 MB_GPIO_0 USB_VBUS 9 SPI_CS L710 LCC Top View 41 GND 40 VDD_1V8 29 30 31 32 VBAT_BB GND GND UART_
L710HG Hardware Design 9 USB_VBUS 10 RESERVED 11 GND 12 UIM_CLK 13 UIM_RESET 14 UIM_DATA 15 UIM_PRESENT 16 USIM_VDD 17 GND 18 ANT_MAIN 19 GND 20 GND 21 RESERVED 22 GND #23 BOOT_CONFIG_0 24 UART_TX_DBG 25 VBAT 26 VBAT 27 GND 28 GND 29 VBAT 30 VBAT 31 GND 32 GND 33 UART_RX_DBG 34 RESERVED 35 ADC1 36 PWRKEY 37 RESERVED 38 RESERVED 39 NETLIGHT 40 VDD_1V8 41 GND 42 MB_GPIO_0 43 I2C_SCL 44 I2C_SDA 45 GND 46 WAKEUP_IN 47 WAKEUP_OUT 48 F
L710HG Hardware Design Table 3-3 Pin Function Description Power interface Pin Name Pin No. I/O Description Content The power supply for system Maximum VBAT 25,26,29,30 PI Power supply voltage, load current must VBAT=3.4V~4.2V. above 2A. de-cap Keep capacitor close to the this Net. USIM_VDD 16 PO Module LDO output power, single-voltage 1.8V output, Max current 50mA. Only use for external SIM Card VDD.
L710HG Hardware Design UIM_RESET 13 DO UIM Reset UIM_CLK 12 DO UIM Clock UIM Card Power output, output, only support USIM_VDD 16 PO 1.8V SIM Current is less than 50mA. USIM_PRESE USIM hot-plug detection (default low level 15 DI Pin Name Pin No. I/O Description SPI_CS 1 DO SPI_CS ,SPI chip select DI UART_CTS，Clear to Send SPI_MOSI 2 DO SPI master-out slave-in DO UART_TX，Transmit Data If not use keep it DI SPI master-in slave-out open.
L710HG Hardware Design If not use keep it RI 55 DO Ring Indicator. DCD 56 DO Carrier detects. TX 54 DO Transmit Data. DTR 57 DI DTE get ready. Pin No. I/O Description 24 DO LOG for DEBUG 38 DI LOG for DEBUG Pin Name Pin No. I/O Description Content I2C_SCL 43 DO I2C clock output. If not use keep it I2C_SDA 44 I/O I2C data input/output. open. Pin Name Pin No. I/O Description Content MAIN _ANT 18 AIO Main Antenna Pin Name Pin No.
L710HG Hardware Design VBAT Main power supply for 3.4 3.8 4.2 V the module 3.3 Digital I/O characteristics Table 3-5 1.8V Digital I/O characteristics Parameter Description Min. Max. Unit VIH High level input voltage 0.65*VDD_PX - V VIL Low level input voltage - 0.35* VDD_PX V VOH High level output voltage VDD_PX-0.45 - V VOL Low level output voltage - 0.
L710HG Hardware Design 3.4.2 Power supply requirements There are four VBAT PIN power for the module, VBAT directly power supply for the module baseband and PA, and operating rating is 3.4V~4.2V; In the weak network environment, the antenna will be maximum power emission. Voltage must be stable, because during operation the current drawn from VCC may vary significantly.
L710HG Hardware Design Figure 3-2 VBAT input application circuit Note: The Cd, Ce, Cb, Cc and Cf are recommended being mounted for L710HG, but the Ca, Cb, Ce, Cc and Cf for tune. In addition, in order to get a stable power source, it is suggested to use a Zener diode of which reverse Zener voltage is 5.1V and dissipation power is more than 500mW. Some zener diodes will have leakage of 1uA, which will increase the power consumption in PSM mode. Table 3-8: Recommended Zener diode models NO.
L710HG Hardware Design Figure 3-4 Reference circuit of the DCDC power supply Note: DCDC may deprave RF performance because of ripple current intrinsically. 3.4.5 Power Supply Layout guide The layout of the power supply section and the related components is of vital importance in the power module design. If processes this part layout is not good, will lead to various effects, such as bad EMC, effective the emission spectrum and receiving sensitivity, etc.
L710HG Hardware Design USIM_VDD LDO power output 1.75 VIH High-level input voltage VIL Low-level input voltage VOH High-level output voltage VOL Low-level output voltage 0.65·USI M_VDD -0.3 USIM_V DD -0.45 0 1.8 1.95 V USIM_V DD +0.3 - 0.35·USI 0 M_VDD USIM_V -- DD 0.45 0 V V V V 3.5.2 Design Guide In order to meet the 3 GPP TS 51.010 1 protocol and EMC certification requirements.
L710HG Hardware Design 3.6 PCM interface(TBD) 3.6.1 PCM interface definition L710HG provides hardware PCM interface for external codec. L710HG PCM interface can be used in short sync master mode only, and only supports 16 bits linear format： Table 3-10 (a) PCM interface definition Pin No. Signal name I/O Type PCM DC Characteristics（V） Min. Typ. Max. -0.3 1.8 1.9 63 PCM_SYNC synchronizing signal 62 PCM_DIN PCM data input -0.3 1.8 1.9 61 PCM_DOUT PCM Data output -0.3 1.8 1.
L710HG Hardware Design Figure 3-8 L710HG to codec module timing Table 3-10 (b) PCM interface Timing DC characters Parameter T(sync) T(synch) T(syncl) T(clk) T(clkh) Descriptions Min. Typ. Max. Unit PCM_SYNC cycle - 125 - us PCM_SYNC high level hold - 488 - ns - 124.
L710HG Hardware Design 0R PCM_DIN PCM_OUT 0R PCM_DOUT PCM_IN 0R PCM_SYNC PCM_SYNC 0R PCM_CL K PCM_CL K GND GND L710 CODEC Figure 3-19 PCM application circuit（L710HG only support in host mode） Note:1. L710HG PCM port DC character is base on 1.8 voltage, please pay attention the voltage matching. 2. If your design need this function, you should connect the PCM_MACLK as the codec chip clock or add the crystal for PCM clock. About the crystal type please contact our market. 3.
L710HG Hardware Design distortion, the impact of bus communication. Differential impedance of differential data line in 90ohm + 10%. MODULE HOST USB_VBUS 1 VUSB USB_DM 2 USB_DM USB_DP 3 USB_DP 5 GND GND C2 1UF D1 D2 ESD D3 ZENER ESD D4 ESD Figure 3-10 USB application 3.8 UART Interface 3.8.1 Pin description L710HG module provides a flexible 7-wire UART (universal asynchronous serial transmission) interface.
L710HG Hardware Design 56 DO UART_DCD UART Carrier detects. 3.8.2 UART interface application L710HG UART is COMS 1.8V level, Complete serial port with RS-232 functionality conforming to the ITU-T V.24 Recommendation, with CMOS compatible signal levels (0 V for low data bit or ON state and 1.8 V for high data bit or OFF state), if the AP voltage level is not the 1.8V should add a voltage transfer module in your application. Below is RS-232 voltage transfer module application diagram.
L710HG Hardware Design L610 Serial Port Figure 3-13 Client (DTE) Serial Port TXD1 TXD RXD1 RXD RTS1 RTS CTS1 CTS DTR1 DTR DCD1 DCD RING1 RING GND GND UART Full mode The L710HG UART is 1.8V interface. A level shifter should be used if user’s application is equipped with a 3.3V UART interface. The level shifter TXB0108RGYR provided by Texas Instruments is recommended. The reference design of the TXB0108RGYR is in the following figures.
L710HG Hardware Design 3.9 Power on/off and reset interface 3.9.1 Pin definition The power-on sequence of this product is: Pull down the PWRKEY pin and input a low pulse of about 1s to the boot signal. Then suspend or pull up the pin to start the machine. The PWRKEY pin has its own reset function. The hardware reset requires the PWRKEY pin to be pulled down for 12 seconds, and the module system can only reset and power-on after 12s.
L710HG Hardware Design power on. 2. The STATUS pin can be used to identify whether has been power on, when the module has access to electricity and initialization is completed, the STATUS output high level, or has maintained low level. 3.9.3 Power off sequence The following methods can be used to power down. These procedures will make module disconnect from the network and allow the software to enter a safe state, and then save data before completely powering the module off.
L710HG Hardware Design 3.9.4 Force PSM mode Out When the L710HG in PSM (Power saving mode) you can force the module to exit PSM mode by pulling down the PWRKEY pin. About how to enter the PSM please refer the L710HG AT command user manual. 3.9.5 Reset sequence L710HG do not have special RESET pin to reset module. PWRKEY is used for reset pin. This function is used as an emergency reset only when AT command “AT+CPOF” and the PWRKEY pin has no effect.
L710HG Hardware Design MODULE S1 PWRKEY 1S D1 ESD Figure 3-18: power on/off and reset recommended circuit (physical buttons) 3.10 Interactive interface 3.10.1 Pin definition Table 3-16 list the interface is mainly with the application processor interactive interface, including query, wake up four types, status indication, flight mode interface. Table 3-16 Interactive interface Pin No.
L710HG Hardware Design 3.10.2 interactive interface application L710HG provides three shook hands with application processor communication signals. Application processor can query whether the module boot normal work through STATUS. Through the WAKEUP_OUT query module is in sleep mode, and sleep in the module, through WAKEUP_IN wake module. Similarly, when application processor in the sleep state, the L710HG modules can through WAKEUP_OUT wake application processor.
L710HG Hardware Design Pin No. Net name I/O type description 39 NETLIGHT DO Module net state identify control LED port 3.11.2 Net light application The L710HG module has 1 pins for controlling the LED display, which can be used as an indicator of network connection status. Different network states are represented by the mode of the flashing light. This pin is an GPIO，with An external NPN Transistor，External connect VBAT can directly drive LED.
L710HG Hardware Design OFF Power off / Sleep Note: NETLIGHT output low level as “ON”, and high level as “OFF”. 3.12 System boot configuration and download 3.12.1 Pin definition L710HG can configure BOOT_CONFIG (Boot Configuration) pin to VDD_1V8 to disable the WATCHDOG function when power-on. Also force module to enter USB download mode by pulling up the FORCE_USB_BOOT and pulling down the PWRKEY. Table 3-19 Boot configuration and force USB download Pin No.
L710HG Hardware Design 3.13 Analog and Digital conversion (ADC) interface L710HG integrated two analog-to-digital conversion interface, specific parameters are as follows: Table 3-20 ADC1, ADC2 characters characters Min. Typ. Max. Unit ADC1 accuracy -11 ±6 11 mv ADC1 Input voltage range 0 1.875 v ADC1 Input resistance 1 -- -- MΩ Transfer time -- 514 550 us Note: The need for special software version to support access to the ADC. 3.14 I2C interface 3.14.
L710HG Hardware Design Note: 1. L710HG I2C only support host mode. 2. Only special software version support inquire the I2C. 3.15 SPI interface SPI signal consists of four signal lines: CS, CLK, MOSI and MISO. When SPI signal is used as the main device, its maximum speed can reach 50MHZ; when SPI signal is used as a slave device, its maximum speed can reach 25MHZ.
L710HG Hardware Design 3.16 Antenna interface 3.16.1 RF signal PCB layout guide L710HG provides RF antenna interface. Customer’s antenna should be located in the host board and connected to module’s antenna pad through micro-strip line or other types of RF trace and the trace impedance must be controlled in 50Ω. we recommends that the total insertion loss between the antenna pad and antenna should meet the following requirements: ● LTE (F<1GHz) <0.5dB ● LTE (1GHz
L710HG Hardware Design default, the R1, R2 are 0 Ohm resistors, and the C1, C2 are reserved for tuning. The RF test connector in the figure is used for the conducted RF performance test, and should be placed as close as to the module’s antenna pin. The traces impedance between components must be controlled in 50ohm. If the environment is very static, you can add TVS or 100nH inductance to the antenna end to enhance the anti-static capability 3.16.
L710HG Hardware Design 4 Product characteristics 4.1 Absolute parameters The following table shows the state of the absolute maximum work in abnormal situation. Exceed the limit value will likely result in permanent damage to the module. Table 4-1 L710HG absolute parameters Parameter Min. Max. Unit VBAT absolute voltage parameter -0.5 6.0 V USB_VBUS absolute voltage parameter -0.5 5.25 V I/O absolute voltage parameter： -0.3 2.
L710HG Hardware Design In this case, the power consumption depends on network settings such as DTX off/on, FR/EFR/HR, hopping sequences, antenna. (LTE) Standby Module is ready for GPRS/EDGE/WCDMA/TD-SCDMA/EVDO/LTE data transfer, but no data is currently sent or received. In this case, power consumption depends on network settings and EDGE/HSPA+ /LTE configuration. (LTE) Data transfer There is GPRS/EDGE/WCDMA/TD-SCDMA/EVDO/LTE data transfer in progress.
L710HG Hardware Design 4.2.3 current consumption The power consumption in suspended mode and without USB connection is listed in the table below. Table 4-4 working current consumption (VBAT=3.8V) Power off Power off current 14uA PSM 5uA Sleep/Idle GSM Sleep mode typical：1.72mA Idle mode typical：TBD EDRX （ EDRX value=81.92s、 Paging Time Sleep mode typical：0.63mA window=2.56s,小循环 1.28s） Idle mode typical：TBD DRX(2.56s) Sleep mode typical：1.
L710HG Hardware Design 4.4 ESD performance L710HG is electrostatic sensitive device, therefore, the user in the production, assembly and operation of the module must pay attention to the electrostatic protection.
L710HG Hardware Design 5 Design guideline This chapter provides a general design of the products instruction, the user can refer to design guidance for design, make products to achieve better performance. 5.1 General design rules and requirements Users in the design of this product is peripheral circuit, the first to ensure the external power supply circuit can provide enough power supply capacity, And the requirements for high speed signal lines USB control 90 ohm + / - 10% difference impedance.
L710HG Hardware Design between the transfer. 5.4 EMC and ESD design advice Users should take full account of the EMC problem caused by signal integrity and power integrity in the design of the whole machine, In the module of the peripheral circuit layout, for power and signal lines, etc., to maintain the spacing of 2 times line width. Can effectively reduce the coupling between the signal, so that the signal has a clean, the return path.
L710HG Hardware Design Figure 5-1 RECOMMENDED LAND PATTERN (Unit: mm) 5.6 Products recommended upgrade L710HG default through the USB firmware updates, so products to facilitate the software update, when the design proposal to set aside the USB test points or interface to facilitate subsequent product of the firmware upgrade.
L710HG Hardware Design 6 Manufacturers 6.1 Steel mesh design At the bottom of the module pad thermal, can be reduced by way of steel mesh openings, reduce the risk of short circuit between the thermal and the module of the module Pin, have certain effect; Module pad thermal welded steel mesh openings are recommended for reference. Figure 6-1 is recommended for steel mesh and size.
L710HG Hardware Design 6.2 Temperature curve In order to ensure soldering quality, special attention should be paid to the control of temperature curve pipes. The soldering profile shown below is only a general recommendation and should be adjusted according to the specific application and manufacturing. Figure 6-2 The reference temperature curve 6.3 Device moisture-sensitivity level (MSL) L710HG module complies with the humidity level 3.
L710HG Hardware Design 6 Mandatory bake before use. After bake, it must be reflowed within the time limit specified on the label. After unpacking, <30 degrees in temperature and relative humidity <60% environmental conditions, 168 hours in the SMT patch. If not meet the above conditions need to be baked. NOTES: For product handling, storage, processing, IPC / JEDEC J-STD-020C must be followed 6.
L710HG Hardware Design 7 Package Storage information 7.1 Package information 7.1.1 Tape and reel information Figure 7-1 Tap and reel information 7.1.1 Package information L710HG packing diagram is as follows, every 4 volumes of material packed in a case between each volume of material has a bubble mat do isolation protection.
L710HG Hardware Design Figure 7-2 Package and ship information 7.2 Bagged storage conditions L710HG shipments in the form of vacuum sealing anti-static bag. Module of storage need to follow the following conditions: Environment below 40 Degrees Celsius temperature, air humidity is less than 90% of cases, the module can be in vacuum sealed bags for 12 months. Conditions set the storage environment Suggestions with reference to the following form.
L710HG Hardware Design When open the vacuum bags, module storage air humidity is more than 10%. If modules need baking, please under 125 degrees Celsius (allowing fluctuations of 5 degrees Celsius) up and down bake for 48 hours. The following warning statements : This device complies with part 15 of the FCC Rules.
L710HG Hardware Design 8 Safety Information For the reasonable usage of the module, please comply with all these safety notices of this page. The product manufacturers should send followed safety information to user, operator or product’s spec. The devices using the module may disturb some electronic equipment. Put the module away from the phone, TV, radio and automation equipment to avoid the module and the equipment to interfere with each other.
