Intel® Xeon® Processor 7400 Series Datasheet October 2008 Order Number: 320335, Revision: -003
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Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ..................................................................................................... 11 1.2 State of Data .................................................................................................... 13 1.3 References .......................................................................................................
6.2 6.3 Processor Thermal Features ................................................................................97 6.2.1 Intel® Thermal Monitor Features ..............................................................97 6.2.2 Intel Thermal Monitor..............................................................................97 6.2.3 Intel Thermal Monitor 2 ...........................................................................98 6.2.4 On-Demand Mode ....................................................
Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 7-1 7-2 Intel® Xeon® X7460 Processor Load Current versus Time ...................................... 28 Intel® Xeon® Processor E7400 Series Load Current versus Time ............................ 28 Intel® Xeon® Processor L7400 Series Load Current versus Time.............................
Tables 1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 3-1 3-2 3-3 4-1 4-2 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 7-1 7-2 7-3 7-4 7-5 7-6 7-7 6 Processor Features.............................................................................................10 Core Frequency to Multiplier Configuration ............................................................17 BSEL[2:0] Frequency Table ..................................................
Revision History Document Number Revision 320335 001 Initial Release September 2008 320335 002 Updated Power Information September 2008 320335 003 Add Boxed Processor Information Description Date October 2008 § Intel® Xeon® Processor 7400 Series Datasheet 7
Intel® Xeon® Processor 7400 Series Datasheet
Introduction 1 Introduction ALL INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE. The Intel® Xeon® Processor 7400 Series is a four or six core product for multiprocessor servers. The processor is a single die based on Intel’s 45 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. The processor maintains the tradition of compatibility with IA-32 software.
Introduction Intel® Xeon® Processor 7400 Series are intended for high performance multiprocessor server systems. The processors support a Multiple Independent Bus (MIB) architecture with one processor on each bus. The MIB architecture provides improved performance by allowing increased FSB speeds and bandwidth. All versions of the Intel® Xeon® Processor 7400 Series will include manageability features.
Introduction 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted.
Introduction • Symmetric Agent – A symmetric agent is a processor which shares the same I/O subsystem and memory array, and runs the same operating system as another processor in a system. Systems using symmetric agents are known as Symmetric Multiprocessing (SMP) systems. • Integrated Heat Spreader (IHS) – A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.
Introduction Note: I2C is a two-wire communications bus/protocol developed by Phillips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Phillips Electronics N.V. and North American Phillips Corporation. 1.2 State of Data The data contained within this document is subject to change.The specifications are subject to change without notice.
Introduction 14 Intel® Xeon® Processor 7400 Series Datasheet
Electrical Specifications 2 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Intel® Xeon® Processor 7400 Series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination.
Electrical Specifications 2.2 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
Electrical Specifications The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. If lower speeds are desired, the appropriate ratio can be configured via the CLOCK_FLEX_MAX Model Specific Register (MSR). For details of operation at core frequencies lower than the maximum rated processor speed.
Electrical Specifications 2.3.2 PLL Power Supply An on-die PLL filter solution is implemented on the processor. The VCCPLL input is used to provide power to the on chip PLL of the processor. Please refer to Table 2-9 for DC specifications. Refer to the appropriate platform design guidelines for decoupling and routing guidelines. 2.
Electrical Specifications Table 2-3. HEX VID6 400 mV Voltage Identification Definition VID5 200 mV VID4 100 mV VID3 50 mV VID2 VID1 12.5 mV VCC_MAX HEX 25 mV VID6 VID5 VID4 VID3 VID2 VID1 12.5 mV VCC_MAX 400 mV 200 mV 100 mV 50 mV 25 mV 7A 1 1 1 1 0 1 0.8500 3C 0 1 1 1 1 0 1.2375 78 1 1 1 1 0 0 0.8625 3A 0 1 1 1 0 1 1.2500 76 1 1 1 0 1 1 0.8750 38 0 1 1 1 0 0 1.2625 74 1 1 1 0 1 0 0.8875 36 0 1 1 0 1 1 1.
Electrical Specifications 2.5 Reserved, Unused, or Test Signals All Reserved signals must remain unconnected. Connection of these signals to VCC, VTT, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section 4 for a pin listing of the processor and the location of all Reserved signals. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level.
Electrical Specifications Table 2-4. FSB Signal Groups Signal Group Signals1 Type AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#; AGTL+ Common Clock Output Synchronous to BCLK[1:0] BPM4#, BPM[2:1]#, BPMb[2:1]# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#2, BNR#2, BPM5#, BPM3#, BPM0#, BPMb3#, BPMb0#, BR[1:0]#, DBSY#, DP[3:0]#, DRDY#, HIT#2, HITM#2, LOCK#, MCERR#2 AGTL+ Source Synchronous I/O Synchronous to assoc.
Electrical Specifications Table 2-6 outlines AGTL+ signals which include on-die termination (RTT) and those that require external termination. Table 2-6 outlines non AGTL+ signals including open drain signals. Table 2-7 provides signal reference voltages. Table 2-5.
Electrical Specifications 2.9 Mixing Processors Intel supports and validates multi-processor configurations only in which all processors operate with the same FSB frequency, core frequency, number of cores, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies or number of cores is not supported and will not be validated by Intel.
Electrical Specifications 2.11 Processor DC Specifications The following notes apply: • The processor DC specifications in this section are defined at the processor die and not at the package pins unless noted otherwise. • The notes associated with each parameter are part of the specification for that parameter. • Unless otherwise noted, all specifications in the tables apply to all frequencies and cache sizes. See Section 5 for the pin signal definitions.
Electrical Specifications Table 2-9.
Electrical Specifications Table 2-9.
Electrical Specifications Table 2-9.
Electrical Specifications Figure 2-1. Intel® Xeon® X7460 Processor Load Current versus Time 15 5 Sustained Current (A) 15 0 14 5 14 0 13 5 13 0 12 5 12 0 0 .0 1 0 .1 1 10 10 0 10 0 0 Tim e Duration (s) Notes: 1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization. Figure 2-2.
Electrical Specifications Figure 2-3. Intel® Xeon® Processor L7400 Series Load Current versus Time 10 0 Sustained Current (A) 95 90 85 80 75 70 65 60 0 .0 1 0 .1 1 10 10 0 10 0 0 Tim e Duration (s) Notes: 1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization.
Electrical Specifications Table 2-10. VCC Static and Transient Tolerance ICC (A) VCC_Max (V) VCC_Typ (V) VCC_Min (V) Notes 0 VID - 0.000 VID - 0.015 VID - 0.030 1, 2, 3 5 VID - 0.006 VID - 0.021 VID - 0.036 1, 2, 3 10 VID - 0.013 VID - 0.028 VID - 0.043 1, 2, 3 15 VID - 0.019 VID - 0.034 VID - 0.049 1, 2, 3 20 VID - 0.025 VID - 0.040 VID - 0.055 1, 2, 3 25 VID - 0.031 VID - 0.046 VID - 0.061 1, 2, 3 30 VID - 0.038 VID - 0.053 VID - 0.068 1, 2, 3 35 VID - 0.
Electrical Specifications Figure 2-4. VCC Static and Transient Tolerance Load Lines Icc [A ] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 V ID - 0.000 VCC M ax im um V ID - 0.050 Vcc [V] V ID - 0.100 V ID - 0.150 VCC Ty pic al VCC M inim um V ID - 0.200 V ID - 0.250 Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.11.2 for VCC overshoot specifications. 2.
Electrical Specifications Table 2-12. CMOS Signal Input/Output Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 VIL Input Low Voltage -0.10 0.00 0.3*VTT V 2 VIH Input High Voltage 0.7*VTT VTT VTT+0.1 V 2 VOL Output Low Voltage -0.10 0 0.1*VTT V 2 VOH Output High Voltage 0.9*VTT VTT VTT+0.1 V 2 IOL Output Low Current 1.70 N/A 4.70 mA 3 IOH Output High Current 1.70 N/A 4.70 mA 4 ILI Input Leakage Current N/A N/A ± 100 μA 5, 6 Notes: 1.
Electrical Specifications 2.11.2 VCC Overshoot Specification Processors can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE pins and across the VCC_SENSE2 and VSS_SENSE2 pins. Table 2-15.
Electrical Specifications 2.11.4 Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary one-wire bus interface that provides a communication channel between Intel processor and external thermal monitoring devices. The Intel® Xeon® Processor 7400 Series contains Digital Thermal Sensors (DTS) distributed throughout the die.
Electrical Specifications 2.11.4.2 Input Device Hysteresis The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-6 as a guide for input buffer design. Figure 2-6. Input Device Hysteresis VTT Maximum VP PECI High Range Minimum VP Minimum Hysteresis Valid Input Signal Range Maximum VN Minimum VN PECI Low Range PECI Ground 2.
Electrical Specifications Table 2-17. AGTL+ Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes1 GTLREF_DATA_MID GTLREF_DATA_END Data Bus Reference Voltage 0.98 * 0.67 * VTT 0.67 * VTT 1.02 * 0.67 * VTT V 2, 3 GTLREF_ADD_MID GTLREF_ADD_END Address Bus Reference Voltage 0.98 * 0.67 * VTT 0.67 * VTT 1.02 * 0.67 * VTT V 2, 3 RTT Termination Resistance (pull up) 45 50 55 Ω 4 COMP COMP Resistance 49.4 49.9 50.4 Ω 5 Notes: 1.
Electrical Specifications 2.13 Front Side Bus AC Specifications The processor FSB timings specified in this section are defined at the processor core (pads). Therefore, proper simulation of the FSB is the only means to verify proper timing and signal quality. See Table 4-1 for the pin listing and Table 5-1 for signal definitions. Table 2-19 through Table 2-24 list the AC specifications associated with the processor FSB.
Electrical Specifications 4. 5. 6. 7. 8. Valid delay timings for these signals are specified into the test circuit described in Figure 2-7 and with GTLREF_DATA_MID, GTLREF_DATA_END, GTLREF_ADD_MID, and GTLREF_ADD_END at 0.67 * VTT. Specification is for a minimum swing is specified into the test circuit described in Figure 2-7 and defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 2.0 V/ns to 3.0 V/ns. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
Electrical Specifications 13. This specification applies only to DSTBN[3:0]# and is measured to the second falling edge of the strobe. 14. This specification reflects a typical value, not a minimum or maximum. 15. For this timing parameter, n = 0 to 1. Table 2-22.
Electrical Specifications Table 2-24. TAP Signal Group AC Specifications T# Parameter T55: TCK Period Min Max 30 Unit Figure Notes 1, 2, 8 ns 2-8 3 T56: TDI, TMS Setup Time 7.5 ns 2-15 4,7 T57: TDI, TMS Hold Time 7.5 ns 2-15 4,7 ns 2-15 5 TTCK 2-16 6 T58: TDO Clock to Output Delay 0 T59: TRST# Assert Time 2 7.5 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Not 100% tested. Specified by design characterization. 3.
Electrical Specifications 3. 4. 5. 2.14 Rise time is measured from (VIL_MAX - 0.15V) to (VIH_MIN + 0.15V). Fall time is measured from (0.9 * SM_VCC) to (VIL_MAX - 0.15V). DC parameters are specified in Table 2-26. Minimum time allowed between request cycles. Following a write transaction, an internal write cycle time of 10ms must be allowed before starting the next transaction.
Electrical Specifications Figure 2-8. TCK Clock Waveform V2 TCK V3 V1 Tp Tp = T55: Period V1, V2: For rise and fall times, TCK is measured between 20% and 80% points on the waveform. V3: TCK is referenced to 0.5 * VTT Figure 2-9. Differential Clock Waveform Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tp Tp = T1: BCLK[1:0] period Figure 2-10.
Electrical Specifications Figure 2-11. BCLK Waveform at Processor Pad and Pin SKT PAD Notes: 1. Waveform at pin is non-monotonic. Waveform at pad is monotonic. 2. Differential Edge Rate (DER) measured zero +/- 200mv. 3. g indicates V/ns units and meg indicates mv/ns units. 4. Waveform at pad has faster edge rate than at pin. Figure 2-12.
Electrical Specifications Figure 2-13. FSB Source Synchronous 2X (Address) Timing Waveform T0 Tp/4 Tp/2 T1 3Tp/4 T2 BCLK1 BCLK0 TR ADSTB# (@ driver) TJ TH A# (@ driver) valid TJ TH valid TK TS ADSTB# (@ receiver) A# (@ receiver) valid valid TM TN TP = T1: BCLK[1:0] Period TH = T23: Source Sync. Address Output Valid Before Address Strobe TJ = T24: Source Sync. Address Output Valid After Address Strobe TK = T27: Source Sync. Address Strobe Setup Time to BCLK TM = T25: Source Sync.
Electrical Specifications Figure 2-14. FSB Source Synchronous 4X (Data) Timing Waveform T0 Tp/4 Tp/2 T1 3Tp/4 T2 BCLK1 BCLK0 TD DSTBp# (@ driver) DSTBn# (@ driver) TA TB TA TB D# (@ driver) TC DSTBp# (@ receiver) TJ DSTBn# (@ receiver) D# (@ receiver) TE TG TE TG TP = T1: BCLK[1:0] Period TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T28: Source Sync.
Electrical Specifications Figure 2-15. TAP Valid Delay Timing Waveform V TCK Tx Ts Th V Valid Signal Tx = T58: TDO Clock to Output Delay Ts = T56: TDI, TMS Setup Time Th = T57: TDI, TMS Hold Time V = 0.5 * VTT Note: Please refer to Table 2-12 for TAP Signal Group DC specifications and Table 2-24 for TAP Signal Group AC specifications. Figure 2-16. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform V Tq T = T59 (TRST# Pulse Width), V = 0.
Electrical Specifications Figure 2-18. SMBus Timing Waveform t t LOW tF R t HD;STA Clk t HD;STA t t HD;DAT t SU;DAT HIGH t SU;STA t SU;STO Data t BUF P STOP S S START START t LOW = T93 t HD;STA = T100 t SU;STA = T101 t HIGH = T92 t HD;DAT = T98 t SU;STD = T102 tR tF = T94 t BUF = T95 t SU;DAT = T97 P STOP = T99 Figure 2-19.
Electrical Specifications Figure 2-20.
Electrical Specifications Notes: 1. Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion). 2. FERR# / PBE# is undefined from STPCLK# assertion until the Stop-Grant acknowledge is driven on the FSB. FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions, the PBE# signal is driven. FERR# is driven at all other times. Figure 2-22. VID Step Timings VID n ...
Electrical Specifications 50 Intel® Xeon® Processor 7400 Series Datasheet
Mechanical Specifications 3 Mechanical Specifications The Intel® Xeon® Processor 7400 Series is packaged in a lead free FC-mPGA8 package that interfaces with the motherboard via a mPGA604 socket. The package consists of the processor die mounted on a substrate pin-carrier. An IHS is attached to the package substrate and die and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Mechanical Specifications Figure 3-2.
Mechanical Specifications Figure 3-3.
Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate. All drawing dimension are in mm [in].
Mechanical Specifications Figure 3-4.
Mechanical Specifications Figure 3-5.
Mechanical Specifications Figure 3-6.
Mechanical Specifications Figure 3-7.
Mechanical Specifications Figure 3-8.
Mechanical Specifications 3.3 Package Loading Specifications Table 3-1 provides dynamic and static load specifications for the processor package. These mechanical load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solutions.
Mechanical Specifications 3.4 Package Handling Guidelines Table 3-2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 3-2. Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N [80 lbf] 1, 2 Tensile 156 N [35 lbf] 3, 2 Torque 8 N-m [70 lbf-in] 4, 2 Notes: 1. 2. 3. 4. 3.
Mechanical Specifications 3.8 Processor Markings Figure 3-9 shows the topside markings and Figure 3-10 shows the bottom-side markings on the processor. These diagrams are to aid in the identification of the Intel® Xeon® Processor 7400 Series. Please note that the figures in this section are not to scale. Figure 3-9.
Mechanical Specifications 3.9 Processor Pin-Out Coordinates Figure 3-11 shows the top view of the processor pin coordinates. The coordinates are referred to throughout the document to identify processor pins. Figure 3-11.
Mechanical Specifications 64 Intel® Xeon® Processor 7400 Series Datasheet
Pin Listing 4 Pin Listing 4.1 Processor Pin Assignments Section 2.6 contains the front side bus signal groups for the Intel® Xeon® Processor 7400 Series (see Table 2-4). This section provides a sorted pin list in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor pins ordered alphabetically by pin name. Table 4-2 is a listing of all processor pins ordered by pin number. 4.1.1 Pin Listing by Pin Name Table 4-1. Pin Listing by Pin Name (Sheet 2 of 16) Table 4-1.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 3 of 16) Table 4-1. Pin Listing by Pin Name (Sheet 4 of 16) Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 5 of 16) Pin Name Pin No. Signal Buffer Type Table 4-1. Pin Listing by Pin Name (Sheet 6 of 16) Direction Pin Name Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 7 of 16) Table 4-1. Pin Listing by Pin Name (Sheet 8 of 16) Pin No. Signal Buffer Type C24 TAP Input TDO E25 TAP TESTHI0 A16 Power/Other TESTHI1 W3 TESTIN1 D1 TESTIN2 C2 THERMTRIP# F26 TMS A25 TRDY# E19 TRST# VCC Pin Name TDI Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 9 of 16) Pin No. Signal Buffer Type VCC M9 Power/Other Pin Name Table 4-1. Pin Listing by Pin Name (Sheet 10 of 16) Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 11 of 16) Table 4-1. Pin Listing by Pin Name (Sheet 12 of 16) Pin No. Signal Buffer Type VCC AC3 Power/Other VSS VCC AC16 Power/Other VSS E9 Power/Other VCC AC22 Power/Other VSS E15 Power/Other VCC AC31 Power/Other VSS E17 Power/Other VCC AD2 VSS E23 Power/Other VCC AD20 Power/Other VSS E29 Power/Other VSS E31 Power/Other Pin Name Direction Power/Other Pin Name Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 13 of 16) Pin No. Signal Buffer Type VSS J29 Power/Other VSS J31 VSS K2 VSS K4 VSS K6 VSS VSS VSS VSS VSS VSS Pin Name Table 4-1. Pin Listing by Pin Name (Sheet 14 of 16) Direction Pin Name Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 15 of 16) Table 4-1. Pin Listing by Pin Name (Sheet 16 of 16) Pin No.
Pin Listing 4.1.2 Pin Listing by Pin Number Table 4-2. Pin Listing by Pin Number (Sheet 1 of 14) Pin No. A1 Pin Name VID5 Signal Buffer Type Power/Other Direction Table 4-2. Pin No.
Pin Listing Table 4-2. Pin No. 74 Pin Listing by Pin Number (Sheet 3 of 14) Pin Name Signal Buffer Type Direction Table 4-2. Pin Listing by Pin Number (Sheet 4 of 14) Pin No.
Pin Listing Table 4-2. Pin No. Pin Listing by Pin Number (Sheet 5 of 14) Pin Name Signal Buffer Type Table 4-2. Pin Listing by Pin Number (Sheet 6 of 14) Pin Name Signal Buffer Type Direction Pin No.
Pin Listing Table 4-2. Pin No. 76 Pin Listing by Pin Number (Sheet 7 of 14) Pin Name Signal Buffer Type Direction Table 4-2. Pin Listing by Pin Number (Sheet 8 of 14) Pin No.
Pin Listing Table 4-2. Pin No. Pin Listing by Pin Number (Sheet 9 of 14) Pin Name Signal Buffer Type Direction Table 4-2. Pin No.
Pin Listing Table 4-2. Pin No. 78 Pin Listing by Pin Number (Sheet 11 of 14) Pin Name Signal Buffer Type Direction Table 4-2. Pin Listing by Pin Number (Sheet 12 of 14) Pin No.
Pin Listing Table 4-2. Pin No. Pin Listing by Pin Number (Sheet 13 of 14) Pin Name Signal Buffer Type Table 4-2. Pin Listing by Pin Number (Sheet 14 of 14) Pin Name Signal Buffer Type Direction Pin No.
Pin Listing 80 Intel® Xeon® Processor 7400 Series Datasheet
Signal Definitions 5 Signal Definitions 5.1 Signal Definitions Table 5-1. Signal Definitions (Sheet 1 of 8) Name A[39:3]# Type Description Notes 240-byte I/O A[39:3]# (Address) define a physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the processor FSB.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 2 of 8) Type Description BINIT# I/O BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration (see Section 7.
Signal Definitions Table 5-1. Name D[63:0]# Signal Definitions (Sheet 3 of 8) Type I/O Description Notes D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period.
Signal Definitions Table 5-1. Signal Definitions (Sheet 4 of 8) Name DSTBN[3:0]# DSTBP[3:0]# Type I/O I/O Description Data strobe used to latch in D[63:0]#. Signals Associated Strobes D[15:0]#, DBI0# DSTBN0# D[31:16]#, DBI1# DSTBN1# D[47:32]#, DBI2# DSTBN2# D[63:48]#, DBI3# DSTBN3# Data strobe used to latch in D[63:0]#.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 5 of 8) Type Description IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 6 of 8) Type Description PROCHOT# O PROCHOT# (Processor Hot) will go active when the processor’s temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the Thermal Control Circuit (TCC) has been activated, if enabled. The TCC will remain active until shortly after the processor deasserts PROCHOT#. See Section 6.2.5 for more details.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 7 of 8) Type Description SM_WP I WP (Write Protect) can be used to write protect the Scratch EEPROM. The Scratch EEPROM is write-protected when this input is pulled high to SM_VCC. The processor includes a 10 kΩ pull-down resistor to VSS for this signal. SMI# I SMI# (System Management Interrupt) is asserted asynchronously by system logic.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 8 of 8) Type Description VID[6:1] O VID[6:1] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). These are CMOS signals that are driven by the processor and must be pulled up through a resistor. Conversely, the voltage regulator output must be disabled prior to the voltage supply for these pins becomes invalid. The VID pins are needed to support processor voltage specification variations.
Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The Intel® Xeon® Processor 7400 Series require a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Thermal Specifications enabled 2U heatsink). In this scenario, it is expected that the Thermal Control Circuit (TCC) would only be activated for very brief periods of time when running the most power intensive applications. Intel has developed the thermal profile to allow customers to choose the thermal solution and environmental parameters that best suit their platform implementation.
Thermal Specifications Table 6-1.
Thermal Specifications 2. 3. Table 6-2. Implementation of Thermal Profile should result in virtually no TCC activation. Furthermore, utilization of thermal solutions that do not meet processor Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss. (See Section 6.2 for details on TCC activation). Refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide for system and environmental implementation details.
Thermal Specifications Figure 6-2. 6-Core Intel® Xeon® Processor E7400 Series Thermal Profile 75.0 70.0 65.0 Temperature (C) 60.0 55.0 50.0 o TCASE=0.256xPower +45 C 45.0 40.0 35.0 30.0 0 10 20 30 40 50 60 70 80 90 Power (W) Notes: 1. Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-3 for discrete points that constitute the thermal profile. 2. Implementation of Thermal Profile should result in virtually no TCC activation.
Thermal Specifications Figure 6-3. 4-Core Intel® Xeon® Processor E7400 Series Thermal Profile 70.0 65.0 Temperature (C) 60.0 55.0 50.0 TCASE= 0.222 x Power + 45oC 45.0 40.0 35.0 30.0 0 10 20 30 40 50 60 70 80 90 Power (W) Notes: 1. Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-4 for discrete points that constitute the thermal profile. 2. Implementation of Thermal Profile should result in virtually no TCC activation.
Thermal Specifications Figure 6-4. 6-Core Intel® Xeon® Processor L7400 Series Thermal Profile 60.0 Temperature (C) 55.0 50.0 TCASE= 0.431 x Power + 45 oC 45.0 40.0 35.0 0 10 20 30 40 50 60 Power (W) Notes: 1. Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-5 for discrete points that constitute the thermal profile. 2. Implementation of Thermal Profile should result in virtually no TCC activation.
Thermal Specifications Figure 6-5. 4-Core Intel® Xeon® Processor L7400 Series Thermal Profile 70.0 65.0 Temperature (C) 60.0 55.0 TCASE = 0.400 x Pow er + 45 oC 50.0 45.0 40.0 35.0 0 10 20 30 40 50 Power (W) Notes: 1. Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 6-6 for discrete points that constitute the thermal profile. 2. Implementation of Thermal Profile should result in virtually no TCC activation.
Thermal Specifications 6.1.2 Thermal Metrology The minimum and maximum case temperatures (TCASE) are specified in Table 6-2 through Table 6-5, and are measured at the geometric top center of the processor integrated heat spreader (IHS). Figure 6-6 illustrates the location where TCASE temperature measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Intel® Xeon® Processor 7400 Series Thermal Mechanical Design Guide. Figure 6-6.
Thermal Specifications is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. When the Intel Thermal Monitor is enabled, and a high temperature situation exists (that is, TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30 - 50%).
Thermal Specifications order of 5 µs. During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency. Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator.
Thermal Specifications IA32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Intel Thermal Monitor; however, if the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. 6.2.
Thermal Specifications of processor activity and does not generate any bus cycles. If THERMTRIP# is asserted, processor core voltage (VCC) must be removed within the time frame defined in Table 2-22 and Figure 2-17. Intel also recommends the removal of VTT. 6.3 Platform Environment Control Interface (PECI) 6.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues.
Thermal Specifications 6.3.1.1 TCONTROL and Tcc Activation on PECI-Based Systems Fan speed control solutions based on PECI utilize a TCONTROL (Temperature Control Offset) value stored in the processor IA32_TEMPERATURE_TARGET MSR. This MSR uses the same offset temperature format as PECI, though it contains no sign bit. Thermal management devices should infer the TCONTROL value as negative.
Thermal Specifications 6.3.2 PECI Specifications 6.3.2.1 PECI Device Address The Intel® Xeon® Processor 7400 Series obtains its PECI address based on the processors APIC ID[4:3] at power on. APIC ID[4:3] is also known as the Cluster ID[1:0]. The Cluster ID[1:0] is set, by the chipset, by asserting the power-on configuration (POC) signals A[12:11]# at the deassertion of RESET#. The PECI address for the Intel® Xeon® Processor 7400 Series = 0x30 + Cluster ID[0:1] 1..
Thermal Specifications actions to protect the corresponding device and/or other system components from overheating. The host controller may also implement an alert to software in the event of a critical or continuous fault condition. 6.3.2.4 PECI GetTemp0() and GetTemp1() Error Code Support The error codes supported for the processor GetTemp0() and GetTemp1() commands are listed inTable 6-7 below: Table 6-7.
Features 7 Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Intel® Xeon® Processor 7400 Series samples its hardware configuration at reset, on the active-toinactive transition of RESET#. For specifics on these options, please refer to Table 7-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features 7.2.1 Normal State This is the normal operating state for the processor. 7.2.2 HALT or Extended HALT State The Extended HALT state (C1E) is enabled via the BIOS. The Extended HALT state must be enabled for the processor to remain within its specifications. The Extended HALT state requires support for dynamic VID transitions in the platform. 7.2.2.1 HALT State HALT is a low power state entered when the processor has executed the HALT or MWAIT instruction.
Features E Table 7-2.
Features Figure 7-1.
Features While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus. The PBE# signal can be driven when the processor is in Stop-Grant state.
Features Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage/frequency operating points. P-states are lower power capability states within the Normal state as shown in Figure 7-1. Enhanced Intel SpeedStep Technology enables real-time dynamic switching between frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage.
Features Figure 7-2. Logical Schematic of SMBus Circuitry SM_VCC VCC SM_EP_A0 SM_EP_A1 SM_EP_A2 SM_WP DATA Processor Information ROM and Scratch EEPROM (1Kbit each) CLK VSS SM_CLK SM_DAT Note: 7.4.1 Actual implementation may vary. This figure is provided to offer a general understanding of the architecture. All SMBus pull-up and pull-down resistors are 10 kΩ and located on the processor.
Features Table 7-3. Memory Device SMBus Addressing Address (Hex) Upper Address1 Device Select R/W bits 7-4 SM_EP_A2 bit 3 SM_EP_A1 bit 2 SM_EP_A0 bit 1 bit 0 A0h/A1h 1010 0 0 0 X A2h/A3h 1010 0 0 1 X A4h/A5h 1010 0 1 0 X A6h/A7h 1010 0 1 1 X A8h/A9h 1010 1 0 0 X AAh/ABh 1010 1 0 1 X ACh/ADh 1010 1 1 0 X AEh/AFh 1010 1 1 1 X Note: 1. This addressing scheme will support up to 8 processors on a single SMBus. 7.4.
Features 7.4.3 Processor Information ROM (PIROM) The lower half (128 bytes) of the SMBus memory component is an electrically programmed read-only memory with information about the processor. This information is permanently write-protected. Table 7-6 shows the data fields and Section 7.4.3 provides the formats of the data fields included in the Processor Information ROM (PIROM).
Features Table 7-6.
Features Table 7-6. Processor Information ROM Data Sections (Sheet 3 of 3) Offset/Section # of Bits Function Notes 8 Reserved Reserved Thermal Ref.
Features 7.4.3.1.1 DFR: Data Format Revision This location identifies the data format revision of the PIROM data structure. Writes to this register have no effect. Offset: 00h Bit Description 7:0 Data Format Revision The data format revision is used whenever fields within the PIROM are redefined. The initial definition will begin at a value of 1.
Features 7.4.3.1.4 PCDA: Processor Core Data Address This location provides the offset to the Processor Core Data Section. Writes to this register have no effect. Offset: 04h Bit 7:0 Description Processor Core Data Address Byte pointer to the Processor Data section 00h: Processor Core Data section not present 01h - 15h: Reserved 16h: Processor Core Data section pointer value 17h-FFh: Reserved 7.4.3.1.5 L3CDA: L3 Cache Data Address This location provides the offset to the L3 Cache Data Section.
Features 7.4.3.1.7 PNDA: Part Number Data Address This location provides the offset to the Part Number Data Section. Writes to this register have no effect. Offset: 07h Bit Description 7:0 Part Number Data Address Byte pointer to the Part Number Data section 00h: Part Number Data section not present 01h - 37h: Reserved 38h: Part Number Data section pointer value 39h-FFh: Reserved 7.4.3.1.8 TRDA: Thermal Reference Data Address This location provides the offset to the Thermal Reference Data Section.
Features 7.4.3.1.10 ODA: Other Data Address This location provides the offset to the Other Data Section. Writes to this register have no effect. Offset: 0Ah Bit 7:0 Description Other Data Address Byte pointer to the Other Data section 00h: Other Data section not present 01h - 7Dh: Reserved 7Eh: Other Data section pointer value 7Fh- FFh: Reserved 7.4.3.1.11 RES1: Reserved 1 This locations are reserved. Writes to this register have no effect.
Features Offset: 0Eh-13h Bit 47:40 Description Character 6 S-SPEC character or 20h 00h-0FFh: ASCII character 39:32 Character 5 S-SPEC character or 20h 00h-0FFh: ASCII character 31:24 Character 4 S-SPEC character 00h-0FFh: ASCII character 23:16 Character 3 S-SPEC character 00h-0FFh: ASCII character 15:8 Character 2 S-SPEC character 00h-0FFh: ASCII character 7:0 Character 1 S-SPEC character 00h-0FFh: ASCII character 7.4.3.2.
Features 7.4.3.2.3 PDCKS: Processor Data Checksum This location provides the checksum of the Processor Data Section. Writes to this register have no effect. Offset: 15h Bit 7:0 Description Processor Data Checksum One Byte Checksum of the Header Section 00h- FFh: See Section 7.4.4 for calculation of the value 7.4.3.3 Processor Core Data This section contains core silicon-related data. 7.4.3.3.
Features 7.4.3.3.2 FSB: Front Side Bus Speed This location contains the front side bus transaction rate information. Systems may need to read this offset to decide if all installed processors support the same front side bus speed. Because FSB is described as a 4X data bus, the transaction rate given in this field is currently 1066 MTS. The data provided is the speed, rounded to a whole number, and reflected in hex. Writes to this register have no effect.
Features Offset: 1Dh-1Eh Bit 15:0 Description Maximum Core Frequency 0000h-FFFFh: MHz 7.4.3.3.5 MAXVID: Maximum Core VID This location contains the maximum Core VID (Voltage Identification) voltage that may be requested via the VID pins. This field, rounded to the next thousandth, is in mV and is reflected in hex. Writes to this register have no effect. Example: From Table 2-9the maximum VID is 1.450 V maximum voltage. Offset 1F 20h would contain 05AAh (1450 decimal).
Features Offset: 23h Bit 7:0 Description TCASE Maximum 00h-FFh: Degrees Celsius 7.4.3.3.8 PCDCKS: Processor Core Data Checksum This location provides the checksum of the Processor Core Data Section. Writes to this register have no effect. Offset: 24h Bit 7:0 Description Processor Core Data Checksum One Byte Checksum of the Header Section 00h- FFh: See Section 7.4.4 for calculation of the value 7.4.3.4 Cache Data This section contains cache-related data. 7.4.3.4.
Features 7.4.3.4.3 L3SIZE: L3 Cache Size This location contains the size of the level three cache in kilobytes. Writes to this register have no effect. Example: The Intel® Xeon® Processor 7400 Series has either a 12 MB (12288 KB) , 16 MB (16384 KB) or 8 MB ((8192 KB))L3 cache. Thus, offset 29 - 2Ah will contain 3000h (for 12 MB) ,4000h (for 16 MB) or 2000h(for 8 MB). Offset: 29h-2Ah Bit 15:0 Description L3 Cache Size 0000h-FFFFh: KB 7.4.3.4.
Features 7.4.3.4.6 RES4: Reserved 4 These locations are reserved. Writes to this register have no effect. Offset: 2Fh-30h Bit 15:0 Description RESERVED 4 0000h-FFFFh: Reserved 7.4.3.4.7 CDCKS: Cache Data Checksum This location provides the checksum of the Cache Data Section. Writes to this register have no effect. Offset: 31h Bit 7:0 Description Cache Data Checksum One Byte Checksum of the Header Section 00h- FFh: See Section 7.4.4 for calculation of the value 7.4.3.
Features 7.4.3.5.2 RES5: Reserved 5 This location is reserved. Writes to this register have no effect. Offset: 36h Bit 7:0 Description RESERVED 5 00h-FFh: Reserved 7.4.3.5.3 PDCKS: Package Data Checksum This location provides the checksum of the Package Data Section. Writes to this register have no effect. Offset: 37h Bit 7:0 Description Package Data Checksum One Byte Checksum of the Header Section 00h- FFh: See Section 7.4.4 for calculation of the value 7.4.3.
Features Offset: 38h-3Eh Bit 23:16 Description Character 3 ASCII character 00h-0FFh: ASCII character 15:8 Character 2 ASCII character 00h-0FFh: ASCII character 7:0 Character 1 ASCII character 00h-0FFh: ASCII character 7.4.3.6.2 RES6: Reserved 6 This location is reserved. Writes to this register have no effect. Offset: 3Fh-4Ch Bit 111:0 7.4.3.6.3 Description RESERVED 6 PS/ESIG: Processor Serial/Electronic Signature This location contains a 64-bit identification number.
Features 7.4.3.6.5 PNDCKS: Part Number Data Checksum This location provides the checksum of the Part Number Data Section. Writes to this register have no effect. Offset: 6F Bit 7:0 Description Part Number Data Checksum One Byte Checksum of the Header Section 00h- FFh: See Section 7.4.4 for calculation of the value 7.4.3.7 Thermal Reference Data This section is reserved for future use. 7.4.3.7.1 RES8: Reserved 8 This location is reserved. Writes to this register have no effect.
Features 7.4.3.8 Feature Data This section provides information on key features that the platform may need to understand without powering on the processor. 7.4.3.8.1 PCFF: Processor Core Feature Flags This location contains a copy of results in EDX[31:0] from Function 1 of the CPUID instruction. These details provide instruction and feature support by product family. A decode of these bits is found in the AP-485 Intel® Processor Identification and CPUID Instruction application note.
Features Offset: 79h Bit 7.4.3.8.4 Description 7:2 Number of cores 1:0 Number of threads per cores AFF: Additional Processor Feature Flags This location contains additional feature information for the processor. This field is defined as follows: Writes to this register have no effect.
Features 7.4.3.9.1 FDCKS: Feature Data Checksum This location provides the checksum of the Feature Data Section. Writes to this register have no effect. Offset: 7Fh Bit 7:0 Description Feature Data Checksum One Byte Checksum of the Header Section 00h- FFh: See Section 7.4.4 for calculation of the value 7.4.4 Checksums The PIROM includes multiple checksums. Table 7-7 includes the checksum values for each section defined in the 128 byte ROM. Table 7-7.
Debug Tools Specifications 8 Debug Tools Specifications Please refer to the appropriate platform design guidelines for information regarding debug tool specifications. Section 1.3 provides collateral details. 8.1 Debug Port System Requirements The Intel® Xeon® Processor 7400 Series debug port is the command and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the processors for system debug.
Debug Tools Specifications different requirements from the space normally occupied by the heatsink. If this is the case, the logic analyzer vendor will provide either a cooling solution as part of the LAI or additional hardware to mount the existing cooling solution. 8.2.
Boxed Processor Specifications 9 Boxed Processor Specifications 9.1 Introduction The Intel® Xeon® Processor 7400 Series is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will not be supplied with a cooling solution. Future revisions may have solutions that differ from those discussed here. 9.
Boxed Processor Specifications 136 Intel® Xeon® Processor 7400 Series Datasheet
