Intel® Xeon® Processor 5600 Series Datasheet, Volume 1 March 2010 Reference Number: 323369-001
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Contents 1 Introduction ............................................................................................................ 11 1.1 Processor Features ............................................................................................ 12 1.2 Platform Features .............................................................................................. 12 1.3 Terminology ..................................................................................................... 13 1.
7.3 7.4 7.2.3 On-Demand Mode ............................................................................... 133 7.2.4 PROCHOT# Signal ............................................................................... 133 7.2.5 THERMTRIP# Signal ............................................................................ 134 Platform Environment Control Interface (PECI) .................................................... 134 7.3.1 PECI Client Capabilities ....................................................
Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 3-1 4-1 4-2 4-3 4-4 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 Active ODT for a Differential Link Example ............................................................ 17 Input Device Hysteresis ..................................................................................... 18 VCC Static and Transient Tolerance Loadlines1,2,3,4...............
7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 8-1 8-2 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 6 GetDIB() ........................................................................................................ 137 Device Info Field Definition ............................................................................... 137 Revision Number Definition ...............................................................................
Tables 1-1 1-2 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 3-1 4-1 4-2 4-3 5-1 5-2 6-1 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 Intel® Xeon® Processor 5600 Series Feature Set Overview .................................... 12 References ....................................................................................................... 15 Processor Power Supply Voltages1 ............................................
7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 8-1 8-2 8-3 8-4 9-1 9-2 9-3 8 Low Power Platform 60W Thermal Specifications .................................................. 125 Low Power Platform 60W Thermal Profile (6 Core)................................................ 125 Low Power Platform 40W Thermal Specifications ..................................................
Revision History Revision Number -001 Description • Date Initial Release March 2010 § Intel® Xeon® Processor 5600 Series Datasheet Volume 1 9
Intel® Xeon® Processor 5600 Series Datasheet Volume 1
Introduction 1 Introduction The Intel® Xeon® processor 5600 series is a server/workstation multi-core processor based on 32 nm process technology. The processors feature two Intel® QuickPath Interconnect point-to-point links capable of up to 6.4 GT/s, up to 12 MB of shared cache, and an Integrated Memory Controller. The processors are optimized for performance with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems.
Introduction product. The reference use condition differs between workstation and server processor SKU’s. Implementing processors outside of reference use conditions may affect reliability performance. 1.1 Processor Features Table 1-1 provides an overview the Intel Xeon processor 5600 series feature set. . Table 1-1.
Introduction Intel Xeon processor 5600 series are based on a low-power micro-architecture that supports operation within various C-states. Additionally, six execution cores and power management coordination logic are optimized to manage C-state support at both the execution core and package levels. An Intel Turbo Boost Technology optimization feature is supported on these processors for improved energy efficiency.
Introduction • Intel® Trusted Execution Technology - A highly versatile set of hardware extensions to Intel processors and chipsets that, with appropriate software, enhance the platform security capabilities. • Intel® QuickPath Interconnect (Intel® QPI) — A cache-coherent, links-based interconnect specification for Intel processors, chipsets, and I/O bridge components.
Introduction 1.4 References Platform designers are strongly encouraged to maintain familiarity with the most up-todate revisions of processor and platform collateral. Table 1-2. References Document Advanced Configuration and Power Interface Specification Compact Electronics Bay Specification: A Server System Infrastructure (SSI) Specification for Value Servers and Workstations Location / Document#1 Notes www.acpi.info. www.ssiforum.
Introduction 16 Intel® Xeon® Processor 5600 Series Datasheet Volume 1
Electrical Specifications 2 Electrical Specifications 2.1 Processor Signaling The Intel Xeon processor 5600 series include 1366 lands, which utilize various signaling technologies. Signals are grouped by electrical characteristics and buffer type into various signal groups.
Electrical Specifications The PECI interface operates at a nominal voltage set by VTTD. The set of DC electrical specifications shown in Table 2-13 is used with devices normally operating from a VTTD interface supply. 2.1.3.1 Input Device Hysteresis The PECI client and host input buffers must use a Schmitt-triggered input design for improved noise immunity. Please refer to Figure 2-2 and Table 2-13. Figure 2-2.
Electrical Specifications Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK_DP, BCLK_DN input, with exceptions for spread spectrum clocking. DC specifications for the BCLK_DP, BCLK_DN inputs are provided in Table 2-14 and AC specifications in Table 2-22. These specifications must be met while also meeting the associated signal quality specifications outlined in Section 3. 2.1.
Electrical Specifications 2.1.7 Power / Other Signals Processors also include various other signals including power/ground, sense points, and analog inputs. Details can be found in Table 2-5. Table 2-1 outlines the required voltage supplies necessary to support Intel Xeon processor 5600 series. Table 2-1. Processor Power Supply Voltages1 Power Rail Nominal Voltage VCC See Table 2-9; Figure 2-3 VCCPLL 1.80 V Each processor includes dedicated VCCPLL and PLL circuits. VDDQ 1.50 V 1.
Electrical Specifications current during longer lasting changes in current demand, for example coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. Care must be taken in the baseboard design to ensure that the voltages provided to the processor remain within the specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime of the processor. 2.1.7.
Electrical Specifications Table 2-2. 22 Voltage Identification Definition (Sheet 2 of 6) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX 0 0 0 0 1 1 0 0 1.53750 0 0 0 0 1 1 0 1 1.53125 0 0 0 0 1 1 1 0 1.52500 0 0 0 0 1 1 1 1 1.51875 0 0 0 1 0 0 0 0 1.51250 0 0 0 1 0 0 0 1 1.50625 0 0 0 1 0 0 1 0 1.50000 0 0 0 1 0 0 1 1 1.49375 0 0 0 1 0 1 0 0 1.48750 0 0 0 1 0 1 0 1 1.48125 0 0 0 1 0 1 1 0 1.
Electrical Specifications Table 2-2. Voltage Identification Definition (Sheet 3 of 6) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX 0 0 1 1 0 1 1 0 1.27500 0 0 1 1 0 1 1 1 1.26875 0 0 1 1 1 0 0 0 1.26250 0 0 1 1 1 0 0 1 1.25625 0 0 1 1 1 0 1 0 1.25000 0 0 1 1 1 0 1 1 1.24375 0 0 1 1 1 1 0 0 1.23750 0 0 1 1 1 1 0 1 1.23125 0 0 1 1 1 1 1 0 1.22500 0 0 1 1 1 1 1 1 1.21875 0 1 0 0 0 0 0 0 1.
Electrical Specifications Table 2-2. 24 Voltage Identification Definition (Sheet 4 of 6) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX 0 1 1 0 0 0 0 0 1.01250 0 1 1 0 0 0 0 1 1.00625 0 1 1 0 0 0 1 0 1.00000 0 1 1 0 0 0 1 1 0.99375 0 1 1 0 0 1 0 0 0.98750 0 1 1 0 0 1 0 1 0.98125 0 1 1 0 0 1 1 0 0.97500 0 1 1 0 0 1 1 1 0.96875 0 1 1 0 1 0 0 0 0.96250 0 1 1 0 1 0 0 1 0.95625 0 1 1 0 1 0 1 0 0.
Electrical Specifications Table 2-2. Voltage Identification Definition (Sheet 5 of 6) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX 1 0 0 0 1 0 1 0 0.75000 1 0 0 0 1 0 1 1 0.74375 1 0 0 0 1 1 0 0 0.73750 1 0 0 0 1 1 0 1 0.73125 1 0 0 0 1 1 1 0 0.72500 1 0 0 0 1 1 1 1 0.71875 1 0 0 1 0 0 0 0 0.71250 1 0 0 1 0 0 0 1 0.70625 1 0 0 1 0 0 1 0 0.70000 1 0 0 1 0 0 1 1 0.69375 1 0 0 1 0 1 0 0 0.
Electrical Specifications Table 2-2. Voltage Identification Definition (Sheet 6 of 6) VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC_MAX 1 0 1 1 0 0 1 0 0.50000 1 1 1 1 1 1 1 0 OFF 1 1 1 1 1 1 1 1 OFF Notes: 1. When the “11111111” VID pattern is observed, or when the SKTOCC# pin is pulled high, the voltage regulator output should be disabled. 2. The VID range includes VID transitions that may be initiated by thermal events, Extended HALT state transitions (see Section 8.
Electrical Specifications 2.1.7.4 Processor VTT Voltage Identification (VTT_VID) Signals The voltage set by the VTT_VID signals is the typical reference voltage regulator (VR) output to be delivered to the processor VTTA and VTTD lands. It is expected that one regulator will supply all VTTA and VTTD lands. VTT_VID signals are CMOS push/pull outputs. Please refer to Table 2-18 for the DC specifications for these signals.
Electrical Specifications 2.2 Signal Group Summary Signals are aligned in Table 2-5 by buffer type and characteristics. “Buffer Type” denotes the applicable signaling technology and specifications. Table 2-5.
Electrical Specifications Table 2-5.
Electrical Specifications • that share symmetry across physical packages with respect to the number of logical processor per package, number of cores per package, number of Intel® QuickPath interfaces, and cache topology. • that have identical Extended Family, Extended Model, Processor Type, Family Code and Model Number as indicated by the Function 1 of the CPUID instruction. Note: Processors must operate with the same Intel® QuickPath Interconnect, DDR3 memory and core frequency.
Electrical Specifications specifications equal to the FMB value in the foreseeable future. System designers should meet the FMB values to ensure their systems will be compatible with future processors. 2.5 Absolute Maximum and Minimum Ratings Table 2-7 specifies absolute maximum and minimum ratings only, which lie outside the functional limits of the processor. Only within specified operation limits, can functionality and long-term reliability be expected.
Electrical Specifications 2.6 Processor DC Specifications DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting specifications for case temperature (TCASE specified in Section 7, “Thermal Specifications”), clock frequency, and input voltages. Care should be taken to read all notes associated with each specification. Table 2-8. Voltage and Current Specifications (Sheet 1 of 2) Symbol Voltage Plane Min 0.
Electrical Specifications Table 2-8. Voltage and Current Specifications (Sheet 2 of 2) Symbol ICC_TDC ICCPLL_TDC IDDQ_TDC ITT_TDC IDDQ_S3 Parameter Voltage Plane Min Typ Max Unit Notes1 Thermal Design Current: Frequency Optimized Server/Workstation (TDP = 130 W) (Launch - FMB) VCC VCCPLL VDDQ VTTA VTTD 110 1.1 9 6 22 A A A A A 11,12 Thermal Design Current: Advanced Server/Workstation (TDP = 95 W) (Launch - FMB) VCC VCCPLL VDDQ VTTA VTTD 101 1.
Electrical Specifications 13.Specification is at TCASE = 50 C. 14.Characterized by design (not tested) Table 2-9. VCC Static and Transient Tolerance ICC (A) VCC_MAX (V) VCC_TYP (V) VCC_MIN (V) 0 VID - 0.000 VID - 0.015 VID - 0.030 5 VID - 0.004 VID - 0.019 VID - 0.034 10 VID - 0.008 VID - 0.023 VID - 0.038 15 VID - 0.012 VID - 0.027 VID - 0.042 20 VID - 0.016 VID - 0.031 VID - 0.046 25 VID - 0.020 VID - 0.035 VID - 0.050 30 VID - 0.024 VID - 0.039 VID - 0.054 35 VID - 0.
Electrical Specifications Figure 2-3. VCC Static and Transient Tolerance Loadlines1,2,3,4 Icc [A] 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 VID - 0.000 VID - 0.020 VID - 0.040 Vcc [V] VID - 0.060 VID - 0.080 VID - 0.100 VID - 0.120 VID - 0.140 VID - 0.160 VID - 0.180 Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.6.1 for VCC overshoot specifications. 2. Refer to Table 2-9 for VCC Static and Transient Tolerance.
Electrical Specifications Figure 2-4. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID Notes: 1. VOS is the measured overshoot voltage. 2. TOS is the measured time duration above VID. 2.6.
Electrical Specifications Figure 2-5. Load Current Versus Time (Frequency Optimized Server/Workstation)1,2 155 150 Sustained Current (A) 145 140 135 130 125 120 115 110 105 0.01 0.1 1 10 100 1000 Time Duration, (s) Notes: 1. 2. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. Not 100% tested. Specified by design characterization.
Electrical Specifications Figure 2-6. Load Current Versus Time (Advanced Server/Workstation)1,2 125.0 Sustained Current (A) 120.0 115.0 110.0 105.0 100.0 95.0 0.01 0.1 1 10 100 1000 Time Duration, (s) Notes: 1. 2. 38 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. Not 100% tested. Specified by design characterization.
Electrical Specifications Figure 2-7. Load Current Versus Time (Standard Server/Workstation)1,2 105 100 Sustained Current (A) 95 90 85 80 75 70 65 0.01 0.1 1 10 100 1000 Time Duration, (s) Notes: 1. 2. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. Not 100% tested. Specified by design characterization.
Electrical Specifications Figure 2-8. Load Current Versus Time (Low Power & LV-60W)1,2 85 Sustained Current (A) 80 75 70 65 60 55 50 45 0.01 0.1 1 10 100 1000 Time Duration, (s) Notes: 1. 2. 40 Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. Not 100% tested. Specified by design characterization.
Electrical Specifications Figure 2-9. Load Current Versus Time (Low Power & LV-40W)1,2 55 Sustained Current (A) 50 45 40 35 0.01 0.1 1 10 100 1000 Time Duration, TVR_AVE (s) Notes: 1. 2. Table 2-11. Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. Not 100% tested. Specified by design characterization. VTT Static and Transient Tolerance (Sheet 1 of 2) ITT (A) VTT_Max (V) VTT_Typ (V) VTT_Min (V) 0 VTT_VID + 0.
Electrical Specifications Table 2-11. VTT Static and Transient Tolerance (Sheet 2 of 2) ITT (A) VTT_Max (V) VTT_Typ (V) VTT_Min (V) 19 VTT_VID - 0.0825 VTT_VID - 0.1140 VTT_VID - 0.1455 20 VTT_VID - 0.0885 VTT_VID - 0.1200 VTT_VID - 0.1515 21 VTT_VID - 0.0945 VTT_VID - 0.1260 VTT_VID - 0.1575 22 VTT_VID - 0.1005 VTT_VID - 0.1320 VTT_VID - 0.1635 23 VTT_VID - 0.1065 VTT_VID - 0.1380 VTT_VID - 0.1695 24 VTT_VID - 0.1125 VTT_VID - 0.1440 VTT_VID - 0.1755 25 VTT_VID - 0.
Electrical Specifications Table 2-12. DDR3 and DDR3L Signal Group DC Specifications Symbol Parameter VIL Input Low Voltage VIH Input High Voltage VOL VOH Min Typ Notes1 Max Units 0.43*VDDQ V 2, V 3, 4 0.
Electrical Specifications Table 2-13. PECI Signal DC Electrical Limits (Sheet 2 of 2) Symbol Definition and Conditions Min Max Units Notes1 ILeak- High impedance leakage to GND (Vleak = VOH) N/A 25 µA 3 CBus Bus capacitance per node N/A 10 pF 4,5 VNoise Signal noise immunity above 300 MHz 0.100 * VTTD N/A Vp-p Note: 1. VTTD supplies the PECI interface. PECI behavior does not affect VTTD min/max specifications. 2.
Electrical Specifications Table 2-16. TAP Signal Group DC Specifications Symbol Parameter Min VIL Input Low Voltage VIH Input High Voltage VOL Input Low Voltage VOH Input High Voltage VTTA RON Buffer On Resistance 10 ILI Input Leakage Current Typ Max Units Notes1 0.40 * VTTA V 2 V 2,4 V 2 V 2,4 0.60 * VTTA VTTA * RON / (RON + Rsys_term) 18 ± 200 A 3 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
Electrical Specifications Table 2-18.
Electrical Specifications 2.7 Intel® QuickPath Interconnect Specifications Intel QuickPath Interconnect specifications are defined at the processor pins. In most cases, termination resistors are not required as these are integrated into the processor silicon (Refer to Table 2-6). Table 2-19. Common Intel® QuickPath Interconnect Specifications Symbol Parameter Min Nom Max Unit 0.999 * Nom 1000/f 1.001 * Nom psec UIavg Avg UI size at “f” GT/s (f = 4.8, 5.86, or 6.
Electrical Specifications Notes: 1. Used during initialization. It is the state of “OFF” condition for the transmitter. That is, when the output driver is disconnected and only the minimum termination is connected. The link detection resistor is assumed not connected when specifying this parameter. 2. Used during initialization. It is the state of “OFF” condition for the receiver when only the minimum termination is connected. Table 2-20. Parameter Values for Intel® QuickPath Interconnect Channels at 4.
Electrical Specifications Table 2-21. Parameter Values for Intel® QuickPath Interconnect Channel at 5.86 or 6.4 GT/s Symbol Parameter Min Max Unit VTx-diff-pp-pin Transmitter differential swing 800 1400 mV VTx-cm-dc-pin Transmitter output DC common mode, defined as average of VD+ and VD–. Use setup of Figure 2-11. 0.23 0.27 Fraction of VTX-diff-pp-pin VTx-cm-ac-pin Transmitter output AC common mode, defined as ((VD+ + VD–)/2 - VTX-cm-dc-pin).
Electrical Specifications Table 2-22. System Reference Clock AC Specifications (Sheet 2 of 2) Parameter Min ERBCLK-diffRise, ERBCLK-diffFall 1.0 TBCLK-Dutycycle 40 Nom Max Unit Figure Notes1 4.0 V/ns 2-18 3 60 % 2-17 500 ps 50 TBCLK-diff-jit 4 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. SSC is Spread Spectrum Clocking. The processor core clock frequency is derived from BCLK.
Electrical Specifications Table 2-23. DDR3/DDR3L Electrical Characteristics and AC Specifications at 800 MT/s (Sheet 2 of 2) Symbol Parameter TDQS_CO DQS Edge Placement Accuracy to CK Rising Edge AFTER write leveling TWPRE DQS/DQS# Write Preamble Duration TWPST DQS/DQS# Write Postamble Duration TDQSS CK Rising Edge Output Access Time, Where a Write Command Is Referenced, to the First DQS Rising Edge Channel 0 Channel 1 Channel 2 Unit Max Min +275 -275 ns 2.379 ns 1.129 ns 1.
Electrical Specifications Table 2-24. DDR3 Electrical Characteristics and AC Specifications at 1066 MT/s (Sheet 2 of 2) Symbol Channel 0 Channel 1 Channel 2 Parameter Unit Max Min <2.50 1.875 ns Figure Note Clock Timings TCK CLK Period TCH CLK High Time 1.25 0.94 ns TCL CLK Low Time 1.25 0.
Electrical Specifications 6. 7. 8. The system memory clock outputs are differential (CLK and CLK#), the CLK rising edge is referenced at the crossing point where CLK is rising and CLK# is falling. The system memory strobe outputs are differential (DQS and DQS#), the DQS rising edge is referenced at the crossing point where DQS is rising and DQS# is falling, and the DQS falling edge is referenced at the crossing point where DQS is falling and DQS# is rising.
Electrical Specifications Table 2-25. DDR3/DDR3L Electrical Characteristics and AC Specifications at 1333 MT/s (Sheet 2 of 2) Symbol Channel 0 Channel 1 Channel 2 Parameter Max TWPRE DQS/DQS# Write Preamble Duration TWPST DQS/DQS# Write Postamble Duration TDQSS CK Rising Edge Output Access Time, Where a Write Command Is Referenced, to the First DQS Rising Edge 0.825 CWL x (TCK + 4) Unit Figure Note Min 1.425 ns 0.674 ns ns 5,6 Notes: 1.
Electrical Specifications Table 2-26. Processor Sideband Signal Group AC Specifications T# Parameter Min Asynchronous GTL input pulse width 8 Tb: VTT stable to VTTPWRGOOD assertion 1 Tf: VTTPWRGOOD to valid VID Th: VCC stable to VCCPWRGOOD assertion Figure Notes 1,2,3,4 BCLKs ms 2-28 5,7,8,10 10 µs 2-28 9 ns 2-28 5,6,7 0 10 µs 2-28 0.
Electrical Specifications Table 2-27. TAP Signal Group AC Specifications T# Parameter TCK Period Ts: TDI, TMS Setup Time Th: TDI, TMS Hold Time Tx: TDO Clock to Output Delay Tq: TRST# Assert Time Min Max Unit Figure 31.25 ns 1 ns 2-25 1 0.5 4 2 ns 2-25 ns 2-25 TTCK 2-26 Notes 1,2,3 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Not 100% tested. Specified by design characterization. 3.
Electrical Specifications Figure 2-11. Intel® QuickPath Interconnect Electrical Test Setup for Validating Standalone TX Voltage and Timing Parameters Ideal Loads Silicon TX Tx Package SI Tx pin terminations are set to optimum values (targeted around 42.5 ohms single-ended) Figure 2-12.
Electrical Specifications Figure 2-13. Distribution Profile of Common Mode Noise for Either Tx or Rx 0.5* (VD+ - VD-) - X_cm_dc_pin Figure 2-14.
Electrical Specifications Figure 2-15. Eye Mask at the End of Tx + Channel Voltage Margin Distribution Probability = 1E -9 Timing Margin Distribution VRx-diff-pp-pin Probability = 1E -9 TRx-diff-pp-pin Figure 2-16. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 250 + 0.
Electrical Specifications Figure 2-17. Differential Clock Measurement Points for Duty Cycle and Period Figure 2-18. Differential Clock Measurement Points for Rise and Fall time Figure 2-19.
Electrical Specifications Figure 2-20. Single-Ended Clock Measurement Points for Delta Cross Point Figure 2-21. Differential Clock Measurement Point for Ringback Figure 2-22.
Electrical Specifications Figure 2-23. DDR3 Clock to Output Timing Waveform Figure 2-24.
Electrical Specifications Figure 2-25. TAP Valid Delay Timing Waveform Note: Please refer to Table 2-18 for TAP Signal Group DC specifications and Table 2-27 for TAP Signal Group AC specifications. Figure 2-26. Test Reset (TRST#), Asynch GTL Input, and PROCHOT# Timing Waveform V Tq T = PROCHOT# Pulse Width, V = VTTA q TRST# Assert Time, V = 0.5 * VTTA Figure 2-27.
RESET# BCLK VCCPWRGOOD VCC VCC VID[7:0] VTTPWRGOOD VDDPWRGOOD VDDQ VCCPLL VTT_VID[2:0] VTT Td VTTFINAL VCCBOOT VLFM Th LFM VID From CPU Tm Tj Te Ti VTT VID FINAL VTT must be stable before VCCPWRGOOD assertion Refer to VRD11.
Electrical Specifications Note: In order In order to ensure Timestamp Counter (TSC) synchronization across sockets in multi-socket systems, the RESET# deassertion edge should arrive at the same BCLK rising edge at both sockets and should meet the Tsu and Th requirement of 600ps relative to BCLK, as outlined in Table 2-26. Figure 2-29.
Electrical Specifications 66 Intel® Xeon® Processor 5600 Series Datasheet Volume 1
Signal Quality Specifications 3 Signal Quality Specifications Data transfer requires the clean reception of data and clock signals. Ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swings will adversely affect system timings. Ringback and signal non-monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines.
Signal Quality Specifications Figure 3-1.
Package Mechanical Specifications 4 Package Mechanical Specifications 4.1 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA) package that interfaces with the baseboard via an LGA1366 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Package Mechanical Specifications 4.1.1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 4-2 and Figure 4-3. The drawings include dimensions necessary to design a thermal solution and reflect the processor as received by Intel. These dimensions include: 1. Package reference with tolerances (total height, length, width, and so forth) 2. IHS parallelism and tilt 3. Land dimensions 4. Top-side and back-side component keep-out dimensions 5. Reference datums 6.
Package Mechanical Specifications Figure 4-2.
Package Mechanical Specifications Figure 4-3.
Package Mechanical Specifications 4.1.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keep-out zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Do not contact the Test Pad Area with conductive material. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 4-2 and Figure 4-3 for keep-out zones.
Package Mechanical Specifications 4.1.6 Processor Mass Specification The typical mass of the processor is 35 grams. This mass [weight] includes all the components that are included in the package. 4.1.7 Processor Materials Table 4-3 lists some of the package components and associated materials. Table 4-3. Processor Materials Component Material Integrated Heat Spreader (IHS) Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands 4.1.
Land Listing 5 Land Listing 5.1 Listing by Land Name Table 5-1. By Land Name (Sheet 1 of 36) Land Name BCLK_DN Table 5-1. By Land Name (Sheet 2 of 36) Land No. Buffer Type Direction AH35 CMOS I QPI0_DRX_DN[6] Land Name Land No.
Land Listing Table 5-1. By Land Name (Sheet 3 of 36) Land Name Land No. Buffer Type Direction Table 5-1. By Land Name (Sheet 4 of 36) Land Name Land No.
Land Listing Table 5-1. By Land Name (Sheet 5 of 36) Land Name Land No. Buffer Type Direction Table 5-1. By Land Name (Sheet 6 of 36) Land Name Land No.
Land Listing Table 5-1. By Land Name (Sheet 7 of 36) Land No. Buffer Type Direction DDR0_DQ[26] A38 CMOS I/O DDR0_DQ[27] D37 CMOS I/O DDR0_DQ[28] D41 CMOS DDR0_DQ[29] D42 CMOS Land Name Table 5-1. By Land Name (Sheet 8 of 36) Land No.
Land Listing Table 5-1. By Land Name (Sheet 9 of 36) Land Name Land No. Buffer Type Direction Table 5-1. By Land Name (Sheet 10 of 36) Land Name Land No.
Land Listing Table 5-1. By Land Name (Sheet 11 of 36) Table 5-1. By Land Name (Sheet 12 of 36) Land No.
Land Listing Table 5-1. By Land Name (Sheet 13 of 36) Table 5-1. By Land Name (Sheet 14 of 36) Land No.
Land Listing Table 5-1. By Land Name (Sheet 15 of 36) Land Name Land No. Buffer Type Direction Table 5-1. By Land Name (Sheet 16 of 36) Land Name Land No.
Land Listing Table 5-1. By Land Name (Sheet 17 of 36) Table 5-1. By Land Name (Sheet 18 of 36) Land No. Buffer Type Direction DDR2_MA[1] K17 CMOS O RSVD AK2 DDR2_MA[10] H17 CMOS O RSVD AK7 Land Name Land Name Land No.
Land Listing Table 5-1. By Land Name (Sheet 19 of 36) Land Name Land No. Buffer Type Table 5-1. Direction By Land Name (Sheet 20 of 36) Land Name Land No.
Land Listing Table 5-1. By Land Name (Sheet 21 of 36) Land No. Buffer Type VCC AN30 PWR VCC AN31 PWR VCC AN33 VCC AN34 VCC VCC Table 5-1. By Land Name (Sheet 22 of 36) Land No.
Land Listing Table 5-1. By Land Name (Sheet 23 of 36) Land No. Buffer Type VCC AV31 PWR VCC AV33 PWR VCC AV34 VCC AV9 VCC VCC Table 5-1. By Land Name (Sheet 24 of 36) Land No.
Land Listing Table 5-1. By Land Name (Sheet 25 of 36) Table 5-1. By Land Name (Sheet 26 of 36) Land No.
Land Listing Table 5-1. By Land Name (Sheet 27 of 36) Land Name Land No. Buffer Type Table 5-1. Direction By Land Name (Sheet 28 of 36) Land Name Land No.
Land Listing Table 5-1. By Land Name (Sheet 29 of 36) Table 5-1. By Land Name (Sheet 30 of 36) Land No.
Land Listing Table 5-1. By Land Name (Sheet 31 of 36) Table 5-1. By Land Name (Sheet 32 of 36) Land No. Buffer Type VSS B37 GND VSS J13 GND VSS B42 GND VSS J3 GND VSS BA11 GND VSS J33 GND VSS BA14 GND VSS J38 GND VSS BA17 GND VSS J43 GND VSS BA20 GND VSS J8 GND VSS BA26 GND VSS K1 GND VSS BA29 GND VSS K11 GND Land Name Direction Land Name Land No.
Land Listing Table 5-1. By Land Name (Sheet 33 of 36) Land Name Land No. Buffer Type Table 5-1. Direction By Land Name (Sheet 34 of 36) Land Name Land No.
Land Listing Table 5-1. By Land Name (Sheet 35 of 36) Table 5-1. By Land Name (Sheet 36 of 36) Land No. Buffer Type VTTD AD34 PWR VTTD AD35 PWR VTTD AD36 VTTD AD9 VTTD AE34 PWR VTTD AF9 PWR VTTD AE35 PWR VTTD_SENSE AE36 Analog VTTD AE8 PWR VTTPWRGOOD AB35 Asynch Land Name 5.2 Land No. Buffer Type VTTD AE9 PWR VTTD AF36 PWR PWR VTTD AF37 PWR PWR VTTD AF8 PWR Direction Land Name Direction I Listing by Land Number Table 5-2.
Land Listing Table 5-2. By Land Number (Sheet 3 of 35) Land Name Land No. QPI0_DTX_DP[17] VSS Table 5-2. By Land Number (Sheet 4 of 35) Buffer Type Direction AB39 QPI O VTTD AD36 PWR AB4 GND VSS AD37 GND Land Name Land No.
Land Listing Table 5-2. By Land Number (Sheet 5 of 35) Table 5-2. By Land Number (Sheet 6 of 35) Land No. Buffer Type VTTA AF33 PWR VCC VTTA AF34 PWR QPI1_DTX_DP[9] Land Name Direction Land Name Land No.
Land Listing Table 5-2. By Land Number (Sheet 7 of 35) Table 5-2. By Land Number (Sheet 8 of 35) Land No. Buffer Type TDI AJ9 TAP I RSVD AK7 QPI1_DTX_DP[7] AK1 QPI O ISENSE Land Name Direction Land Name Land No.
Land Listing Table 5-2. By Land Number (Sheet 9 of 35) Land Name Land No. Buffer Type Table 5-2. By Land Number (Sheet 10 of Direction Land Name Land No.
Land Listing Table 5-2. By Land Number (Sheet 11 of Land Name Land No. Buffer Type Direction QPI0_DRX_DP[15] VSS AN40 QPI I AN41 GND QPI0_DRX_DN[13] AN42 QPI QPI0_DRX_DP[14] AN43 QPI Table 5-2. By Land Number (Sheet 12 of Land Name Land No.
Land Listing Table 5-2. By Land Number (Sheet 13 of Land Name Land No. Buffer Type Direction I RSVD AR37 QPI0_DRX_DN[19] AR38 QPI VSS AR39 GND AR4 QPI QPI1_DRX_DP[11] Table 5-2. By Land Number (Sheet 14 of Land No.
Land Listing Table 5-2. By Land Number (Sheet 15 of Land No. Buffer Type VCC AU33 PWR VCC AU34 PWR VSS AU35 VSS AU36 QPI0_DRX_DN[0] AU37 QPI QPI0_DRX_DP[1] AU38 QPI QPI0_DRX_DP[7] AU39 QPI1_DRX_DP[8] AU4 Land Name Table 5-2. By Land Number (Sheet 16 of Land No.
Land Listing Table 5-2. By Land Number (Sheet 17 of Land Name QPI1_DRX_DN[7] Land No. Buffer Type Direction I Table 5-2. By Land Number (Sheet 18 of Land Name RSVD Land No.
Land Listing Table 5-2. By Land Number (Sheet 19 of Land Name Land No. Buffer Type Direction Table 5-2. By Land Number (Sheet 20 of Land Name Land No.
Land Listing Table 5-2. By Land Number (Sheet 21 of Land No. Buffer Type Direction DDR0_DQ[30] C38 CMOS I/O DDR0_DQS_N[12] C39 CMOS I/O I/O Land Name DDR0_DQ[33] Table 5-2. By Land Number (Sheet 22 of Land No.
Land Listing Table 5-2. By Land Number (Sheet 23 of Land No. Buffer Type Direction DDR1_ECC[6] E34 CMOS I/O DDR1_DQS_N[17] E35 CMOS I/O Land Name Table 5-2. By Land Number (Sheet 24 of Land No.
Land Listing Table 5-2. By Land Number (Sheet 25 of Table 5-2. By Land Number (Sheet 26 of Land No. Buffer Type Direction DDR2_DQS_N[8] G30 CMOS I/O RSVD DDR2_DQS_N[17] G31 CMOS I/O DDR0_DQ[45] Land Name Land Name Land No.
Land Listing Table 5-2. By Land Number (Sheet 27 of Land No. Buffer Type Direction DDR1_MA[6] J27 CMOS O VDDQ J28 PWR RSVD J29 Land Name VSS Table 5-2. By Land Number (Sheet 28 of Land Name Land No.
Land Listing Table 5-2. By Land Number (Sheet 29 of Land No. Buffer Type Direction DDR_VREF L23 Analog I VDDQ L24 PWR Land Name Table 5-2. By Land Number (Sheet 30 of Land No.
Land Listing Table 5-2. By Land Number (Sheet 31 of Land Name DDR1_DQ[11] DDR2_DQS_P[15] Land No. Table 5-2. By Land Number (Sheet 32 of Buffer Type Direction N39 CMOS I/O VSS R36 GND N4 CMOS I/O DDR1_DQS_N[1] R37 CMOS I/O VSS N40 GND DDR0_DQ[8] N41 CMOS Land Name Land No.
Land Listing Table 5-2. By Land Number (Sheet 33 of Land Name Land No. Buffer Type Table 5-2.
Land Listing Table 5-2. By Land Number (Sheet 35 of Land Name Land No.
Land Listing 110 Intel® Xeon® Processor 5600 Series Datasheet Volume 1
Signal Definitions 6 Signal Definitions 6.1 Signal Definitions Table 6-1. Signal Definitions (Sheet 1 of 4) Name Type Description BCLK_DN BCLK_DP I Differential bus clock input to the processor. BCLK_ITP_DN BCLK_ITP_DP O Buffered differential bus clock pair to ITP. BPM#[7:0] I/O BPM#[7:0] are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance.
Signal Definitions Table 6-1. Signal Definitions (Sheet 2 of 4) Name Type Description DBR# I DBR# is used only in systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. DDR_COMP[2:0] I Must be terminated on the system board using precision resistors. DDR_THERM# I DDR_THERM# is used for imposing duty cycle throttling on all memory channels.
Signal Definitions Table 6-1. Name Signal Definitions (Sheet 3 of 4) Type Description I/O PROCHOT# will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal can also be driven to the processor to activate the Thermal Control Circuit.
Signal Definitions Table 6-1. Name Signal Definitions (Sheet 4 of 4) Type Description VCCPWRGOOD I VCCPWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that BCLK, VCC, VCCPLL, VTTA and VTTD supplies are stable and within their specifications. 'Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Thermal Specifications 7 Thermal Specifications 7.1 Package Thermal Specifications The processor requires a thermal solution to maintain temperatures within operating limits. Any attempt to operate the processor outside these limits may result in permanent damage to the processor and potentially other components within the system. Maintaining the proper thermal environment is key to reliable, long-term system operation.
Thermal Specifications The processor Advanced Server/Workstation Platform supports dual thermal profiles, either of which can be implemented. Both ensure adherence to Intel reliability requirements. Thermal Profile A is representative of a volumetrically unconstrained thermal solution (that is, industry enabled 2U heatsink). In this scenario, it is expected that the Thermal Control Circuit (TCC) would only be activated for very brief periods of time when running the most power intensive applications.
Thermal Specifications Figure 7-1. Frequency Optimized Server/Workstation Platform Thermal Profile (6 Core) 85 80 75 70 Temperature [C] Y = 0.176 *x + 55.6 65 60 55 50 45 40 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Power [W] Notes: 1. The Frequency Optimized Server/Workstation Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 7-2 for discrete points that constitute the thermal profile. 2.
Thermal Specifications Figure 7-2. Frequency Optimized Server/Workstation Platform Thermal Profile (4 Core) 85 80 75 70 Temperature [C] Y = 0.190 *x + 55.7 65 60 55 50 45 40 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Power [W] Notes: 1. The Frequency Optimized Server/Workstation Thermal Profile is representative of a volumetrically unconstrained platform. Please refer to Table 7-3 for discrete points that constitute the thermal profile. 2.
Thermal Specifications Table 7-4. Advanced Server/Workstation Platform Thermal Specifications Core Frequency Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Launch to FMB 95 5 See Figure 7-3, Figure 7-4, Table 7-5, Table 7-6, Table 7-7, Table 7-8 Notes 1, 2, 3, 4 Notes: 1. These values are specified at VCC_MAX for all processor frequencies.
Thermal Specifications Table 7-5. Table 7-6. 120 Advanced Server/Workstation Thermal Profile A (6 Core) Power (W) Maximum TCASE (C) 0 56.9 10 58.7 20 60.5 30 62.3 40 64.1 50 65.9 60 67.7 70 69.5 80 71.3 90 73.1 95 74.0 Advanced Server/Workstation Thermal Profile B (6 Core) Power (W) Maximum TCASE (C) 0 56.9 10 59.5 20 62.0 30 64.6 40 67.2 50 69.8 60 72.3 70 74.9 80 77.5 90 80.0 95 81.
Thermal Specifications Figure 7-4. Advanced Server/Workstation Platform Thermal Profile A and B (4 Core) TCASE_MAX is a thermal solution design point. In actuality, units will not significantly exceed TCASE_MAX_A due to TCC activation. 90 85 80 75 Temperature [C] Thermal Profile B Y = 0.272 * x + 57.1 70 Thermal Profile A Y = 0.195 * x + 57.1 65 60 55 50 45 40 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 Pow er [W] Notes: 1.
Thermal Specifications Table 7-8. Table 7-9. Advanced Server/Workstation Thermal Profile B (4 Core) Power (W) Maximum TCASE (C) 0 57.1 10 59.8 20 62.5 30 65.3 40 68.0 50 70.7 60 73.4 70 76.1 80 78.8 90 81.6 95 82.9 Standard Server/Workstation Platform Thermal Specifications Core Frequency Launch to FMB Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) 80 5 See Figure 7-5; Table 7-10, Figure 7-6, Table 7-11 Notes 1, 2, 3, 4 Notes: 1.
Thermal Specifications Figure 7-5. Standard Server/Workstation Platform Thermal Profile (6 Core) 80 75 70 Temperature [C] Y = 0.306*x + 51.7 65 60 55 50 45 0 10 20 30 40 50 60 70 80 Powe r [W] Notes: 1. The Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 7-10 for discrete points that constitute the thermal profile. 2. Implementation of the Thermal Profile should result in virtually no TCC activation.
Thermal Specifications Figure 7-6. Standard Server/Workstation Platform Thermal Profile (4 Core) 80 75 70 Temperature [C] Y = 0.321*x + 51.9 65 60 55 50 45 0 10 20 30 40 50 60 70 80 Power [W] Notes: 1. The Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 7-11 for discrete points that constitute the thermal profile. 2. Implementation of the Thermal Profile should result in virtually no TCC activation.
Thermal Specifications Table 7-12. Low Power Platform 60W Thermal Specifications Core Frequency Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes 60 5 See Figure 7-7; Table 7-13 1, 2, 3, 4 Launch to FMB Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC.
Thermal Specifications Table 7-13. Low Power Platform 60W Thermal Profile (6 Core) (Sheet 2 of 2) Power (W) Maximum TCASE (C) 30 60.2 40 63.2 50 66.3 60 69.4 Table 7-14. Low Power Platform 40W Thermal Specifications Core Frequency Launch to FMB Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) Notes 40 5 See Figure 7-8; Table 7-15 1, 2, 3, 4 Notes: 1. These values are specified at VCC_MAX for all processor frequencies.
Thermal Specifications 3. Refer to the Intel® Xeon® Processor 5500/5600 Series Thermal/Mechanical Design Guidelines for system and environmental implementation details. Table 7-15. Low Power Platform 40W Thermal Profile (4 Core) Power (W) Maximum TCASE (C) 0 50.4 10 53.6 20 56.8 30 59.9 40 63.1 Table 7-16.
Thermal Specifications 2. 3. 4. 5. Implementation of the nominal and short-term Thermal Profiles should result in virtually no TCC activation. Utilization of thermal solutions that do not meet the Thermal Profile will result in increased probability of TCC activation and may incur measurable performance loss. The Nominal Thermal Profile must be used for all normal operating conditions, or for products that do not require NEBS Level 3 compliance.
Thermal Specifications Figure 7-10. LV-40W Processor Dual Thermal Profile Notes: 1. The Thermal Profile is representative of a volumetrically constrained platform. Please refer to Table 7-19 for discrete points that constitute the thermal profile. 2. Implementation of the nominal and short-term Thermal Profiles should result in virtually no TCC activation.
Thermal Specifications 7.1.2 Thermal Metrology The minimum and maximum case temperatures (TCASE) are specified in Table 7-1,Table 7-4, Table 7-9. Table 7-12, Table 7-14, Table 7-16 and Table 7-18 and are measured at the geometric top center of the processor integrated heat spreader (IHS). Figure 7-11 illustrates the location where TCASE temperature measurements should be made.
Thermal Specifications temperature is calibrated on a part-by-part basis and normal factory variation may result in the actual TCC activation temperature being higher than the value listed in the register. TCC activation temperatures may change based on processor stepping, frequency or manufacturing efficiencies.
Thermal Specifications frequencies and voltages. When the TCC is activated, the processor automatically transitions to the new operating frequency. This transition occurs very rapidly (on the order of 2 µs). Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps to support this method.
Thermal Specifications modulation is automatically engaged as part of the TCC activation when the Frequency/VID targets are at their minimum settings. It may also be initiated by software at a configurable duty cycle. 7.2.3 On-Demand Mode The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “OnDemand” mode and is distinct from the Adaptive Thermal Monitor feature.
Thermal Specifications With a properly designed and characterized thermal solution, it is anticipated that PROCHOT# will only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. 7.2.
Thermal Specifications will accept lower bit rates from a host according to timing negotiation specifications. What follows is a processor-specific PECI client definition. PECI commands listed in Table 7-20 apply to Intel Xeon processor 5600 series only. Table 7-20. Summary of Processor-Specific PECI Commands Command Intel® Xeon® Processor 5600 Series Support Ping() Yes GetDIB() Yes GetTemp() Yes PCIConfigRd() Yes PCIConfigWr() Yes MbxSend() MbxGet() 1 1 Yes Yes Note: 1.
Thermal Specifications 7.3.1.3 Processor Interface Tuning and Diagnostics Intel Xeon processor 5600 series Intel IBIST allows for in-field diagnostic capabilities in Intel QuickPath Interconnect and memory controller interfaces. PECI provides a port to execute these diagnostics via its PCI Configuration read and write capabilities. 7.3.2 Client Command Suite 7.3.2.1 Ping() Ping() is a required message for all PECI devices.
Thermal Specifications Figure 7-15. GetDIB() Byte # Byte Definition 7.3.2.2.2 0 1 2 3 4 Client Address Write Length 0x01 Read Length 0x08 Cmd Code 0xf7 FCS 5 6 7 8 9 Device Info Revision Number Reserved Reserved Reserved 10 11 12 13 Reserved Reserved Reserved FCS Device Info The Device Info byte gives details regarding the PECI client configuration. At a minimum, all clients supporting GetDIB will return the number of domains inside the package via this field.
Thermal Specifications 7.3.2.3 GetTemp() The GetTemp() command is used to retrieve the temperature from a target PECI address. The temperature is used by the external thermal management system to regulate the temperature on the die. The data is returned as a negative value representing the number of degrees centigrade below the Thermal Control Circuit Activation temperature of the PECI device. Note that a value of zero represents the temperature at which the Thermal Control Circuit activates.
Thermal Specifications Table 7-21. GetTemp() Response Definition Response 7.3.2.4 Meaning General Sensor Error (GSE) Thermal scan did not complete in time. Retry is appropriate. 0x0000 Processor is running at its maximum temperature or is currently being reset. All other data Valid temperature reading, reported as a negative offset from the TCC activation temperature.
Thermal Specifications command responses are prepended with a completion code that includes additional pass/fail status information. Refer to Section 7.3.4.2 for details regarding completion codes. Figure 7-21. PCIConfigRd() Byte # Byte Definition 0 1 2 3 Client Address Write Length 0x05 Read Length {0x02,0x03,0x05} Cmd Code 0xc1 4 5 LSB 6 PCI Configuration Address 9 10 Completion Code Data 0 ...
Thermal Specifications Table 7-23. PCIConfigWr() Device/Function Support (Sheet 2 of 2) Writable Description Device Function 4 3 Memory Controller Channel 0 Thermal Control / Status 5 3 Memory Controller Channel 1 Thermal Control / Status 6 3 Memory Controller Channel 2 Thermal Control / Status Note: 1. Currently not available for access through the PECI PCIConfigWr() command.
Thermal Specifications Figure 7-22. PCIConfigWr() Byte # Byte Definition 0 1 2 3 Client Address Write Length {0x07,0x08,0x10} Read Length 0x01 Cmd Code 0xc5 4 LSB 5 6 PCI Configuration Address 8 LSB WL AW FCS 7 MSB WL-1 Data (1, 2 or 4 bytes) MSB WL+1 WL+2 WL+3 FCS Completion Code FCS Note that the 4-byte PCI configuration address and data defined above are sent in standard PECI ordering with LSB first and MSB last. 7.3.2.5.
Thermal Specifications 7.3.2.6.1 Capabilities Table 7-25. Mailbox Command Summary Request Type Code (byte) MbxSend Data (dword) MbxGet Data (dword) Ping 0x00 0x00 0x00 Thermal Status Read/Clear 0x01 Log bit clear mask Thermal Status Register Counter Snapshot 0x03 0x00 0x00 Counter Clear 0x04 0x00 0x00 Counter Read 0x05 Counter Number Counter Data Command Name Description Verify the operability / existence of the Mailbox.
Thermal Specifications These status bits are a subset of the bits defined in the IA32_THERM_STATUS MSR on the processor, and more details on the meaning of these bits may be found in the Intel 64 and IA-32 Architectures Software Developer’s Manual, Vol 3B. Both status and sticky log bits are managed in this status word. All sticky log bits are set upon a rising edge of the associated status bit, and the log bits are cleared only by Thermal Status reads or a processor reset.
Thermal Specifications 7.3.2.6.5 Icc-TDC Read Icc-TDC is the processor Thermal Design Current specification. This data may be used to confirm matching Icc profiles of processors in DP configurations. It may also be used during the processor boot sequence to verify processor compatibility with baseboard Icc delivery capabilities. This command returns Icc-TDC in units of 1 Amp. 7.3.2.6.6 TCONTROL Read TCONTROL is used for fan speed control management.
Thermal Specifications Table 7-27.
Thermal Specifications Table 7-27.
Thermal Specifications Table 7-27. Machine Check Bank Definitions (Sheet 3 of 3) 7.3.2.6.
Thermal Specifications Duty Cycle Code Definition 0x4 50% clocks on / 50% clocks off 0x5 62.5% clocks on / 37.5% clocks off 0x6 75% clocks on / 25% clocks off 0x7 87.5% clocks on / 12.5% clocks off The T-state control word is defined as follows: Figure 7-26. ACPI T-State Throttling Control Read / Write Definition 7.3.2.6.10 Energy Accumulator Read Intel Xeon processor 5600 series energy consumption may be monitored with regular reads of the free running Energy Accumulator.
Thermal Specifications Figure 7-27. Energy Accumulator Register Definition Example 7-1.Sample Energy Accumulator Read and Power Calculation.
Thermal Specifications This capability may not be available on all products. To enumerate availability, users may issue an Energy Accumulator Read command. Products that return a passing completion code support the command. 7.3.2.7 MbxSend() The MbxSend() command is utilized for sending requests to the generic Mailbox interface. Those requests are in turn serviced by the processor with some nominal latency and the result is deposited in the mailbox for reading.
Thermal Specifications Figure 7-29. MbxSend() Byte # Byte Definition 0 1 2 3 Client Address Write Length 0x07 Read Length 0x01 Cmd Code 0xd1 4 5 6 7 Request Type LSB 9 10 11 12 AW FCS FCS Completion Code FCS Data[31:0] 8 MSB Note that the 4-byte data defined above is sent in standard PECI ordering with LSB first and MSB last. Table 7-29.
Thermal Specifications Unlike MbxSend(), no Assured Write protocol is necessary for this command because this is a read-only function. 7.3.2.8.2 Command Format The MbxGet() format is as follows: Write Length: 2 Read Length: 5 Command: 0xd5 Multi-Domain Support: Yes (see Table 7-32) Description: Retrieves response data from mailbox and unlocks / releases that mailbox resource. Figure 7-30.
Thermal Specifications Table 7-30. MbxGet() Response Definition (Sheet 2 of 2) Response Meaning 0x88 Machine Check Banks is currently unavailable (selected core is asleep or unavailable) 0x89 Invalid Core Select for Machine Check Bank Read 0xFF Unknown/Invalid Mailbox Request 7.3.2.9 Mailbox Usage Definition 7.3.2.9.1 Acquiring the Mailbox The MbxSend() command is used to acquire control of the PECI mailbox and issue information regarding the specific request.
Thermal Specifications cleared. In the event that this timeout occurs, the originating agent will receive a failed completion code upon issuing a MbxGet() command, or even worse, it may receive corrupt data if this MbxGet() command so happens to be interleaved with an MbxSend() from another process. Please refer to Table 7-30 for more information regarding failed completion codes from MbxGet() commands.
Thermal Specifications • Assured Write FCS (AW FCS) failure. Note that under most circumstances, an Assured Write failure will appear as a bad FCS. However, when an originator issues a poorly formatted command with a miscalculated AW FCS, the client will intentionally abort the FCS in order to guarantee originator notification. 7.3.4.2 Completion Codes Some PECI commands respond with a completion code byte.
Thermal Specifications 7.3.5 Originator Responses The simplest policy that an originator may employ in response to receipt of a failing completion code is to retry the request. However, certain completion codes or FCS responses are indicative of an error in command encoding and a retry will not result in a different response from the client. Furthermore, the message originator must have a response policy in the event of successive failure responses.
Thermal Specifications PECI temperature readings are not reliable at temperatures above TCC activation (since the processor is operating out of spec at this temperature). Therefore, the readings are never positive. 7.3.6.3 Temperature Filtering The processor digital thermal sensor (DTS) provides an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals.
Thermal Specifications In the event that the processor is tri-stated using power-on-configuration controls, the PECI client will also be tri-stated. Figure 7-32. PECI Power-Up Timeline Vtt VttPwrGd SupplyVcc Bclk VccPwrGd RESET# Mclk CSI training CSI pins uOp execution In Reset PECI Client Status PECI Node ID 7.3.7.
Thermal Specifications • Ping(), GetDIB(), GetTemp() and MbxGet() have no impact on processor power under C-states. All other commands (MbxSend(), PCIConfigRd() and PCIConfigWr()) result in the same behavior, as follows: • MbxSend(), PCIConfigRd() and PCIConfigWr() usage under package C-states may result in increased power consumption because the processor must temporarily return to a C0 state in order to execute the request.
Thermal Specifications Notes: 1. Storage conditions are applicable to storage environments only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, please refer to the processor case temperature specifications. 2. These ratings apply to the Intel component and do not include the tray or packaging. 3.
Thermal Specifications 162 Intel® Xeon® Processor 5600 Series Datasheet Volume 1
Features 8 Features 8.1 Power-On Configuration (POC) Several configuration options can be configured by hardware. Power-On configuration (POC) functionality is either MUx’ed onto VID signals (see Section 2.1.7.3.1) or sampled on the active-to-inactive transition of RESET#. For specifics on these options, please refer to Table 8-1.
Features Power-On Configuration (POC) logic levels are MUX’ed onto the VID[7:0] signals with 1-5 k pull-up and pull-down resistors located on the baseboard. These include: • VID[2:0] / MSID[2:0] = Market Segment ID • VID[5:3] / CSC [2:0] = Current Sense Configuration • VID[6] = Reserved • VID[7] = VR11.1 Select Pull-up and pull-down resistors on the baseboard eliminate the need for timing specifications.
Features Figure 8-2. Power States C0 MWAIT C1, HLT 2 2 2 2 MWAIT C1, HLT MWAIT C3, I/O C3 (C1E enabled) 1 1 C3 C1E C1 MWAIT C6, I/O C6 C6 1. No transition to C0 is needed to service a snoop when in C1 or C1E. 2. Transitions back to C0 occur on an interrupt or on access to monitored address (if state was . entered via MWAIT). . 8.2.1 Thread and Core Power State Descriptions Individual threads may request low power states as described below.
Features A System Management Interrupt (SMI) handler will return execution to either Normal state or the C1 state. See the Intel® 64 and IA-32 Architecture Software Developer's Manuals, Volume III: System Programmer's Guide for more information. While in C1/C1E state, the processor will process bus snoops and snoops from the other threads. To operate within specification, BIOS must enable the C1E feature for all installed processors. 8.2.1.
Features 8.2.2.3 Package C3 State The package will enter the C3 low power state when all cores are in the C3 or lower power state and the processor has been granted permission by the other component(s) in the system to enter the C3 state. The package will also enter the C3 state when all cores are in an idle state lower than C3 but other component(s) in the system have only granted permission to enter C3.
Features Table 8-4. Processor S-States S-State Power Reduction Allowed Transitions S0 Normal Code Execution S1 (via PMReq) S1 Cores in C1E like state, processor responds with CmpD(S1) message. S0 (via reset or PMReq) S3, S4 (via PMReq) S3 Memory put into self-refresh, processor responds with CmpD(S3) message. S0 (via reset) S4/S5 Processor responds with CmpD(S4/S5) message. S0 (via reset) Notes: 1.
Boxed Processor Specifications 9 Boxed Processor Specifications 9.1 Introduction Intel boxed processors are intended for system integrators who build systems from components available through distribution channels. The Intel® Xeon® processor 5600 series will be offered as an Intel boxed processor, however the thermal solution will be sold separately. Intel Xeon processor 5600 series boxed processors will not include a thermal solution in the box.
Boxed Processor Specifications Figure 9-1. STS100C Passive / Active Combination Heat Sink (with Removable Fan) Figure 9-2. STS100C Passive / Active Combination Heat Sink (with Fan Removed) 9.1.3 Intel Thermal Solution STS100A (Active Heat Sink Solution) The STS100A will be available for purchase for processors with TDP’s of 80W and lower and is an aluminum extrusion. This heat sink solution is intended to be used as an active heat sink only for pedestal chassis.
Boxed Processor Specifications Figure 9-3. STS100A Active Heat Sink 9.1.4 Intel Thermal Solution STS100P (Boxed 25.5 mm Tall Passive Heat Sink Solution) The STS100P is available for use with boxed processors that have TDP’s of 95W and lower. The 25.5 mm Tall passive solution is designed to be used in SSI Blades, 1U, and 2U chassis where ducting is present. The use of a 25.5 mm Tall heatsink in a 2U chassis is recommended to achieve a lower heatsink TLA and a more optimized heatsink design.
Boxed Processor Specifications 9.2.1 Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones The boxed processor and boxed thermal solutions will be sold separately. Clearance is required around the thermal solution to ensure unimpeded airflow for proper cooling. Baseboard keepout zones are shown in Figure 9-5 through Figure 9-7. Physical space requirements and dimensions for the boxed processor and assembled heat sink are shown in Figure 9-8 and Figure 9-9.
Intel® Xeon® Processor 5600 Series Datasheet Volume 1 A B C D 8 7 6 8 BALL 1 POSITION 4 LINE REPRESENTS OF OUTERMOST ROWS AND COLUMNS OF SOCKET BALL ARRAY OUTLINE. FOR REFERENCE ONLY SOCKET BODY OUTLINE FOR REFERENCE ONLY 7 6 AS VIEWED FROM PRIMARY SIDE OF THE MOTHERBOARD 36.00 [1.417 ] SOCKET ILM HOLE PATTERN 41.66 [1.640 ] CENTERLINE OF OUTER SOCKET BALL ARRAY 47.50 [1.870 ] SOCKET BODY OUTLINE, FOR REFERENCE ONLY 80.00 [3.150 ] THERMAL RETENTION HOLE PATTERN 90.00 [3.
A B C D 8 7 6 8 5.00 [ 0.197 ] 85.00 [ 3.346 ] 3X 80.00 [ 3.150 ] 77.90 [ 3.067 ] 2X 72.50 [ 2.854 ] 2X 70.600 [ 2.7795 ] 62.39 [ 2.456 ] BALL 1 4 49.40 [ 1.945 ] 30.600 [ 1.205 ] 29.90 [ 1.177 ] 9.900 [ 0.3898 ] 2X 9.400 [ 0.3701 ] 2X 7.50 [ 0.295 ] 2X 0.00 [0.000] 3.30 [ 0.130 ] 7 58.000 [ 2.2835 ] 47.15 [ 1.856 ] 32.85 [ 1.293 ] 19.17 [ 0.755 ] BALL 1 4 22.000 [ 0.8661 ] 9.60 [ 0.378 ] 12.30 [ 0.484 ] 6 AS VIEWED FROM PRIMARY SIDE OF THE MOTHERBOARD (DETAILS) 67.70 [ 2.
Intel® Xeon® Processor 5600 Series Datasheet Volume 1 A B C D 8 7 6 8 (90.00 ) [3.543 ] 8X 7 6.00 [ 0.236 ] (72.20 ) [2.843 ] DESKTOP BACKPLATE KEEPIN SHOWN FOR REFERENCE ONLY 6 9.50 [ 0.374 ] 32.85 [ 1.293 ] 47.15 [ 1.856 ] 70.50 [ 2.776 ] 5 AS VIEWED FROM SECONDARY SIDE OF THE MOTHERBOARD (DETAILS) (90.00 ) [3.543 ] (47.00 ) [1.850 ] 5 85.00 [ 3.346 ] 4 4 0.00 [0.000] 85.00 [ 3.346 ] 75.00 [ 2.953 ] 62.83 [ 2.474 ] 49.40 [ 1.945 ] 30.60 [ 1.205 ] 17.17 [ 0.676 ] 5.
7 6 7 4 R REMOVED 3.0 MM HEIGHT RESTRICTION ZONE TO THE LEFT AND RIGHT OF SOCKET OUTLINE MOVED REVISION HISTORY TABLE TO SHEET 4 CORRECTED SOCKET SOLDERBALL ARRAY & POS 41.66 --> 40.64 (ARRAY SIZE) 44.85 --> 44.70 (ARRAY SIZE) 62.43 --> 62.39 (ARRAY POSITION) 19.17 --> 19.67 (ARRAY POSITION) ADDED TOPSIDE CU PAD CALLOUT FOR ILM HOLES SEE DETAIL A, SHEET 2 REVERTED SOCKET SOLDERBALL ARRAY X DIRECTION SIZE AND POSITION TO REV G. 40.64 --> 41.66 (ARRAY WIDTH) 19.67 --> 19.
Boxed Processor Specifications Figure 9-9.
Boxed Processor Specifications Figure 9-10.
Boxed Processor Specifications Figure 9-11.
Boxed Processor Specifications Figure 9-12.
Boxed Processor Specifications 9.2.2 Boxed Processor Retention Mechanism and Heat Sink Support (URS) Baseboards designed for use by a system integrator should include holes that are in proper alignment with each other to support the boxed processor. Refer to Figure 9-5 and Figure 9-5 for mounting hole dimensions. Figure 9-13 illustrates the Unified Retention System (URS) and the Unified Backplate Assembly.
Boxed Processor Specifications Figure 9-13. Thermal Solution Installation Note: Actual boxed thermal solution may differ from this image, but installation is similar. 9.3 Fan Power Supply [STS100C (Combo) and STS100A (Active) Solutions] The 4-pin PWM controlled thermal solution is being offered to help provide better control over pedestal chassis acoustics. This is achieved though more accurate measurement of processor die temperature through the processor’s Digital Thermal Sensors.
Boxed Processor Specifications solution and does not support variable voltage control or 3-pin PWM control. See Figure 9-14 and Table 9-1 through Table 9-3 for details on the 4-pin active heat sink solution connectors. The fan power header on the baseboard must be positioned to allow the fan heat sink power cable to reach it. The fan power header identification and location must be documented in the suppliers platform documentation, or on the baseboard itself.
Boxed Processor Specifications 9.3.1.1 STS100C (Passive / Active Combination Heat Sink Solution) Active Configuration: The active configuration of the combination solution is designed to help pedestal chassis users to meet the thermal processor requirements without the use of chassis ducting. It may be still be necessary to implement some form of chassis air guide or air duct to meet the TLA temperature of 40 C depending on the pedestal chassis layout.
Boxed Processor Specifications Processors with a TDP of 80 W or lower must provide a minimum airflow of 9.7 CFM at 0.20 in. H2O (16.5 m3/hr at 49.8 Pa) of flow impedance. It is assumed that a TLA of 49°C is met for these processor installations. This requires a chassis design to limit the TRISE at or below 14°C with an external ambient temperature of 35°C.
Boxed Processor Specifications 186 Intel® Xeon® Processor 5600 Series Datasheet Volume 1
