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Low Voltage Intel

Xeon

™

Processor at

1.60 GHz, 2.0 GHz and 2.4 GHz

Datasheet

Product Features

The Low Voltage Intel

Xeon™ processor at 1.6 Ghz and 2.0 Ghz with 400 Mhz system bus and

2.4 Ghz with 533 Mhz system bus are designed for high-performance dual and single processor

applications. Based on the Intel

NetBurst™ micro-architecture and the new Hyper-Threading

Technology, it is binary compatible with previous Intel Architecture (IA-32) processors. The

Low Voltage Intel Xeon processor is scalable to two processors in a multiprocessor system

providing exceptional performance for applications running on advanced operating systems such

as Windows XP*, Windows* 2000, Linux*, and UNIX*. The Low Voltage Intel Xeon processor

delivers compute power at unparalleled value and flexibility for embedded applications. The

Intel

NetBurst™ micro-architecture and Hyper-Threading Technology deliver outstanding

performance and headroom for embedded applications, resulting in faster response times,

support for more users, and improved scalability.

■ Available at 1.60 GHz, 2.0 GHz and 2.4 GHz

■ Dual-/Uni- processing support

■ Binary compatible with applications running on

previous members of Intel’s IA32

microprocessor line

■ Intel

NetBurst™ micro-architecture

■ Hyper-Threading Technology

—Hardware support for multithreaded

applications

■ 400 MHz System bus (1.6 Ghz and 2.0 Ghz)

—Bandwidth up to 3.2 GBytes/second

■ 533 MHz System bus (2.4 Ghz)

—Bandwidth up to 4.3 GBytes/second

■ Rapid Execution Engine: Arithmetic Logic

Units (ALUs) run at twice the processor core

frequency

■ Hyper Pipelined Technology

■ Advance Dynamic Execution

—Very deep out-of-order execution

—Enhanced branch prediction

■ Level 1 Execution Trace Cache stores 12 K

micro-ops and removes decoder latency from

main execution loops

■ Level 1 of 8 Kbytes data cache

■ 512 KB Advanced Transfer L2 Cache (on-die,

full speed Level 2 cache) with 8-way

associativity and Error Correcting Code (ECC)

■ Enables system support of up to 64 Gbytes of

physical memory

■ Streaming SIMD Extensions 2 (SSE2)

— 144 new instructions for double-precision

floating point operations, media/video

streaming, and secure transactions

■ Enhanced floating point and multimedia unit for

enhanced video, audio, encryption, and 3D

performance

■ Power Management capabilities

— System Management mode

— Multiple low-power states

■ Advanced System Management Features

— Thermal Monitor

— Machine Check Architecture (MCA)

Order Number: 273766-005

September 2003

Summary of content (102 pages)

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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Datasheet Product Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Available at 1.60 GHz, 2.0 GHz and 2.4 GHz Dual-/Uni- processing support Binary compatible with applications running on previous members of Intel’s IA32 microprocessor line Intel® NetBurst™ micro-architecture Hyper-Threading Technology — Hardware support for multithreaded applications 400 MHz System bus (1.6 Ghz and 2.0 Ghz) — Bandwidth up to 3.2 GBytes/second 533 MHz System bus (2.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Contents Contents 1.0 Introduction....................................................................................................................................9 1.1 1.2 1.3 2.0 Electrical Specifications ............................................................................................................. 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 3.0 System Bus and GTLREF ............................
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Contents 4.5 4.6 4.7 5.0 Materials ............................................................................................................................. 57 Markings ............................................................................................................................. 58 Processor Pin-Out Diagram................................................................................................
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Contents 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform........................... 37 THERMTRIP# to VCC Timing .................................................................................................... 37 Example 3.3 VDC/VID_VCC Sequencing...................................................................................
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Contents 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 6 Miscellaneous Signals+ AC Specifications................................................................................. 30 System Bus AC Specifications (Reset Conditions) .................................................................... 31 TAP Signal Group AC Specifications ...........................................................................
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Contents Revision History Date Revision Description September 2003 005 • Updated Figure 3, Low Voltage and Current Projections in a Dual-Processor Configuration. • Added Vcc and Icc voltage and current specificaitons for 2.4 GHz. • Added system bus to core frequency ratio specifications for 2.4 GHz. September 2003 004 • Added processor thermal design power specifications for 2.4 GHz.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 1.0 Introduction The Low Voltage Intel® Xeon™ processor is based on the Intel® NetBurst™ micro-architecture, which operates at significantly higher clock speeds and delivers performance levels that are significantly higher than previous generations of IA-32 processors. While based on the Intel NetBurst micro-architecture, it maintains the tradition of compatibility with IA-32 software.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz compatible with the Pentium Pro processor system bus. The system bus uses Source-Synchronous Transfer (SST) of address and data to improve performance, and transfers data four times per bus clock (4X data transfer rate). Along with the 4X data bus, the address bus may deliver addresses two times per bus clock and is referred to as a ‘double-clocked’ or 2X address bus. In addition, the Request Phase completes in one clock cycle.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz • OEM - Original Equipment Manufacturer. • Processor core - The processor’s execution engine. All AC timing and signal integrity specifications are to the pads of the processor core. • Retention mechanism - The support components that are mounted through the baseboard to the chassis to provide mechanical retention for the processor and heatsink assembly. 1.2 State of Data The data contained in this document is subject to change.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Document Intel Order Number1 Low Voltage Intel® Xeon™ Processor Signal Integrity Models2 Intel® Xeon™ Processor with 512 KB L2 Cache Mechanical Models in ProE* Format http://developer.intel.com Intel® Xeon™ Processor with 512 KB L2 Cache Mechanical Models in IGES* Format http://developer.intel.com Intel® Xeon™ Processor with 512 KB L2 Cache Core Boundary Scan Descriptor Language (BSDL) Model http://developer.intel.com NOTES: 1.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 2.0 Electrical Specifications 2.1 System Bus and GTLREF Most Low Voltage Intel® Xeon™ processor system bus signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. The processor termination voltage level is VCC, the operating voltage of the processor core.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 2.3.1 VCC Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and the baseboard designer must ensure a low interconnect resistance from the regulator (or VRM pins) to the 604-pin socket. Bulk decoupling may be provided on the voltage regulation module (VRM) to meet help meet the large current swing requirements. The remaining decoupling is provided on the baseboard.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 2.4.1 Bus Clock The system bus frequency is set to the maximum supported by the individual processor. BSEL[1:0] are outputs used to select the system bus frequency. Table 3 defines the possible combinations of the signals and the frequency associated with each combination. The frequency is determined by the processor(s), chipset, and clock synthesizer. All system bus agents must operate at the same frequency.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 1. Typical VCCIOPLL, VCCA and VSSA Power Distribution Trace < 0.02 Ω VCC Processor interposer "pin" L1/L2 R-Socket R-Trace VCCA PLL C Baseboard via that connects filter to VCC plane Socket pin R-Socket Processor VSSA C R-Socket R-Trace VCCIOPLL L1/L2 Figure 2. Phase Lock Loop (PLL) Filter Requirements 0.2 dB 0 dB -0.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 2.5.1 Mixing Processors Intel only supports those processor combinations operating with the same system bus frequency, core frequency, VID settings, and cache sizes. Not all operating systems may support multiple processors with mixed frequencies. Intel does not support or validate operation of processors with different cache sizes.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 4. Voltage Identification Definition Processor Pins 2.6.1 VID4 VID3 VID2 VID1 VID0 VCC_VID (V) 1 1 1 1 1 VRM output off 1 1 1 1 0 1.100 1 1 1 0 1 1.125 1 1 1 0 0 1.150 1 1 0 1 1 1.175 1 1 0 1 0 1.200 1 1 0 0 1 1.225 1 1 0 0 0 1.250 1 0 1 1 1 1.275 1 0 1 1 0 1.300 1 0 1 0 1 1.325 1 0 1 0 0 1.350 1 0 0 1 1 1.375 1 0 0 1 0 1.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 2.7 Reserved Or Unused Pins All Reserved pins must remain unconnected on the system baseboard. Connection of these pins to VCC, V SS, or to any other signal (including one another) may result in component malfunction or incompatibility with future processors. See Chapter 5.0 for a pin listing of the processor and for the location of all Reserved pins.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz rising edge of BCLK0. Asynchronous signals are still present (A20M#, IGNNE#, etc.) and may become active at any time during the clock cycle. Table 5 identifies which signals are common clock, source synchronous and asynchronous. Table 5.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 2.9 Asynchronous GTL+ Signals The Low Voltage Intel® Xeon™ processor does not utilize CMOS voltage levels on any signals that connect to the processor silicon. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output FERR#/PBE# and other non-AGTL+ signals IERR#, and THERMTRIP# utilize GTL+ output buffers. PROCHOT# uses GTL+ input/output buffer.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 2.11 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Section 5.1 for the processor pin listings and Section 5.2 for the signal definitions. The voltage and current specifications for all versions of the processor are detailed in Table 7. For platform planning refer to Figure 3.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 7. Voltage and Current Specifications Symbol VCC Parameter VCC for Low Voltage Intel Xeon processor core in a dual-processor configuration. VID_VCC VID supply voltage ICC ICC for Low Voltage Intel Xeon processor core in a dual-processor configuration. Core Freq Min 1.60 GHz 1.187 2.0 GHz 1.179 2.4 GHz 1.170 All freq 3.135 Typ Max 1.270 3.3 3.465 30.4 35.7 2.4 GHz 40.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 3. Low Voltage Intel® Xeon™ Processor Voltage and Current Projections in a Dual-Processor Configuration Vccmax Maximum Processor Voltage (VDC) 1.31 1.3 1.29 1.28 1.27 1.26 1.25 1.24 0 5 10 15 20 25 30 35 40 Processor Current (A) Table 8. System Bus Differential BCLK Specifications (Sheet 1 of 2) Notes 1 Symbol Parameter Min Typ Max Unit Figure VL Input Low Voltage -.150 0.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 8. System Bus Differential BCLK Specifications (Sheet 2 of 2) VRBM Ringback Margin 0.200 N/A N/A V 6 6 VTM Threshold Margin VCROSS - 0.100 N/A VCROSS + 0.100 V 6 7 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. 3.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 10. TAP and PWRGOOD Signal Group DC Specifications Symbol Min Max VHYS TAP Input Hysteresis 200 300 7 VT+ TAP input low to high threshold voltage 0.5 * (VCC + VHYS_MIN) 0.5 * (VCC + VHYS_MAX) 4 VT- TAP input high to low threshold voltage 0.5 * (VCC - VHYS_MAX) 0.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 2.12 AGTL+ System Bus Specifications Routing topologies are dependent on the number of processors supported and the chipset used in the design. Please refer to the appropriate platform design guidelines. In most cases, termination resistors are not required as these are integrated into the processor. See Table 5 for details on which AGTL+ signals do not include on-die termination.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz All AGTL+ timings are referenced to GTLREF for both 0 and 1 logic levels unless otherwise specified. The timings specified in this section should be used in conjunction with the signal integrity models provided by Intel. These signal integrity models, which include package information, are available for the Intel® Xeon™ processor in IBIS format. AGTL+ layout guidelines are also available in the appropriate platform design guidelines.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz . Table 14. System Bus Common Clock AC Specifications T# Parameter Unit Figure Notes1, 2 1.27 ns 8 3 N/A ns 8 4 0.40 N/A ns 8 4 1.00 10.00 ms 11 5, 6, 7 Min Max T10: Common Clock Output Valid Delay 0.12 T11: Common Clock Input Setup Time 0.65 T12: Common Clock Input Hold Time T13: RESET# Pulse Width NOTES: 1. Not 100% tested. Specified by design characterization. 2.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 15. System Bus Source Synchronous AC Specifications (Sheet 2 of 2) T# Parameter Min Max Unit Figure Notes T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay (400 MHz) 8.80 10.20 ns 10 1, 2, 3, 4, 12 T30: Data Strobe ‘n’ (DSTBN#) Output Valid Delay (533 MHz) 6.47 8.00 ns 10 1, 2, 3, 4, 12 T31: Address Strobe Output Valid Delay (400 MHz) 2.27 4.23 ns 9 1, 2, 3 T31: Address Strobe Output Valid Delay (533 MHz) 1.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 17. System Bus AC Specifications (Reset Conditions) T# Parameter Min T45: Reset Configuration Signals (A[31:3]#, BR0#, INIT#, SMI#) Setup Time 4 T46: Reset Configuration Signals (A[31:3]#, INIT#, SMI#) Hold Time 2 T47: Reset Configuration Signal BR0# Hold Time 2 Max Unit Figure Notes BCLKs 11 1 20 BCLKs 11 2 2 BCLKs 11 2 NOTES: 1. Before the de-assertion of RESET# 2. After the clock that de-asserts RESET# ..
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz falling edge of their associated data strobe. Source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. All source synchronous AGTL+ signal timings are referenced at GTLREF at the processor core (pads). 3. All AC timings for AGTL+ strobe signals are referenced to BCLK[1:0] at V CROSS. All AGTL+ strobe signal timings are referenced at GTLREF at the processor core (pads). 4.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 6.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 8. System Bus Common Clock Valid Delay Timing Waveform T0 T1 T2 BCLK1 BCLK0 TP Common Clock Signal (@ driver) valid valid TQ TR Common Clock Signal (@ receiver) valid TP = T10: Common Clock Output Valid Delay TQ = T11: Common Clock Input Setup TR = T12: Common Clock Input Hold Time Figure 9.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 10. System Bus Source Synchronous 4X (Data) Timing Waveform T0 1/4 BCLK 1/2 BCLK T1 3/4 BCLK T2 BCLK1 BCLK0 DSTBp# (@ driver) TH DSTBn# (@ driver) TA TB TA TD D# (@ driver) DSTBp# (@ receiver) TJ DSTBn# (@ receiver) TC D# (@ receiver) TE TG TE TG TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T27: Source Sync.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 11. System Bus Reset and Configuration Timing Waveform BCLK Tt Reset Ty Tv Tx Tw Configuration A[31:3], SM#, INIT# Valid Configuration BR0# Valid Notes: Tv = T13 (RESET# Pulse Width) Tw = T45 (Reset Configuration Signals Setup Time) Tx = T46 (Reset Configuration Signals A[31:3], SM#, and INIT# Hold Time Ty = T47 (Reset Configuration BR0# Hold Time) B2276-01 Figure 12.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 13. TAP Valid Delay Timing Waveform V TCK Tx Ts Th Signal V Valid Tx = T63 (Valid Time) Ts = T61 (Setup Time) Th = T62 (Hold Time) V = 0.5 * Vcc Figure 14. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform V Tq T = T64 (TRST# Pulse Width), V=0.5*Vcc q T38 (PROCHOT# Pulse Width), V=GTLREF Figure 15. THERMTRIP# to VCC Timing THERMTRIP# Power Down Sequence T39 THERMTRIP# V cc T39 < 0.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 16. Example 3.3 VDC/VID_VCC Sequencing T0=95% 3.3 volt level Power Up 3.3 VDC/VID_VCC PWR_OK / OUTEN > T0 + 100ms VID_OUT T0 + 10mS VRM PWRGD > 10ms Processor PWRGOOD Processor RESET 1ms
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 3.0 System Bus Signal Quality Specifications This section documents signal quality metrics used to derive topology and routing guidelines through simulation. All specifications are made at the processor core (pad measurements). Source synchronous data transfer requires the clean reception of data signals and their associated strobes.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 17. BCLK[1:0] Signal Integrity Waveform Overshoot VH BCLK1 Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot 3.2 System Bus Signal Quality Specifications and Measurement Guidelines Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are available in the appropriate platform design guidelines.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 21. Ringback Specifications for TAP Buffers Signal Group Transition Maximum Ringback (with Input Diodes Present) Threshold Unit Figure Notes TAP and PWRGOOD L→H VT+(max) TO VT-(max) VT+(max) V 20 1, 2, 3, 4 TAP and PWRGOOD H→L VT-(min) TO VT+(min) VT-(min) V 21 1, 2, 3, 4 NOTES: 1. All signal integrity specifications are measured at the processor core (pads). 2. Specifications are for the edge rate of 0.3 - 4.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 20. Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers Vcc Threshold Region to switch receiver to a logic 1. Vt+ (max) Vt+ (min) 0.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 21. High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffer Vcc Allowable Ringback Vt+ (min) 0.5 * Vcc Vt- (max) Vt- (min) Threshold Region to switch receiver to a logic 0. Vss 3.3 System Bus Signal Quality Specifications and Measurement Guidelines 3.3.1 Overshoot/Undershoot Guidelines Overshoot (or undershoot) is the absolute value of the maximum voltage above or below VSS.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz ensure that ESD models do not clamp extreme voltage levels. Intel’s signal integrity models also contain I/O capacitance characterization. Therefore, removing the ESD diodes from a signal integrity model may impact results and may yield excessive overshoot/undershoot. 3.3.2 Overshoot/Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level (VSS).
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Note: The following three notes apply to the activity factor. 1. Activity factor for common clock AGTL+ signals is referenced to BCLK[1:0] frequency. 2. Activity factor for source synchronous (2x) signals is referenced to ADSTB[1:0]#. 3. Activity factor for source synchronous (4x) signals is referenced to DSTBP[3:0]#and DSTBN[3:0]#. 3.3.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz The following notes apply to Table 22 through Table 25: • Absolute Maximum Overshoot magnitude of 1.8 V must never be exceeded. • Absolute Maximum Overshoot is measured referenced to VSS, Pulse Duration of overshoot is measured relative to VCC. • Absolute Maximum Undershoot and Pulse Duration of undershoot is measured relative to VSS. • • • • Ringback below VCC cannot be subtracted from overshoots/undershoots.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 23. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 1.45 -0.15 10.00 10.00 10.00 1.40 -0.10 10.00 10.00 10.00 1.35 -0.05 10.00 10.00 10.00 NOTES: 1. These specifications are measured at the processor pad. 2.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 25. 400 MHz Asynchronous GTL+, PWRGOOD, and TAP Signal Groups Overshoot/Undershoot Tolerance (Sheet 2 of 2) Absolute Maximum Overshoot (V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF = 1 Pulse Duration (ns) AF = 0.1 Pulse Duration (ns) AF = 0.01 1.45 -0.15 60.00 60.00 60.00 1.40 -0.10 60.00 60.00 60.00 1.35 -0.05 60.00 60.00 60.00 NOTES: 1. These specifications are measured at the processor pad. 2.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 27. Source Synchronous (533 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance (Continued) (Sheet 2 of 2) Absolute Maximum Overshoot(V) Absolute Maximum Undershoot (V) Pulse Duration (ns) AF=1 Pulse Duration (ns) AF-0.1 Pulse Duration (ns) AF=0.01 1.400 -0.100 7.50 7.50 7.50 1.350 -0.050 7.50 7.50 7.50 NOTES: 1. These specifications are measured at the processor pad. 2. Assumes a BCLK period of 10 ns. 3.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 22.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 4.0 Mechanical Specifications The Low Voltage Intel® Xeon™ processor uses the Flip Chip Micro-Pin Grid Array (FC-µPGA2) package technology. This includes an integrated heat spreader (IHS) mounted to a pinned substrate. Mechanical specifications for the processor are given in this section. See Section 1.1 for terminology definitions. Figure 23 provides a basic assembly drawing and includes the components which make up the entire processor.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 4.1 Mechanical Specifications Figure 24.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 25.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 30. Dimensions for the Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package Symbol A B E F G H J K L M N R T φP Pin Tp Milimeters Nominal 42.50 31.00 3.60 2.03 19.05 38.10 6.35 12.70 14.99 15.24 30.23 30.48 6.35 1.27 12.70 0.26 0.31 Min 42.40 30.90 3.42 1.95 18.80 37.85 Notes Max 42.60 31.10 3.78 2.11 19.30 38.35 Nominal Component Keepin Nominal Component Keepin 15.49 30.73 Nominal Component Keepin Nominal 0.36 0.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 27. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Cross Section View, Pin Side Component Keep-In Figure 28. Low Voltage Intel® Xeon™ Processor in the FC-µPGA2 Package: Pin Detail 0.65 MAX R0.065 MAX R0.0254 MIN ⊄0.65 MAX ⊄0.37 MAX 1.032 MAX 0.3 MAX 2.03±0.08 Figure 29 details the flatness and tilt specifications for the IHS of the Low Voltage Intel Xeon processor, respectively.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 29. Low Voltage Intel® Xeon™ Processor FC-µPGA2 Package: IHS Flatness and Tilt Drawing 0.080 4.2 Processor Package Load Specifications Table 31 provides dynamic and static load specifications for the processor IHS. These mechanical load limits should not be exceeded during heat sink assembly, mechanical stress testing, or standard drop and shipping conditions.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 4.3 Insertion Specifications The processor may be inserted and removed 15 times from a 604-pin socket meeting the 604-Pin Socket Design Guidelines document. Note that this specification is based on design characterization and is not tested. 4.4 Mass Specifications Table 32 specifies the processors mass. This includes all components which make up the entire processor product. Table 32.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 4.6 Markings The following section details the processor top-side laser markings. It is provided to aid in the identification of the processor. Figure 30. Processor Top-Side Markings IN T E L C O N F ID E N T IA L i m c ‘0 0 {A T P O } NOTES: 1. Character size for laser markings is: height 0.050" (1.27mm), width 0.032" (0.81mm). 2. All characters are in upper case. 80528KC1.5G1M QXXXES {COO} {FPO}-[{SN} } Figure 31.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 32.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 33.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 5.0 Pin Listing and Signal Definitions 5.1 Processor Pin Assignments Section 2.8 contains the system bus signal groups in Table 5 for the Low Voltage Intel® Xeon™ processor. This section provides a sorted pin list in Table 34 and Table 35. Table 34 is a listing of all processor pins ordered alphabetically by pin name. Table 35 is a listing of all processor pins ordered by pin number. 5.1.1 Pin Listing by Pin Name Table 34.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 34. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Direction BPM4# E8 Common Clk Input/Output BPM5# E4 Common Clk Input/Output BPRI# D23 Common Clk Input D20 Common Clk Input/Output BR0# 62 Table 34. Pin Listing by Pin Name Pin Name Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 34. Pin Listing by Pin Name Table 34. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 34. Pin Listing by Pin Name Table 34. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 34. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VCC G2 VCC VCC Table 34. Pin Listing by Pin Name Pin Name Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 34. Pin Listing by Pin Name 66 Pin Name Pin No. Signal Buffer Type VCC R5 VCC VCC Table 34. Pin Listing by Pin Name Pin Name Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 34. Pin Listing by Pin Name Table 34. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type Direction Pin Name Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 34. Pin Listing by Pin Name 68 Pin Name Pin No. Signal Buffer Type VSS J25 VSS VSS Table 34. Pin Listing by Pin Name Pin Name Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 34. Pin Listing by Pin Name Pin Name Pin No. Signal Buffer Type VSS V1 VSS VSS Table 34. Pin Listing by Pin Name Pin Name Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 5.1.2 Pin Listing by Pin Number Table 35. Pin Listing by Pin Number Table 35. Pin Listing by Pin Number Pin No. 70 Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 35. Pin Listing by Pin Number Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 35. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type Direction Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 35. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type Direction Table 35. Pin Listing by Pin Number Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 35. Pin Listing by Pin Number Pin Name Signal Buffer Type M2 VSS M3 VCC M4 VSS M5 M6 Pin No. 74 Direction Table 35. Pin Listing by Pin Number Signal Buffer Type Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 35. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type T6 VCC T7 VSS T8 VCC Table 35. Pin Listing by Pin Number Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 35. Pin Listing by Pin Number Pin No. Pin Name Signal Buffer Type Direction Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 35. Pin Listing by Pin Number Table 35. Pin Listing by Pin Number Pin Name Signal Buffer Type Direction Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 35. Pin Listing by Pin Number Pin No.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 5.2 Signal Definitions Table 36. Signal Definitions (Sheet 1 of 9) Name Type Description 36 I/O A[35:3]# (Address) define a 2 byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the system bus.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 36. Signal Definitions (Sheet 2 of 9) Name BINIT# BNR# BPM[5:0]# BPRI# 80 Type Description I/O BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and when used, must connect the appropriate pins of all such agents. When the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future information.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 36. Signal Definitions (Sheet 3 of 9) Name Type Description BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The BREQ[3:0]# signals are interconnected in a rotating manner to individual processor pins. BR2# and BR3# must not be utilized in a dual processor platform design. The table below gives the rotating interconnect between the processor and bus signals for dual processor systems.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 36. Signal Definitions (Sheet 4 of 9) Name Type Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 36. Signal Definitions (Sheet 5 of 9) Name Type Description FERR#/PBE# O FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/ PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 36. Signal Definitions (Sheet 6 of 9) Name LINT[1:0] LOCK# MCERR# Mechanical Key ODTEN PROCHOT# 84 Type Description I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all system bus agents. When the APIC functionality is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 36. Signal Definitions (Sheet 7 of 9) Name Type Description I PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 36. Signal Definitions (Sheet 8 of 9) Name Type Description I SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Table 36. Signal Definitions (Sheet 9 of 9) Name Type Description TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. I TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents. TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 6.0 Thermal Specifications This chapter provides the thermal specifications necessary for designing a thermal solution for the Low Voltage Intel® Xeon™ processor. Thermal solutions should include heatsinks that apply pressure to the integrated low voltage heat spreader (IHS). The IHS provides a common interface intended to be compatible with many heatsink designs.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Thermal Design Power (TDP) value listed per frequency in Table 37. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more details on thermal solution design, please refer to the appropriate processor thermal design guidelines. The case temperature is defined at the geometric top center of the processor IHS.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz Figure 35. Thermal Measurement Point for Processor TCASE NOTES: 1. Measure from edge of processor substrate. 2. Figure is not to scale and is for reference only.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 7.0 Features 7.1 Power-On Configuration Options The Low Voltage Intel® Xeon™ processor has several configuration options that are determined by the state of specific processor pins at the active-to-inactive transition of the processor RESET# signal. These configuration options cannot be changed except by another reset. Both power on and software induced resets reconfigure the processor(s). Table 38.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz The return from a System Management Interrupt (SMI) handler may be to either Normal Mode or the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system may generate a STPCLK# while the processor is in the AutoHALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor may return execution to the HALT state. Figure 36.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz BINIT# may be recognized while the processor is in Stop-Grant state. When STPCLK# is still asserted at the completion of the BINIT# bus initialization, the processor may remain in Stop-Grant mode. When STPCLK# is not asserted at the completion of the BINIT# bus initialization, the processor may return to Normal state. RESET# may cause the processor to immediately initialize itself, but the processor may stay in Stop-Grant state.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 7.2.6 Bus Response During Low Power States While in AutoHALT Power Down and Stop-Grant states, the processor may process a system bus snoop. When the processor is in Sleep state, the processor may not process interrupts or snoop transactions. 7.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 7.4 Thermal Diode The Low Voltage Intel Xeon processor incorporates an on-die thermal diode. A thermal sensor located on the baseboard may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. Table 39 and Table 40 provide the diode parameter and interface specifications.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 8.0 Debug Tools Specifications The Debug Port design information has been moved. This includes all information necessary to develop a Debug Port on this platform, including electrical specifications, mechanical requirements, and all In-Target Probe (ITP) signal layout guidelines. Please reference the ITP700 Debug Port Design Guide for the design of your platform. 8.
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Low Voltage Intel® Xeon™ Processor at 1.60 GHz, 2.0 GHz and 2.4 GHz 9.0 Appendix A 9.1 Processor Core Frequency Determination To allow system debug and multiprocessor configuration flexibility, the core frequency of the processor may be configured using an MSR. Clock multiplying within the processor is provided by the internal Phase Lock Loop (PLL), which requires a constant frequency BCLK inputs.
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