PIC16F87X Data Sheet 28/40-Pin 8-Bit CMOS FLASH Microcontrollers 2001 Microchip Technology Inc.
“All rights reserved. Copyright © 2001, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise.
PIC16F87X 28/40-Pin 8-Bit CMOS FLASH Microcontrollers • PIC16F873 • PIC16F874 • PIC16F876 • PIC16F877 Microcontroller Core Features: • High performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two cycle • Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle • Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) Up to 256 x 8 bytes of EEPROM Data Memory • Pinout compatible t
PIC16F87X Pin Diagrams PLCC PIC16F877 PIC16F874 39 38 37 36 35 34 33 32 31 30 9 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT 44 43 42 41 40 39 38 37 36 35 34 QFP 7 8 9 10 11 12 13 14 15 16 17 RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/
PIC16F87X Key Features PICmicro™ Mid-Range Reference Manual (DS33023) PIC16F873 PIC16F874 PIC16F876 PIC16F877 Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz RESETS (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) FLASH Program Memory (14-bit words) 4K 4K 8K 8K Data Memory (bytes) 192 192 368 368 EEPROM Data Memory 128 128 256 256 Interrupts 13 14 13 14 I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C
PIC16F87X Table of Contents 1.0 Device Overview ................................................................................................................................................... 5 2.0 Memory Organization.......................................................................................................................................... 11 3.0 I/O Ports .......................................................................................................................................
PIC16F87X 1.0 DEVICE OVERVIEW There are four devices (PIC16F873, PIC16F874, PIC16F876 and PIC16F877) covered by this data sheet. The PIC16F876/873 devices come in 28-pin packages and the PIC16F877/874 devices come in 40-pin packages. The Parallel Slave Port is not implemented on the 28-pin devices. This document contains device specific information.
PIC16F87X FIGURE 1-2: PIC16F874 AND PIC16F877 BLOCK DIAGRAM Device Program FLASH Data Memory Data EEPROM PIC16F874 4K 192 Bytes 128 Bytes PIC16F877 8K 368 Bytes 256 Bytes 13 Program Memory 14 PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS RAM File Registers 8 Level Stack (13-bit) Program Bus 8 Data Bus Program Counter FLASH RAM Addr(1) PORTB 9 RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD Addr MUX Instruction reg Direct Addr 7 8 Indirect Addr FSR reg
PIC16F87X TABLE 1-1: PIC16F873 AND PIC16F876 PINOUT DESCRIPTION DIP Pin# SOIC Pin# I/O/P Type OSC1/CLKIN 9 9 I OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 1 I/P ST Master Clear (Reset) input or programming voltage input. This pin is an active low RESET to the device.
PIC16F87X TABLE 1-2: PIC16F874 AND PIC16F877 PINOUT DESCRIPTION DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type OSC1/CLKIN 13 14 30 I ST/CMOS(4) OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP 1 2 18 I/P ST Master Clear (Reset) input or programming voltage input.
PIC16F87X TABLE 1-2: PIC16F874 AND PIC16F877 PINOUT DESCRIPTION (CONTINUED) Pin Name DIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1 output.
PIC16F87X NOTES: DS30292C-page 10 2001 Microchip Technology Inc.
PIC16F87X 2.0 MEMORY ORGANIZATION There are three memory blocks in each of the PIC16F87X MCUs. The Program Memory and Data Memory have separate buses so that concurrent access can occur and is detailed in this section. The EEPROM data memory block is detailed in Section 4.0. Additional information on device memory may be found in the PICmicro Mid-Range Reference Manual, (DS33023). FIGURE 2-1: PIC16F877/876 PROGRAM MEMORY MAP AND STACK 2.
PIC16F87X 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. RP1:RP0 Bank 00 0 01 1 10 2 11 3 DS30292C-page 12 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers.
PIC16F87X FIGURE 2-3: PIC16F877/876 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.
PIC16F87X FIGURE 2-4: PIC16F874/873 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.
PIC16F87X 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral features section. The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device.
PIC16F87X TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Value on: POR, BOR Details on page: 0000 0000 27 1111 1111 19 0000 0000 26 0001 1xxx 18 xxxx xxxx 27 --11 1111 29 Bit 0 Bank 1 80h(3) INDF 81h OPTION_REG 82h(3) PCL 83h(3) STATUS 84h(3) FSR 85h TRISA 86h TRISB PORTB Data Direction Register 1111 1111 31 87h TRISC PORTC Data Direction Register 1111 1111 33 88h(4) TRISD PORTD Data Direction R
PIC16F87X TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page: Bank 2 100h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 27 101h TMR0 Timer0 Module Register xxxx xxxx 47 102h(3) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 26 103h(3) STATUS 0001 1xxx 18 104h(3) FSR Indirect Data Memory Address
PIC16F87X 2.2.2.1 STATUS Register The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F87X 2.2.2.2 OPTION_REG Register Note: The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16F87X 2.2.2.3 INTCON Register Note: The INTCON Register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F87X 2.2.2.4 PIE1 Register The PIE1 register contains the individual enable bits for the peripheral interrupts. REGISTER 2-4: Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16F87X 2.2.2.5 PIR1 Register Note: The PIR1 register contains the individual flag bits for the peripheral interrupts.
PIC16F87X 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write operation interrupt.
PIC16F87X 2.2.2.7 PIR2 Register . Note: The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt and the EEPROM write operation interrupt. REGISTER 2-7: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F87X 2.2.2.8 PCON Register Note: The Power Control (PCON) Register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT), and an external MCLR Reset. REGISTER 2-8: BOR is unknown on POR. It must be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred.
PIC16F87X 2.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F87X 2.5 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. EXAMPLE 2-2: Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR.
PIC16F87X NOTES: DS30292C-page 28 2001 Microchip Technology Inc.
PIC16F87X 3.0 I/O PORTS FIGURE 3-1: Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023). 3.1 Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch.
PIC16F87X TABLE 3-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2 bit2 TTL Input/output or analog input. RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF. RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input.
PIC16F87X 3.2 PORTB and the TRISB Register PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).
PIC16F87X TABLE 3-3: Name PORTB FUNCTIONS Bit# Buffer RB0/INT bit0 TTL/ST(1) RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. bit3 TTL Input/output pin or programming pin in LVP mode. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up.
PIC16F87X 3.3 PORTC and the TRISC Register PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 3-5).
PIC16F87X TABLE 3-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes.
PIC16F87X 3.4 FIGURE 3-7: PORTD and TRISD Registers PORTD and TRISD are not implemented on the PIC16F873 or PIC16F876. Data Bus PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configureable as an input or output. WR Port PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
PIC16F87X 3.5 FIGURE 3-8: PORTE and TRISE Register PORTE and TRISE are not implemented on the PIC16F873 or PIC16F876. Data Bus PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6, and RE2/CS/AN7) which are individually configureable as inputs or outputs. These pins have Schmitt Trigger input buffers. PORTE BLOCK DIAGRAM (IN I/O PORT MODE) I/O pin(1) Data Latch D Q WR Port CK TRIS Latch The PORTE pins become the I/O control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set.
PIC16F87X REGISTER 3-1: TRISE REGISTER (ADDRESS 89h) R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — Bit2 Bit1 Bit0 bit 7 bit 0 Parallel Slave Port Status/Control Bits: bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Over
PIC16F87X 3.6 Parallel Slave Port The Parallel Slave Port (PSP) is not implemented on the PIC16F873 or PIC16F876. PORTD operates as an 8-bit wide Parallel Slave Port or microprocessor port, when control bit PSPMODE (TRISE<4>) is set. In Slave mode, it is asynchronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR. The PSP can directly interface to an 8-bit microprocessor data bus.
PIC16F87X FIGURE 3-10: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 3-11: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 3-11: Address REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port Data Latch when written: Port pins when read Value on: POR, BOR Value on all other RESETS 08h PORT
PIC16F87X NOTES: DS30292C-page 40 2001 Microchip Technology Inc.
PIC16F87X 4.0 DATA EEPROM AND FLASH PROGRAM MEMORY The Data EEPROM and FLASH Program Memory are readable and writable during normal operation over the entire VDD range. These operations take place on a single byte for Data EEPROM memory and a single word for Program memory. A write operation causes an erase-then-write operation to take place on the specified byte or word. A bulk erase operation may not be issued from user code (which includes removing code protection).
PIC16F87X Write operations have two control bits, WR and WREN, and two status bits, WRERR and EEIF. The WREN bit is used to enable or disable the write operation. When WREN is clear, the write operation will be disabled. Therefore, the WREN bit must be set before executing a write operation. The WR bit is used to initiate the write operation. It also is automatically cleared at the end of the write operation. The interrupt flag EEIF is used to determine when the memory write completes.
PIC16F87X 4.2 Reading the EEPROM Data Memory Reading EEPROM data memory only requires that the desired address to access be written to the EEADR register and clear the EEPGD bit. After the RD bit is set, data will be available in the EEDATA register on the very next instruction cycle. EEDATA will hold this value until another read operation is initiated or until it is written by firmware. The steps to reading the EEPROM data memory are: 1. 2. 3. 4. Write the address to EEDATA.
PIC16F87X 4.4 Reading the FLASH Program Memory 4.5 Writing to the FLASH Program Memory Reading FLASH program memory is much like that of EEPROM data memory, only two NOP instructions must be inserted after the RD bit is set. These two instruction cycles that the NOP instructions execute, will be used by the microcontroller to read the data out of program memory and insert the value into the EEDATH:EEDATA registers. Data will be available following the second NOP instruction.
PIC16F87X At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set. (EEIF must be cleared by firmware.) Since the microcontroller does not execute instructions during the write cycle, the firmware does not necessarily have to check either EEIF, or WR, to determine if the write had finished.
PIC16F87X 4.9 FLASH Program Memory Write Protection The configuration word contains a bit that write protects the FLASH program memory, called WRT. This bit can only be accessed when programming the PIC16F87X device via ICSP. Once write protection is enabled, only an erase of the entire device will disable it. When enabled, write protection prevents any writes to FLASH program memory. Write protection does not affect program memory reads.
PIC16F87X 5.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment either on every rising, or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5.2.
PIC16F87X 5.2 Using Timer0 with an External Clock Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa. This prescaler is not readable or writable (see Figure 5-1). When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks.
PIC16F87X TABLE 5-1: Address 01h,101h REGISTERS ASSOCIATED WITH TIMER0 Name TMR0 Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 Module’s Register 0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h Bit 6 GIE PEIE T0IE Value on: POR, BOR Value on all other RESETS xxxx xxxx uuuu uuuu INTE RBIE OPTION_REG RBPU INTEDG T0CS T0SE PSA T0IF INTF RBIF 0000 000x 0000 000u PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
PIC16F87X NOTES: DS30292C-page 50 2001 Microchip Technology Inc.
PIC16F87X 6.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
PIC16F87X 6.1 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect, since the internal clock is always in sync. FIGURE 6-1: 6.2 Timer1 Counter Operation Timer1 may operate in either a Synchronous, or an Asynchronous mode, depending on the setting of the TMR1CS bit.
PIC16F87X 6.4 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt-on-overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 6.4.1).
PIC16F87X 6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L) 6.8 Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers. TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 and CCP2 special event triggers. T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected.
PIC16F87X 7.0 TIMER2 MODULE Register 7-1 shows the Timer2 control register. Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device RESET. Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023).
PIC16F87X 7.1 Timer2 Prescaler and Postscaler 7.2 The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device RESET (POR, MCLR Reset, WDT Reset, or BOR) Output of TMR2 The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate shift clock. TMR2 is not cleared when T2CON is written.
PIC16F87X 8.0 CAPTURE/COMPARE/PWM MODULES Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation, with the exception being the operation of the special event trigger. Table 8-1 and Table 8-2 show the resources and interactions of the CCP module(s).
PIC16F87X REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1Dh) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as '0' bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
PIC16F87X 8.1 8.1.2 Capture Mode TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: Timer1 must be running in Timer mode, or Synchronized Counter mode, for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. • • • • 8.1.
PIC16F87X 8.2 8.2.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • Driven high • Driven low • Remains unchanged Timer1 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 8.2.
PIC16F87X 8.3 8.3.1 PWM Mode (PWM) In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC16F87X 8.3.3 SETUP FOR PWM OPERATION 3. The following steps should be taken when configuring the CCP module for PWM operation: 4. 1. 5. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. TABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 8-4: Address Make the CCP1 pin an output by clearing the TRISC<2> bit.
PIC16F87X TABLE 8-5: Address REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Bh,8Bh, INTCON 10Bh, 18Bh GIE PEIE T0IE INTE RBIE T0IF INTF RBIF PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF Value on: POR, BOR Value on all other RESETS 0000 000x 0000 000u 0Ch PIR1 TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 00
PIC16F87X NOTES: DS30292C-page 64 2001 Microchip Technology Inc.
PIC16F87X 9.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16F87X REGISTER 9-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control e
PIC16F87X REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to SSPBUF was attempted while the I2C conditions were not valid 0 = No collision Slave mode: 1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overfl
PIC16F87X REGISTER 9-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (In I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (In I2C Master mode only) In Master Transmit mode: 1 = Acknowledge was not received from s
PIC16F87X 9.1 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value.
PIC16F87X 9.1.1 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 9-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI module is only going to receive, the SDO output could be disabled (programmed as an input).
PIC16F87X 9.1.2 SLAVE MODE While in SLEEP mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from SLEEP. In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the interrupt flag bit SSPIF (PIR1<3>) is set. Note 1: When the SPI module is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD.
PIC16F87X TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on: MCLR, WDT 0Bh, 8Bh, INTCON 10Bh,18Bh GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u Address 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmi
PIC16F87X 9.2 MSSP I 2C Operation The MSSP module in I2C mode, fully implements all master and slave functions (including general call support) and provides interrupts on START and STOP bits in hardware, to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Refer to Application Note AN578, "Use of the SSP Module in the I 2C Multi-Master Environment.
PIC16F87X 9.2.1 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs. The MSSP module will override the input state with the output data, when required (slavetransmitter). When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register.
PIC16F87X TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received SSPSR → SSPBUF Generate ACK Pulse Set bit SSPIF (SSP Interrupt occurs if enabled) BF SSPOV 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 1 Yes No Yes 0 Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition. 9.2.1.3 An SSP interrupt is generated for each data transfer byte.
PIC16F87X I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) FIGURE 9-7: R/W = 0 Not ACK R/W = 1 Receiving Address SDA A7 SCL A6 1 2 Data in sampled S Transmitting Data ACK A5 A4 A3 A2 A1 3 4 5 6 7 D7 8 9 1 SCL held low while CPU responds to SSPIF D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P SSPIF BF (SSPSTAT<0>) Cleared in software SSPBUF is written in software From SSP Interrupt Service Routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written to
PIC16F87X 9.2.3 SLEEP OPERATION 9.2.4 While in SLEEP mode, the I2C module can receive addresses or data. When an address match or complete byte transfer occurs, wake the processor from SLEEP (if the SSP interrupt is enabled). EFFECTS OF A RESET A RESET disables the SSP module and terminates the current transfer.
PIC16F87X 9.2.5 MASTER MODE Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle, with both the S and P bits clear.
PIC16F87X 9.2.7 I2C MASTER MODE SUPPORT Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit. Once Master mode is enabled, the user has six options: • Assert a START condition on SDA and SCL. • Assert a Repeated START condition on SDA and SCL. • Write to the SSPBUF register initiating transmission of data/address. • Generate a STOP condition on SDA and SCL. • Configure the I2C port to receive data.
PIC16F87X FIGURE 9-11: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL allowed to transition high SCL de-asserted but slave holds SCL low (clock arbitration) SCL BRG decrements (on Q2 and Q4 cycles) BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place, and BRG starts its count BRG Reload 9.2.9 I2C MASTER MODE START CONDITION TIMING Note: To initiate a START condition, the user sets the START condition enable bit, SEN (SSPCON2<0>).
PIC16F87X 9.2.10 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode), or eight bits of data (7-bit mode).
PIC16F87X 9.2.11 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or either half of a 10-bit address, is accomplished by simply writing a value to SSPBUF register. This action will set the Buffer Full flag (BF) and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time spec).
2001 Microchip Technology Inc. S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 9 D7 1 SCL held low while CPU responds to SSPIF After START condition SEN, cleared by hardware.
PIC16F87X 9.2.12 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPCON2<3>). Note: The SSP module must be in an IDLE state before the RCEN bit is set, or the RCEN bit will be disregarded. The baud rate generator begins counting, and on each rollover, the state of the SCL pin changes (high to low/ low to high), and data is shifted into the SSPSR.
2001 Microchip Technology Inc.
PIC16F87X 9.2.13 ACKNOWLEDGE SEQUENCE TIMING rate generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the baud rate generator is turned off, and the SSP module then goes into IDLE mode (Figure 9-16). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit is presented on the SDA pin.
PIC16F87X 9.2.14 STOP CONDITION TIMING while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 9-17). A STOP bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low.
PIC16F87X 9.2.15 CLOCK ARBITRATION 9.2.16 Clock arbitration occurs when the master, during any receive, transmit, or Repeated START/STOP condition, de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC16F87X 9.2.18 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION If a START, Repeated START, STOP, or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition.
PIC16F87X 9.2.18.1 Bus Collision During a START Condition During a START condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the START condition (Figure 9-20). SCL is sampled low before SDA is asserted low (Figure 9-21). During a START condition, both the SDA and the SCL pins are monitored.
PIC16F87X FIGURE 9-21: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable START sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, Bus collision occurs, Set BCLIF SEN SCL = 0 before BRG time-out, Bus collision occurs, Set BCLIF BCLIF Interrupts cleared in software S ’0’ ’0’ SSPIF ’0’ ’0’ FIGURE 9-22: BRG RESET DUE TO SDA COLLISION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA TBRG SDA pulled low by other master.
PIC16F87X 9.2.18.2 Bus Collision During a Repeated START Condition SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs, because no two masters can assert SDA at exactly the same time. During a Repeated START condition, a bus collision occurs if: a) b) If, however, SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs.
PIC16F87X 9.2.18.3 Bus Collision During a STOP Condition The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ’0’.
PIC16F87X 9.3 Connection Considerations for I2C Bus For standard-mode I2C bus devices, the values of resistors Rp and Rs in Figure 9-27 depend on the following parameters: example, with a supply voltage of VDD = 5V±10% and VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 = 1.7 kΩ. VDD as a function of Rp is shown in Figure 9-27. The desired noise margin of 0.1VDD for the low level limits the maximum value of Rs. Series resistors are optional and used to improve ESD susceptibility.
PIC16F87X 10.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.
PIC16F87X REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchr
PIC16F87X 10.1 USART Baud Rate Generator (BRG) It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate.
PIC16F87X TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz BAUD RATE (K) % ERROR KBAUD FOSC = 16 MHz SPBRG value (decimal) % ERROR KBAUD FOSC = 10 MHz SPBRG value (decimal) KBAUD % ERROR SPBRG value (decimal) 0.3 - - - - - - - - - 1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129 2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64 9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15 19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7 28.
PIC16F87X 10.2 USART Asynchronous Mode enabled/disabled by setting/clearing enable bit TXIE ( PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the TSR register is empty.
PIC16F87X When setting up an Asynchronous Transmission, follow these steps: 5. 1. 6. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 10.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. 2. 3. 4. FIGURE 10-2: Enable the transmission by setting bit TXEN, which will also set bit TXIF.
PIC16F87X 10.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 10-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter, operating at x16 times the baud rate; whereas, the main receive serial shifter operates at the bit rate or at FOSC. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is the receive (serial) shift register (RSR).
PIC16F87X FIGURE 10-5: ASYNCHRONOUS RECEPTION START bit bit0 RX (pin) bit1 bit7/8 STOP bit Rcv Shift Reg Rcv Buffer Reg START bit bit0 bit7/8 STOP bit bit7/8 STOP bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG START bit RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. 6.
PIC16F87X 10.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT When setting up an Asynchronous Reception with Address Detect Enabled: • Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. • Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. • If interrupts are desired, then set enable bit RCIE. • Set bit RX9 to enable 9-bit reception. • Set ADDEN to enable address detect. • Enable the reception by setting enable bit CREN.
PIC16F87X FIGURE 10-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT START bit bit0 RC7/RX/DT (pin) bit1 bit8 STOP bit START bit0 bit bit8 STOP bit Load RSR Bit8 = 0, Data Byte Word 1 RCREG Bit8 = 1, Address Byte Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN = 1.
PIC16F87X 10.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively.
PIC16F87X TABLE 10-8: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other RESETS GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000 Name 0Bh, 8Bh, I
PIC16F87X 10.3.2 USART SYNCHRONOUS MASTER RECEPTION receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. Once synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>).
PIC16F87X FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit ’0’ ’0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRG = ’0’. 10.
PIC16F87X 10.4.2 USART SYNCHRONOUS SLAVE RECEPTION 2. 3. 4. 5. The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. Bit SREN is a “don't care” in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP.
PIC16F87X NOTES: DS30292C-page 110 2001 Microchip Technology Inc.
PIC16F87X 11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers. These registers are: • • • • The Analog-to-Digital (A/D) Converter module has five inputs for the 28-pin devices and eight for the other devices. The analog input charges a sample and hold capacitor. The output of the sample and hold capacitor is the input into the converter. The converter then generates a digital result of this analog level via successive approximation.
PIC16F87X REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.
PIC16F87X These steps should be followed for doing an A/D Conversion: 1. 2. 3. 4. Configure the A/D module: • Configure analog pins/voltage reference and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set PEIE bit • Set GIE bit FIGURE 11-1: 5. 6. 7. Wait the required acquisition time.
PIC16F87X 11.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 11-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 11-2.
PIC16F87X 11.2 Selecting the A/D Conversion Clock For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 µs. The A/D conversion time per bit is defined as TAD. The A/D conversion requires a minimum 12TAD per 10-bit conversion. The source of the A/D conversion clock is software selected.
PIC16F87X 11.4 A/D Conversions acquisition is started. After this 2TAD wait, acquisition on the selected channel is automatically started. The GO/DONE bit can then be set to start the conversion. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample.
PIC16F87X 11.5 A/D Operation During SLEEP Turning off the A/D places the A/D module in its lowest current consumption state. The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion.
PIC16F87X NOTES: DS30292C-page 118 2001 Microchip Technology Inc.
PIC16F87X 12.0 SPECIAL FEATURES OF THE CPU All PIC16F87X devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC16F87X REGISTER 12-1: CP1 CP0 CONFIGURATION WORD (ADDRESS 2007h)(1) DEBUG — WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 bit13 bit 13-12, bit 5-4 bit0 CP1:CP0: FLASH Program Memory Code Protection bits(2) 11 = Code protection off 10 = 1F00h to 1FFFh code protected (PIC16F877, 876) 10 = 0F00h to 0FFFh code protected (PIC16F874, 873) 01 = 1000h to 1FFFh code protected (PIC16F877, 876) 01 = 0800h to 0FFFh code protected (PIC16F874, 873) 00 = 0000h to 1FFFh code protected (PIC16F877, 876)
PIC16F87X 12.2 FIGURE 12-2: Oscillator Configurations 12.2.1 OSCILLATOR TYPES The PIC16F87X can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor 12.2.2 OSC1 Clock from Ext.
PIC16F87X TABLE 12-2: Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq. Cap. Range C1 Cap. Range C2 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF These values are for design guidance only. See notes following this table. 12.2.
PIC16F87X 12.3 RESET The PIC16F87X differentiates between various kinds of RESET: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset (during normal operation) WDT Wake-up (during SLEEP) Brown-out Reset (BOR) Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET.
PIC16F87X 12.4 Power-On Reset (POR) 12.7 A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V - 1.7V). To take advantage of the POR, tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details. The configuration bit, BODEN, can enable or disable the Brown-out Reset circuit.
PIC16F87X TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD 0 x 1 1 Power-on Reset 0 x 0 x Illegal, TO is set on POR 0 x x 0 Illegal, PD is set on POR 1 0 1 1 Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR Reset during normal operation 1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP Legend: x = don’t care, u = unchanged TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Regist
PIC16F87X TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset Wake-up via WDT or Interrupt W INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu 873 874 876 877 N/A N/A N/A 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu 873 874 876 877 0000h 0000h PC + 1(2) (3) 873 874 876 877 0001 1xxx 000q quuu uuuq quuu(3) 873 874 876 877 xxxx xxxx uuuu uuuu uuuu uuuu 873
PIC16F87X TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Devices MCLR Resets, WDT Reset Power-on Reset, Brown-out Reset Wake-up via WDT or Interrupt PIE2 873 874 876 877 -r-0 0--0 -r-0 0--0 -r-u u--u PCON 873 874 876 877 ---- --qq ---- --uu ---- --uu PR2 873 874 876 877 1111 1111 1111 1111 1111 1111 SSPADD 873 874 876 877 0000 0000 0000 0000 uuuu uuuu SSPSTAT 873 874 876 877 --00 0000 --00 0000 --uu uuuu TXSTA 873 874 876 877 0000 -010 0000 -010 uuuu -uuu SPBRG 873 874 8
PIC16F87X FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 12-7: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 12-8: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30292C-page 128 2001 Microchip Technology Inc.
PIC16F87X 12.10 Interrupts The RB0/INT pin interrupt, the RB port change interrupt, and the TMR0 overflow interrupt flags are contained in the INTCON register. The PIC16F87X family has up to 14 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: The peripheral interrupt flags are contained in the special function registers, PIR1 and PIR2.
PIC16F87X 12.10.1 INT INTERRUPT 12.11 Context Saving During Interrupts External interrupt on the RB0/INT pin is edge triggered, either rising, if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16F87X 12.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin.
PIC16F87X 12.13 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16F87X FIGURE 12-11: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency(2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC Instruction Fetched Instruction Executed PC PC+1 Inst(PC) = SLEEP Inst(PC - 1) PC+2 PC+2 Inst(PC + 1) Inst(PC + 2) SLEEP Inst(PC + 1) PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) Not
PIC16F87X 12.17 In-Circuit Serial Programming PIC16F87X microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware, or a custom firmware to be programmed.
PIC16F87X 13.0 INSTRUCTION SET SUMMARY Each PIC16F87X instruction is a 14-bit word, divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16F87X instruction set summary in Table 13-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 13-1 shows the opcode field descriptions.
PIC16F87X TABLE 13-2: PIC16F87X INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W t
PIC16F87X 13.1 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [label] ADDLW Syntax: [label] BCF Operands: 0 ≤ k ≤ 255 Operands: Operation: (W) + k → (W) 0 ≤ f ≤ 127 0≤b≤7 Status Affected: C, DC, Z Operation: 0 → (f) Description: The contents of the W register are added to the eight bit literal ’k’ and the result is placed in the W register. Status Affected: None Description: Bit 'b' in register 'f' is cleared.
PIC16F87X CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 ≤ k ≤ 2047 Operands: None Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Operation: Status Affected: None 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16F87X DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ’f’ are decremented. If ’d’ is 0, the result is placed in the W register.
PIC16F87X MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: No operation Operation: (f) → (destination) Status Affected: None Status Affected: Z Description: No operation. Description: The contents of register f are moved to a destination dependant upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected.
PIC16F87X RLF Rotate Left f through Carry SLEEP Syntax: [ label ] RLF Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ’f’ are rotated one bit to the left through the Carry Flag. If ’d’ is 0, the result is placed in the W register. If ’d’ is 1, the result is stored back in register ’f’.
PIC16F87X SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [label] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Operation: (W) .XOR. (f) → (destination) Status Affected: Z Status Affected: None Description: Description: The upper and lower nibbles of register ’f’ are exchanged. If ’d’ is 0, the result is placed in the W register.
PIC16F87X 14.
PIC16F87X 14.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker.
PIC16F87X 14.8 MPLAB ICD In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PIC16F87X and can be used to develop for this and other PICmicro microcontrollers from the PIC16CXXX family. The MPLAB ICD utilizes the in-circuit debugging capability built into the PIC16F87X.
PIC16F87X 14.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs.
Software Tools Programmers Debugger Emulators 2001 Microchip Technology Inc. á PIC17C7XX á á á á á á PIC17C4X á á á á á á PIC16C9XX á á á á á PIC16F8XX á á á á á PIC16C8X á á á á á á PIC16C7XX á á á á á á PIC16C7X á á á á á á PIC16F62X á á á PIC16CXXX á á á á PIC16C6X á á á á PIC16C5X á á á á PIC14000 á á á PIC12CXXX á á á á á á á á á á á á á á á MCRFXXX á á á á á á á á á á MCP2510 á * Contact the Microchip Technology Inc. web site at www.microchip.
PIC16F87X NOTES: DS30292C-page 148 2001 Microchip Technology Inc.
PIC16F87X 15.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias................................................................................................................ .-55 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ....................................... -0.
PIC16F87X FIGURE 15-1: PIC16F87X-20 VOLTAGE-FREQUENCY GRAPH (COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ONLY) 6.0 V 5.5 V 5.0 V Voltage 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 16 MHz 20 MHz Frequency FIGURE 15-2: PIC16LF87X-04 VOLTAGE-FREQUENCY GRAPH (COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ONLY) 6.0 V 5.5 V Voltage 5.0 V 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 4 MHz 10 MHz Frequency FMAX = (6.0 MHz/V) (VDDAPPMIN - 2.
PIC16F87X FIGURE 15-3: PIC16F87X-04 VOLTAGE-FREQUENCY GRAPH (ALL TEMPERATURE RANGES) 6.0 V 5.5 V Voltage 5.0 V PIC16F87X-04 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 4 MHz Frequency FIGURE 15-4: PIC16F87X-10 VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE RANGE ONLY) 6.0 V 5.5 V Voltage 5.0 V PIC16F87X-10 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 10 MHz Frequency 2001 Microchip Technology Inc.
PIC16F87X 15.
PIC16F87X 15.
PIC16F87X 15.
PIC16F87X 15.2 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Operating voltage VDD range as described in DC specification (Section 15.1) DC CHARACTERISTICS Param No.
PIC16F87X 15.2 DC Characteristics: PIC16F873/874/876/877-04 (Commercial, Industrial) PIC16F873/874/876/877-20 (Commercial, Industrial) PIC16LF873/874/876/877-04 (Commercial, Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial 0°C ≤ TA ≤ +70°C for commercial Operating voltage VDD range as described in DC specification (Section 15.1) DC CHARACTERISTICS Param No.
PIC16F87X 15.3 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) PIC16F873/874/876/877-04 PIC16F873/874/876/877-20 (Extended) Param No. Symbol VDD Characteristic/ Device Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Min Typ† Max Units 4.0 — 5.5 V Conditions Supply Voltage D001 LP, XT, RC osc configuration D001A 4.5 5.5 V HS osc configuration D001A VBOR 5.
PIC16F87X 15.3 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) (Continued) PIC16F873/874/876/877-04 PIC16F873/874/876/877-20 (Extended) Param No. Symbol Min Typ† Max Units D010 — 1.6 4 mA RC osc configurations FOSC = 4 MHz, VDD = 5.5V D013 — 7 15 mA HS osc configuration, FOSC = 10 MHz, VDD = 5.5V — 85 200 µA BOR enabled, VDD = 5.0V 10.5 60 µA VDD = 4.
PIC16F87X 15.4 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Operating voltage VDD range as described in DC specification (Section 15.1) DC CHARACTERISTICS Param No.
PIC16F87X 15.4 DC Characteristics: PIC16F873/874/876/877-04 (Extended) PIC16F873/874/876/877-10 (Extended) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Operating voltage VDD range as described in DC specification (Section 15.1) DC CHARACTERISTICS Param No. Sym Characteristic Min Typ† Max Units VOL Output Low Voltage I/O ports OSC2/CLKOUT (RC osc config) Output High Voltage — — — — 0.6 0.6 V V IOL = 7.0 mA, VDD = 4.5V IOL = 1.
PIC16F87X 15.5 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16F87X FIGURE 15-6: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 15-1: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym Characteristic FOSC External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) 1 TOSC External CLKIN Period (Note 1) Oscillator Period (Note 1) 2 TCY Instruction Cycle Time (Note 1) TosL, External Clock in (OSC1) High or TosH Low Time Min Typ† Max Units DC DC DC DC DC DC 0.
PIC16F87X FIGURE 15-7: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 19 12 18 16 I/O Pin (Input) 15 17 I/O Pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 15-5 for load conditions. TABLE 15-2: Param No.
PIC16F87X FIGURE 15-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 15-5 for load conditions. FIGURE 15-9: BROWN-OUT RESET TIMING VBOR VDD 35 TABLE 15-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Parameter No.
PIC16F87X FIGURE 15-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 15-5 for load conditions. TABLE 15-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param No.
PIC16F87X FIGURE 15-11: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 15-5 for load conditions. TABLE 15-5: Param No. 50* CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Sym TccL CCP1 and CCP2 input low time Characteristic No Prescaler With Prescaler 51* TccH CCP1 and CCP2 input high time Typ† Max Units 0.
PIC16F87X FIGURE 15-12: PARALLEL SLAVE PORT TIMING (PIC16F874/877 ONLY) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 15-5 for load conditions. TABLE 15-6: Parameter No.
PIC16F87X FIGURE 15-13: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 15-5 for load conditions. FIGURE 15-14: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Note: Refer to Figure 15-5 for load conditions.
PIC16F87X FIGURE 15-15: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb BIT6 - - - - - -1 77 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 15-5 for load conditions. FIGURE 15-16: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN 77 BIT6 - - - -1 LSb IN 74 Note: Refer to Figure 15-5 for load conditions.
PIC16F87X TABLE 15-7: Param No.
PIC16F87X I2C BUS START/STOP BITS REQUIREMENTS TABLE 15-8: Parameter No.
PIC16F87X I2C BUS DATA REQUIREMENTS TABLE 15-9: Param No. Sym 100 Thigh Characteristic Clock high time Min Max Units 100 kHz mode 4.0 — µs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — µs Device must operate at a minimum of 10 MHz 0.5TCY — 100 kHz mode 4.7 — µs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — µs Device must operate at a minimum of 10 MHz SSP Module 101 Tlow Clock low time 0.
PIC16F87X FIGURE 15-19: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK Pin 121 121 RC7/RX/DT Pin 120 122 Note: Refer to Figure 15-5 for load conditions. TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC16F87X TABLE 15-12: PIC16F87X-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16F87X-10 (EXTENDED) PIC16F87X-20 (COMMERCIAL, INDUSTRIAL) PIC16LF87X-04 (COMMERCIAL, INDUSTRIAL) Param No. Sym A01 NR A03 Characteristic Min Typ† Max Units Resolution — — 10-bits bit VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF EIL Integral linearity error — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A04 EDL Differential linearity error — — <±1 LSb VREF = VDD = 5.
PIC16F87X FIGURE 15-21: A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 ... 7 ... 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-13: A/D CONVERSION REQUIREMENTS Param No. Sym 130 TAD Characteristic A/D clock period Units Conditions 1.
PIC16F87X NOTES: DS30292C-page 176 2001 Microchip Technology Inc.
PIC16F87X 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented is outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC16F87X FIGURE 16-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.6 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 1.4 5.5V 1.2 5.0V 1.0 I DD (mA) 4.5V 0.8 4.0V 3.5V 0.6 3.0V 0.4 2.5V 2.0V 0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 3.5 4.0 F OSC (MHz) FIGURE 16-4: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 2.0 1.8 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 1.6 5.
PIC16F87X FIGURE 16-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 90 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 80 5.5V 70 5.0V 60 IDD (uA) 4.5V 50 4.0V 3.5V 40 3.0V 30 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 F OS C (kH z ) FIGURE 16-6: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 120 110 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 100 5.0V 90 80 4.
PIC16F87X FIGURE 16-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, 25°C) 4.0 3.3kΩ 3.5 3.0 5.1kΩ Freq (MHz) 2.5 2.0 10kΩ 1.5 1.0 0.5 100kΩ 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 16-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, 25°C) 2.0 1.8 1.6 3.3kΩ 1.4 Freq (MHz) 1.2 5.1kΩ 1.0 0.8 0.6 10kΩ 0.4 0.2 100kΩ 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) DS30292C-page 180 © 2001 Microchip Technology Inc.
PIC16F87X FIGURE 16-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, 25°C) 1.0 0.9 0.8 3.3kΩ 0.7 Freq (MHz) 0.6 5.1kΩ 0.5 0.4 0.3 10kΩ 0.2 0.1 100kΩ 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 V DD (V) FIGURE 16-10: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 100.00 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Max (125C) 10.00 I PD (µ A) Max (85C) 1.00 0.10 Typ (25C) 0.01 2.0 2.5 3.0 3.
PIC16F87X FIGURE 16-11: ∆IBOR vs. VDD OVER TEMPERATURE 1.2 Note: 1.0 Device current in RESET depends on oscillator mode, frequency and circuit. Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) ∆ I BOR (mA) 0.8 Max Reset 0.6 Indeterminate State Typ Reset (25C) 0.4 Device in Sleep Device in Reset 0.2 Max Sleep Typ Sleep (25C) 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 16-12: TYPICAL AND MAXIMUM ∆ITMR1 vs.
PIC16F87X FIGURE 16-13: TYPICAL AND MAXIMUM ∆IWDT vs. VDD OVER TEMPERATURE 14 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 12 10 ∆ I WDT (uA) Max (85C) 8 Typ (25C) 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 16-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs.
PIC16F87X FIGURE 16-15: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO 125°C) 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 40 125C 35 WDT Period (ms) 85C 30 25 25C 20 -40C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 16-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=5V, -40°C TO 125°C) 5.0 Max (-40C) 4.5 Typ (25C) VOH (V) 4.0 3.5 Min (125C) 3.
PIC16F87X FIGURE 16-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD=3V, -40°C TO 125°C) 3.0 Max (-40C) Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 2.5 Typ (25C) VOH (V) 2.0 1.5 Min (125C) 1.0 0.5 0.0 0 5 10 15 20 25 I OH (-mA) FIGURE 16-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=5V, -40°C TO 125°C) 2.0 1.8 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 1.
PIC16F87X FIGURE 16-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD=3V, -40°C TO 125°C) 3.0 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 2.5 VOL (V) 2.0 1.5 Max (125C) 1.0 Typ (25C) 0.5 Min (-40C) 0.0 0 5 10 15 20 25 I OL (-mA) FIGURE 16-20: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40°C TO 125°C) 1.8 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 1.
PIC16F87X FIGURE 16-21: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO 125°C) 4.5 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 4.0 3.5 Max High (125C) 3.0 Min High (-40C) VIN (V) 2.5 2.0 Max Low (125C) 1.5 Min Low (-40C) 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 16-22: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40°C TO 125°C) 3.
PIC16F87X NOTES: DS30292C-page 188 © 2001 Microchip Technology Inc.
PIC16F87X 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example PIC16F876-20/SP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Legend: Note: * 0117HAT XX...
PIC16F87X Package Marking Information (Cont’d) 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead MQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS30292C-page 190 PIC16F877-04/P 0112SAA Example PIC16F877 -04/PT 0111HAT Example PIC16F877 -20/PQ 0104SAT Example PIC16F877 -20/L 0103SAT 2001 Microchip Technology Inc.
PIC16F87X 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c β B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 8.26 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 Molded Package Width E1 .275 .285 .295 6.
PIC16F87X 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E E1 p D B 2 1 n h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β A1 MIN .093 .088 .004 .394 .288 .695 .010 .
PIC16F87X 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) E1 D α 2 1 n E A2 A L c β B1 A1 eB p B Units Dimension Limits n p MIN INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .595 .600 .
PIC16F87X 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.
PIC16F87X 44-Lead Plastic Metric Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.
PIC16F87X 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) E E1 #leads=n1 D1 D n 1 2 CH2 x 45 ° CH1 x 45 ° α A3 A2 35° A B1 B c β E2 Units Dimension Limits n p A1 p D2 INCHES* NOM 44 .050 11 .165 .173 .145 .153 .020 .028 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .020 0 5 0 5 MIN MAX MILLIMETERS NOM 44 1.27 11 4.19 4.39 3.68 3.87 0.51 0.71 0.61 0.74 1.02 1.14 0.00 0.13 17.40 17.53 17.40 17.53 16.51 16.59 16.51 16.
PIC16F87X APPENDIX A: REVISION HISTORY Version Date Revision Description A 1998 This is a new data sheet. However, these devices are similar to the PIC16C7X devices found in the PIC16C7X Data Sheet (DS30390). Data Memory Map for PIC16F873/874, moved ADFM bit from ADCON1<5> to ADCON1<7>. B 1999 FLASH EEPROM access information. C 2000 DC characteristics updated. DC performance graphs added. 2001 Microchip Technology Inc.
PIC16F87X APPENDIX C: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1. TABLE C-1: CONVERSION CONSIDERATIONS Characteristic PIC16C7X PIC16F87X Pins 28/40 28/40 Timers 3 3 Interrupts 11 or 12 13 or 14 Communication PSP, USART, SSP (SPI, I2C Slave) PSP, USART, SSP (SPI, I2C Master/Slave) Frequency 20 MHz 20 MHz Voltage 2.5V - 5.5V 2.0V - 5.
PIC16F87X INDEX A A/D ................................................................................... 111 Acquisition Requirements ........................................ 114 ADCON0 Register .................................................... 111 ADCON1 Register .................................................... 112 ADIF bit .................................................................... 112 Analog Input Model Block Diagram .......................... 114 Analog Port Pins .......................
PIC16F87X PWM Mode ................................................................ 61 Block Diagram .................................................... 61 Duty Cycle .......................................................... 61 Example Frequencies/Resolutions (Table) ........ 62 PWM Period ....................................................... 61 Special Event Trigger and A/D Conversions .............. 60 CCP. See Capture/Compare/PWM CCP1CON ...............................................................
PIC16F87X Master Mode Operation ............................................. 79 Master Mode START Condition ................................. 80 Master Mode Transmission ........................................ 82 Master Mode Transmit Sequence .............................. 79 Multi-Master Communication ..................................... 89 Multi-master Mode ..................................................... 78 Operation ...................................................................
PIC16F87X O On-Line Support ............................................................... 207 OPCODE Field Descriptions ............................................ 135 OPTION_REG Register ............................................... 19, 48 INTEDG Bit ................................................................ 19 PS2:PS0 Bits .............................................................. 19 PSA Bit ....................................................................... 19 T0CS Bit ................
PIC16F87X PORTE ........................................................................... 9, 17 Analog Port Pins ...............................................9, 36, 38 Associated Registers ................................................. 36 Block Diagram ............................................................ 36 Input Buffer Full Status (IBF Bit) ................................ 37 Input Buffer Overflow (IBOV Bit) ................................ 37 Output Buffer Full Status (OBF Bit) ............
PIC16F87X SPI Master Mode .............................................................. 70 Master Mode Timing .................................................. 70 Serial Clock ................................................................ 69 Serial Data In ............................................................. 69 Serial Data Out ........................................................... 69 Serial Peripheral Interface (SPI) ................................ 65 Slave Mode Timing ...................
PIC16F87X Bus Collision During a Repeated START Condition (Case 1) ........................ 92 Bus Collision During a Repeated START Condition (Case2) ......................... 92 Bus Collision During a START Condition (SCL = 0) ................................... 91 Bus Collision During a STOP Condition ..................... 93 Bus Collision for Transmit and Acknowledge ............. 89 Capture/Compare/PWM ........................................... 166 CLKOUT and I/O ......................................
PIC16F87X W Wake-up from SLEEP .............................................. 119, 132 Interrupts .......................................................... 125, 126 MCLR Reset ............................................................. 126 Timing Diagram ........................................................ 133 WDT Reset ............................................................... 126 Watchdog Timer (WDT) ........................................... 119, 131 Block Diagram ...........................
PIC16F87X ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
PIC16F87X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
PIC16F87X PIC16F87X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX XXX Package Pattern Examples: a) b) Device PIC16F87X(1), PIC16F87XT(2); VDD range 4.0V to 5.5V PIC16LF87X(1), PIC16LF87XT(2 ); VDD range 2.0V to 5.
PIC16F87X NOTES: DS30292C-page 210 2001 Microchip Technology Inc.
PIC16F87X NOTES: 2001 Microchip Technology Inc.
PIC16F87X NOTES: DS30292C-page 212 2001 Microchip Technology Inc.
PIC16F87X NOTES: 2001 Microchip Technology Inc.
PIC16F87X NOTES: DS30292C-page 214 2001 Microchip Technology Inc.
PIC16F87X NOTES: 2001 Microchip Technology Inc.
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