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LBA7130

Oct., 2012, Version 0.6 (PRELIMINARY) 1 AMICCOM Electronics Corporation

Document Title

A7130 Data Sheet, 2.4GHz FSK/GFSK Transceiver with 4Mbps data rate

Revision History

Rev. No. History Issue Date Remark

0.0 Initial issue. Dec, 2009 Objective

0.1 Update ch8 and the application circuit. July, 2011 Preliminary,

0.2 Modify the tape reel information and the add Shenzhen office

address.

July, 2011 Preliminary,

0.3 Add Ch20 WOR and Ch21 AES128. Aug., 2011 Preliminary,

0.4 Add section 16.4.3 FIFO extension and Ch21 AES128.

Update sleep cur rent, Xtal start up time and PDL formula, TMOE

timing, WTR Timing, and Ch14.

Apr., 2012 Preliminary,,

0.5 Remove 3Mbps data rate

Add descriptions for HECF, FECF and CRCF clear method in 9.2.1

Aug.,2012 Preliminary

0.6 Add suggestion in WOR function Oct. 2012 Preliminary

Important Notice:

AMICCOM r eserves t he right t o make changes t o its products or to discontinue any integrated circu it prod uct or se rvice

without notice. AMICCOM integrated circuit products are not designed, intended, authorized, or warranted to be suitable for

use in life-support a pplications, de vices o r sys tems or ot her critical ap plications. Use of AM ICCOM products in such

applications is understood to be fully at the risk of the customer.

Summary of content (90 pages)

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LBA7130 Document Title A7130 Data Sheet, 2.4GHz FSK/GFSK Transceiver with 4Mbps data rate Revision History Rev. No. History Issue Date Remark 0.0 Initial issue. Dec, 2009 Objective 0.1 Update ch8 and the application circuit. July, 2011 Preliminary, 0.2 Modify the tape reel information and the add Shenzhen office address. July, 2011 Preliminary, 0.3 Add Ch20 WOR and Ch21 AES128. Aug., 2011 Preliminary, 0.4 Add section 16.4.3 FIFO extension and Ch21 AES128.
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LBA7130 Table of Contents 1. General Description....................................................................................................................................................... 5 2. Typical Applications ....................................................................................................................................................... 5 3. Feature ........................................................................................................................
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LBA7130 9.2.43 DASP2 (Address: 2Ah, Page 2 by AGT[3:0]=2) .........................................................................................30 9.2.43 DASP3 (Address: 2Ah, Page 3 by AGT[3:0]=3) .........................................................................................31 9.2.43 DASP4 (Address: 2Ah, Page 4 by AGT[3:0]=4) .........................................................................................31 9.2.43 DASP5 (Address: 2Ah, Page 5 by AGT[3:0]=5) ............................
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LBA7130 12.2 Use External Clock ............................................................................................................................................54 13. System Clock .............................................................................................................................................................55 13.2 Data Rate Setting .........................................................................................................................................
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LBA7130 1. General Description A7130 is a high performance and low cost 2.4GHz ISM band wireless transceiver. This device integrates both high sensitivity receiver (- 88dBm @4Mbps) and programmable power amplifier 5dBm. Based on Data Rate Register (39h), user can configure on-air data rates to 4Mbps. A7130 supports fast settling time (90 us) for frequency hopping system.
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LBA7130 u u u u u u Auto IF function. Auto FEC by (7, 4) Hamming code (1 bit error correction / code word). Separated 64 bytes RX and TX FIFO. Easy FIFO / Segment FIFO / FIFO Extension (up to 4K bytes). Support FIFO mode frame sync to MCU. Support direct mode with recovery clock output to MCU. REGI CKO GIO2 GIO1 19 18 17 16 VDD_D RFO 4 12 SCK RFC 5 11 SCS 10 13 XO 3 9 RFI XI SDIO 8 14 V_PLL 2 7 GND CP BP_BG VDD_A 15 6 1 V_VCO RSSI 20 4. Pin Configurations Fig 4-1.
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LBA7130 5. Pin Description (I: input; O: output, I/O: input or output) Pin No. Symbol I/O 1 RSSI O Connected to a bypass capacitor for RSSI. 2 BP_BG O Connected to a bypass capacitor for internal Regulator bias point. 3 RFI I LNA input. Connected to matching circuit. 4 RFO O PA input. Connected to matching circuit. 5 RFC I RF Choke input. Connected to matching circuit. 6 V_VCO I VCO supply voltage input. 7 CP O Charge-pump. Connected to loop filter.
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LBA7130 6. Chip Block Diagram Fig 6-1. A7130 Block Diagram Oct., 2012, Version 0.
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LBA7130 7. Absolute Maximum Ratings Parameter With respect to Rating Unit GND -0.3 ~ 3.6 V Digital IO pins range GND -0.3 ~ VDD+0.3 V Voltage on the analog pins range GND -0.3 ~ 2.1 V 10 dBm -55 ~ 125 °C HBM ± 2K V MM ± 100 V Supply voltage range (VDD) Input RF level Storage Temperature range ESD Rating *Stresses above those listed under “ Absolute Maximum Rating” may cause permanent damage to the device.
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LBA7130 8. Electrical Specification (Ta=25℃, VDD=3.3V, FXTAL =16MHz, with Match circuit and low pass filter, On Chip Regulator = 1.8V, unless otherwise noted.) Parameter Description Min. Type Max. Unit 85 3.3 3.6 °C V General Operating Temperature -40 Supply Voltage (VDD) with internal regulator 2.
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LBA7130 IF Filter bandwidth IF center frequency IFS = [11], 4Mbps IFS = [11], 4Mbps Co-Channel (C/I0) 7 Interference * (4Mbps , IF = 4MHz) Maximum Operating Input Power 4 RX Spurious Emission * RSSI Range 4.8M 4M 11 Hz Hz dB ±4MHz Adjacent Channel 0 dB ±8MHz Adjacent Channel - 10 dB ±12MHz Adjacent Channel - 20 dB ±16MHz Adjacent Channel - 30 dB Image (C/IIM) - 10 dB @RF input (BER=0.1%) 30MHz~1GHz 1GHz~12.
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LBA7130 9. Control Register A7130 contains 69 control registers. MCU can access those control registers via 3-wire (SCS, SCK, SDIO) or 4-wire (SCS, SCK, SDIO, GIO1/GIO2) SPI interface (max. 15 Mbps). Please refer to Chapter 10 for SPI timing. In general, most of control registers are just need to configure the recommended values based on A7130 reference code. 9.
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LBA7130 16h TX II 17h Delay I 18h Delay II 19h RX 1Ah RX Gain I 1Bh RX Gain II 1Ch RX Gain III 1Dh RX Gain IV 1Eh RSSI Threshold 1Fh ADC Control 20h Code I 21h Code II 22h Code III 23h IF Calibration I 24h IF Calibration II 25h VCO current Calibration 26h VCO band Calibration I 27h VCO band Calibration II 28h VCO deviation Calibration I 29h VCO deviation Calibration II 2Ah DASP0 W FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 W DPR2 DPR1 DPR0 TDL1 TDL0 PDL2 PDL1 PDL0 W WSEL2 WSEL1 WSEL0 RSSC_D1 RS
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LBA7130 2Bh VCO modulation Delay 2Ch Battery detect W DMV1 DMV0 DEVFD2 DEVFD1 DEVFD0 DEVD2 DEVD1 DEVD0 W LVR RGV1 RGV0 QDS BVT2 BVT1 BVT0 BD_E R -- RGV1 RGV0 BDF BVT2 BVT1 BVT0 BD_E RMP0 TXCS PAC1 PAC0 TBG2 TBG1 TBG0 DCM1 DCM0 MLP1 MLP0 SLF2 SLF1 SLF0 DCH0 DCL2 DCL1 DCL0 RAW CDTM1 CDTM0 CPM2 CPM1 CPM0 CPT3 CPT2 CPT1 CPT0 CPTX2 CPTX1 CPTX0 CPRX3 CPRX2 CPRX1 CPRX0 CPS CPH CPCS DBD XCC XCP1 XCP0 OLM PRIC1 PRIC0 PRRC1 PRRC0 SDPW NSDO D
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LBA7130 9.2 Control register description 9.2.1 Mode Register (Address: 00h) Name R/W Mode R W Bit 7 Bit 6 HECF FECF RESETN RESETN Bit 5 CRCF RESETN Bit 4 CER RESETN Bit 3 XER RESETN Bit 2 PLLER RESETN Bit 1 TRSR RESETN Bit 0 TRER RESETN RESETN: Write to this register by 0x00 to issue reset command, then it is auto clear HECF: Head Control Flag. (HECF will be clear after issue a strobe command.
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LBA7130 9.2.3 Calibration Control Register (Address: 02h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mode Control II R/W -- -- -- VCC VBC VDC FBC RSSC VCC: VCO Current calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. VBC: VCO Bank calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. VDC: VCO Deviation calibration enable (Auto clear when done). [0]: Disable. [1]: Enable. FBC: IF Filter Bank calibration enable (Auto clear when done).
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LBA7130 Recommend to set ID Byte 0 = 5xh or Axh. Refer to section 10.6 for details. 9.2.8 RC OSC Register I (Address: 07h) Name R/W RC OSC I R W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCOC7 RCOC6 RCOC5 RCOC4 RCOC3 RCOC2 RCOC1 RCOC0 WOR_SL7 WOR_SL6 WOR_SL5 WOR_SL4 WOR_SL3 WOR_SL2 WOR_SL1 WOR_SL0 RCOC [7:0]: Reserved for internal usage (read only). 9.2.
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LBA7130 [0000]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode. [0001]: DCK (TX data clock) in TX mode, RCK (RX recovery clock) in RX mode. [0010]: FPF (FIFO pointer flag). [0011]: EOP, EOVBC, EOFBC, EOVCC, EOVDC, RSSC_OK. (Internal usage only). [0100]: External clock output= FSYCK / 2. [0101]: External clock output / 2= FSYCK / 4. [0110]: RXD [0111]: FSYNC. [1000]: WCK. [1001]: PF8M.(8Mhz, internal usage) [1010]: ROSC.
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LBA7130 RX Mode (disable Auto-ack, EAK =0). Note1, If auto-resend is enabled (EAR = 1), WTR behavior is different while it is output to GIO1 and GIO2. Note2, If auto-ack is enabled (EAK = 1), WTR behavior is different while it is output to GIO1 and GIO2. Note3, VPOAK’s behavior is controlled by VPM (0Bh) and VPW (0Bh). Refer to chapter 19 for details GIO1S [3:0]: GIO1 pin function select.
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LBA7130 9.2.13 GIO2 Pin Control Register II (Address: 0Ch) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 GIO2 Pin Control II W BBCKS1 BBCKS0 GIO2S3 GIO2S2 GIO2S1 GIO2S0 Bit 1 Bit 0 GIO2I GI O2OE BBCKS [1:0]: Clock select for digital block. Recommend BBCKS = [00]. [00]: FSYCK. [01]: FSYCK / 2. [10]: FSYCK / 4. [11]: FSYCK / 8. GIO2S [3:0]: GIO2 pin function select.
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LBA7130 SPI (SCS,SCK,SDIO) RX-Strobe Next Instruction No Command Required PLL Mode Auto Back PLL Mode 10us+PDL+TDL RF Port (Input) Preamble + ID Code + Payload + CRC GIO1 Pin - WTR (GIO1S[3:0]=0000) GIO2 Pin - FSYNC (GIO2S[3:0]=0001) ID-Matched T0 T2 T1 < 1us 9.2.14 Clock Register (Address: 0Dh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Clock W R CGC1 IFS1 CGC0 IFS0 GRC3 GRC3 GRC2 GRC2 GRC1 GRC1 GRC0 GRC0 CGS -- XS -- CGC [1:0]: Clock Gen. Current select.
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LBA7130 CHR [3:0]: PLL channel step setting. In FIFO mode, recommend to set CHR [3:0] = [0111]. In Direct mode, recommend to set CHR [3:0] = [1111]. Please refer to chapter 14 and A7130 reference code for details. 9.2.
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LBA7130 Group3 CHGH ~ 255 9.2.22 TX Register I (Address: 15h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TX I W GDR GF TMDE TXDI TME FDP2 FDP1 FDP0 GDR: Gaussian Filter Over Sampling Rate Select. Recommend GDR = [1]. [0]: BT= 0.7 [1]: BT= 0.5 GF: Gaussian Filter Select. [0]: Disable. [1]: Enable. TMDE: TX modulation enable for VCO modulation. Recommend TMDE = [1]. [0]: Disable. [1]: Enable. TXDI: TX data invert. Recommend TXDI = [0]. [0]: Non-invert. [1]: Invert.
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LBA7130 000 000 000 010 011 100 G IO 1 P in (W T R ) 70 us 90 us 110 us PLL M ode TX M ode PA Ramp Down T X S tro be R F O P in 16 u s P a ck e t 10 u s + P D L TDL 9.2.25 Delay Register II (Address: 18h) Name R/W Bit 7 Bit 6 Bit 5 Delay W WSEL2 WSEL1 WSEL0 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RSSC_D1 RSSC_D0 RS_DLY2 RS_DLY1 RS_DLY0 WSEL [2:0]: XTAL settling delay setting (200us ~ 2.5ms). Recommend WSEL = [011]. [000]: 200us. [001]: 400us. [010]: 600us. [011]: 800us. [100]: 1ms. [101]: 1.
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LBA7130 ULS: RX Up/Low side band select. Recommend ULS = [0]. [0]: Up side band, [1]: Low side band. Refer to section 14.2 for details. 9.2.27 RX Gain Register I (Address: 1Ah) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX Gain I W R PRS -- MIC MICR IGC1 IGCR1 IGC0 IGCR0 MGC1 MGCR1 MGC0 MGCR0 LGC1 LGCR1 LGC0 LGCR0 Bit 3 Bit 2 Bit 1 Bit 0 PRS: Limiter amplifier discharge manual select. Recommend PRS =[0]. MIC: Mixer buffer gain setting. Recommend MIC =[1]. [0]: 0dB.
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LBA7130 RL [7:0]: RSSI Calibration Low Threshold. (Ready only) 9.2.30 RX Gain Register IV (Address: 1Dh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RX Gain III W LIMC IFBC1 IFBC0 IFAS MHC1 MHC0 LHC1 LHC0 LIMC: IF limiter current select. Recommend LIMC = [1]. [0]: 0.3mA. [1]: 0.6mA. IFBC [1:0]: IF BPF current Select. Recommend IFBC = [11]. [00]: 0.75 mA.. [01]: 1.4mA. [10]: 2.1mA. [11]: 3.5mA. IFAS: IF Amp current select. Recommend IFAS = [0]. [0]: 0.3mA. [1]: 0.6mA.
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LBA7130 MSC: Manchester Enable. [0]: Disable. [1]: Enable. WHTS: Data Whitening (Data Encryption) Select. [0]: Disable. [1]: Enable (The data is whitening by multiplying PN7). FECS: FEC Select. [0]: Disable. [1]: Enable (The FEC is (7, 4) Hamming code). CRCS: CRC Select. Recommend CRCS = [1]. [0]: Disable. [1]: Enable. IDL [1:0]: ID Code Length Select. Recommend IDL= [01]. [00]: 2 bytes. [01]: 4 bytes. [10]: 6 bytes. [11]: 8 bytes. PML [1:0]: Preamble Length Select. Recommend PML= [11]. [00]: 1 byte.
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LBA7130 [0]: Auto calibration value. [1]: Manual calibration value. MFB [3:0]: IF filter manual calibration value. FBCF: IF filter auto calibration flag (read only). [0]: Pass. [1]: Fail. FB [3:0]: IF filter calibration value (read only). MFBS= 0: Auto calibration value (AFB), MFBS= 1: Manual calibration value (MFB). 9.2.
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LBA7130 CWS: Clock Disable for VCO Modulation. Recommend CWS = [1]. [0]: Enable. [1]: Disable. MVBS: VCO bank calibration value select. Recommend MVBS = [0]. [0]: Auto calibration value. [1]: Manual calibration value. MVB [2:0]: VCO band manual calibration value. VBCF: VCO band auto calibration flag (read only). [0]: Pass. [1]: Fail. VB [2:0]: VCO bank calibration value (read only). MVBS= 0: Auto calibration value (AVB). MVBS= 1: Manual calibration value (MVB). 9.2.
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LBA7130 9.2.43 DASP0 (Address: 2Ah, Page 0 by AGT [3:0]=0) Name DASP0 R/W Bit 7 Bit 6 W QLIM RFSP Bit 5 Bit 4 INTXC CSXTL4 (CSXTL5) Bit 3 Bit 2 Bit 1 Bit 0 CSXTL3 CSXTL2 CSXTL1 CSXTL0 QLIM: quick charge select for IF limiter amp. Recommend QLIM = [0]. [0]: disable. [1]: enable. (QLIM fall down delay 10 us). RFSP: RF single port Select. Recommend RFSP = [0]. [0]: LNA (RFI) and PA (RFO) are combined internally to RFI pin. [1]: LNA (RFI) and PA (RFO) are separated to RFI pin and RFO pin.
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LBA7130 9.2.43 DASP3 (Address: 2Ah, Page 3 by AGT[3:0]=3) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DASP3 W DCV7 DCV6 DCV5 DCV4 DCV3 DCV2 DCV1 DCV0 DCV [7:0]: Demodulator Fix mode DC value. Recommend DCV = [0x80]. 9.2.43 DASP4 (Address: 2Ah, Page 4 by AGT[3:0]=4) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DASP4 W/R VMG7 VMG6 VMG5 VMG4 VMG3 VMG2 VMG1 VMG0 VMG [7:0]: VM Center Value for Deviation Calibration. Recommend VMG [7:0] = [0x80].
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LBA7130 DMV [1:0]: Demodulator D/A Voltage Range Select. Recommend DMV = [11]. [00]: 1/32*1.2. [01]: 1/16*1.2. [10]: 1/8*1.2. [11]: 1/4*1.2. DEVFD [2:0]: VCO Modulation Data Delay by 8x over-sampling Clock. Recommend DEVFD = [011]. DEVD [2:0]: VCO Modulation Data Delay by XCPCK Clock. Recommend DEVD = [100]. 9.2.
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LBA7130 [01]: Preamble hold mode. DC level is preamble average value. [10]: ID hold mode. DC level is the average value hold about 8 bit data rate later if preamble is detected. [11]: Payload average mode (For internal usage). DC level is payload data average. MLP1: Reserved for internal usage. Shall set MLP1 = [0]. MLP0: Reserved for internal usage. Shall set MLP0 = [0]. SLF [2:0]: Symbol Recovery Loop Filter Setting. Shall be SLF[2:0] = [111]. 9.2.
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LBA7130 DBD: Crystal Frequency Doubler High Level Pulse Width Select. Recommend DBD = [0]. [0]: about 8 ns. [1]: about 16 ns. XCC: Crystal Startup Current Selection. Recommend XCC = [1]. [0]: about 0.7 mA. [1]: about 1.5 mA. XCP [1:0]: Crystal Oscillator Regulated Couple Setting. Recommend XCP = [01]. [00]: 1.5mA. [01]: 0.5mA. [10]: 0.35mA. [11]: 0.3mA. 9.2.
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LBA7130 RFT [3:0]: RF analog pin configuration for testing. Recommend RFT= [0000]. 9.2.55 AES Key data Register (Address: 36h) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Key Data R W KEYO7 KEYI7 KEYO6 KEYI6 KEYO5 KEYI5 KEYO4 KEYI4 KEYO3 KEYI3 KEYO2 KEYI2 KEYO1 KEYI1 KEYO0 KEYI0 KEYI [7:0]: AES128 key input, total 16-btyes. (Write only). KEYO [7:0]: AES128 key output, total 16-bytes. (Read only). Select by KEYOS (3Eh).
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LBA7130 [1]: auto program. [0]: manual SPI setting. MPA [1:0]: OPT address setting in manual SPI OTP program. FBG [4:0]: Bandgap voltage SPI fine trim setting. 9.2.57 ROMP2 (Address: 38h, Page 2 by AGT[3:0]=2) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROMP2 W PTM1 PTM0 CTR5 CTR4 CTR3 CTR2 CTR1 CTR0 PTM [1:0]: OTP program operation mode select. Recommend PTM = [00]. CTR [5:0]: ADC voltage SPI fine trim setting. 9.2.
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LBA7130 [0001]: 1 [0010]: 2 [0011]: 3 [0100]: 4 [0101]: 5 [0110]: 6 [0111]: 7 [1000]: 8 [1001]: 9 [1010]: 10 [1011]: 11 [1100]: 12 [1101]: 13 [1110]: 14 [1111]: 15 EAK : Enable Auto ACK. [0]: Disable. [1]: Enable. EAR : Enable Auto Resend. [0]: Disable. [1]: Enable. ARTEF: Auto re-transmission ending flag (read only). [0]: Resend not end [1 ]: Finish resend. VPOAK : Valid Packet or ACK OK Flag. (read only and auto clear by Strobe command) [0]: Neither valid packet nor ACK OK. [1]: Valid packet or ACK OK.
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LBA7130 Byte Name Bit-Map Description Strobe Cmd 0 FCB0 0 0 1 1 1 SID2 SID1 SID0 For auto-resend. NA 1 FCB1 [7:0] ACK info NA by user’s attaching 2 FCB2 [7:0] 3 FCB3 [7:0] Remark: 1. Please refer to section 10.4.10 for details. 2. SID is auto incremental for every new packet if FCB0 is enabled. 3. FCB0 ~ FCB3 is controlled by FCL[1:0] (3Ah) 4. User can attach wanted ACK information to FCB1 ~ FCB3 if auto-ack is enabled (EAK =1). Please refer to chapter 16 and 19 for details.
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LBA7130 10. SPI A7130 only supports one SPI interface with maximum data rate up to 15Mbps. MCU should assert SCS pin low (SPI chip select) to active accessing of A7130. Via SPI interface, user can access control registers and issue Strobe command. Figure 10.1 gives an overview of SPI access manners. 3-wire SPI (SCS, SCK and SDIO) or 4-wire SPI (SCS, SCK, SDIO and GIO1/GIO2) configuration is provided. For 3-wire SPI, SDIO pin is configured as bi-direction to be data input and output.
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LBA7130 10.1 SPI Format The first bit (A7) is critical to indicate A7130 the following instruction is “Strobe command” or “control register”. See Table 10.1 for SPI format. Based on Table 10.1, To access control registers, just set A7=0, then A6 bit is used to indicate read (A6=1) or write operation (A6=0). See Figure 10.2 (3-wire SPI) and Figure 10.3 (4-wire SPI) for details. CMD A7 R/W A6 Address Byte (8 bits) Address A5 A4 A3 A2 A1 A0 7 6 5 Data Byte (8 bits) Data 4 3 2 1 0 Table 10.
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LBA7130 10.3 SPI Timing Chart In this section, 3-wire and 4-wire SPI interface read / write timing are described. 10.3.
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LBA7130 10.4 Strobe Commands A7130 supports 8 Strobe commands to control internal state machine for chip’s operations. Table 10.3 is the summary of Strobe commands. Be notice, Strobe command could be defined by 4-bits (A7~A4) or 8-bits (A7~A0). If 8-bits Strobe command is selected, A3 ~ A0 are don’t care conditions. In such case, SCS pin can be remaining low for asserting next commands.
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LBA7130 Strobe Command Strobe Command A7 A6 A5 A4 A3 A2 A1 A0 1 0 0 1 x X x x SCS Description Idle mode SCS SCK SCK SDIO A7 A6 A5 SDIO A4 A7 A6 Idle mode A5 A4 A3 A2 A1 A0 Idle mode Figure 10.5 Idle mode Command Timing Chart 10.4.3 Strobe Command - Standby Mode Refer to Table 10.3, user can issue 4 bits (1010) Strobe command directly to set A7130 into Standby mode. Below is the Strobe command table and timing chart.
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LBA7130 Figure 10.7 PLL mode Command Timing Chart 10.4.5 Strobe Command - RX Mode Refer to Table 10.3, user can issue 4 bits (1100) Strobe command directly to set A7130 into RX mode. Below are the Strobe command table and timing chart. Strobe Command Strobe Command A7 1 A6 1 A5 0 A4 0 A3 x A2 X A1 x Description A0 x RX mode Figure 10.8 RX mode Command Timing Chart 10.4.6 Strobe Command - TX Mode Refer to Table 10.3, user can issue 4 bits (1101) Strobe command directly to set A7130 into TX mode.
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LBA7130 Refer to Table 10.3, user can issue 4 bits (1110) Strobe command directly to reset A7130 FIFO write pointer. Below is the Strobe command table and timing chart. Strobe Command Strobe Command A7 1 A6 1 A5 1 A4 0 A3 x A2 x A1 x Description A0 x FIFO write pointer reset Figure 10.10 FIFO write pointer reset Command Timing Chart 10.4.8 Strobe Command – FIFO Read Pointer Reset Refer to Table 10.3, user can issue 4 bits (1111) Strobe command directly to reset A7130 FIFO read pointer.
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LBA7130 Figure 10.12 Deep Sleep Mode Timing Chart 10.5 Reset Command In addition to power on reset (POR), MCU could issue software reset to A7130 by setting Mode Register (00h) through SPI interface as shown below. As long as 8-bits address (A7~A0) are delivered zero and data (D7~D0) are delivered zero, A7130 is informed to generate internal signal “RESETN” to initial itself. After reset command, A7130 is in standby mode and calibration procedure shall be issued again.
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LBA7130 Figure 10.15 ID Write Command Timing Chart 10.6.2 ID Read Command User can refer to Figure 10.2 for SPI read timing chart in details. Below is the procedure of ID read command. Step1: Step2: Step3: Deliver A7~A0 = 01000110 (A6=1 for read, A5~A0 = 000110 for ID addr, 06h). SDIO pin outputs 32-bits ID in sequence by Data Byte 0, 1, 2 and 3. Toggle SCS pin to high when step2 is completed. Figure 10.16 ID Read Command Timing Chart 10.
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LBA7130 Figure 10.17 TX FIFO Write Command Timing Chart 10.7.2 Rx FIFO Read Command User can refer to Figure 10.2 for SPI read timing chart in details. Below is the procedure of RX FIFO read command. Step1: Step2: Step3: Deliver A7~A0 = 01000101 (A6=1 for read control register and issue FIFO at address 05h). SDIO pin outputs RX data from RX FIFO in sequence by Data Byte 0, 1, 2 to n. Toggle SCS pin to high when RX FIFO is read completely. Figure 10.18 RX FIFO Read Command Timing Chart Oct.
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LBA7130 11. State machine From accessing data point of view, if FMS=1, FIFO mode is enabled, otherwise, A7130 is in direct mode. 3-Wire SPI 4-Wire SPI SPI chip select SPI Clock SPI Data In SPI Data Out SCS SCK SDIO SDIO SCS SCK SDIO GIO1 or GIO2 FMS register FIFO (FMS=1) Direct (FMS=0) FIFO (FMS=1) Direct (FMS=0) From current consumption point of view, A7130 has below 8 operation modes.
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LBA7130 11.2 FIFO mode This mode is suitable for the requirements of general purpose applications and can be chosen by setting FMS = 1. After calibration, user can issue Strobe command to enter standby mode where write TX FIFO or read RX FIFO. From standby mode to packet data transmission, only one Strobe command is needed. Once transmission is done, A7130 is auto back to standby mode. Figure 11.1 and Figure 11.2 are TX and RX timing diagram respectively. Figure 11.3 illustrates state diagram of FIFO mode.
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LBA7130 Figure 11.3 State diagram of FIFO Mode 11.3 Direct mode This mode is suitable to let MCU to drive customized packet to A7130 directly by setting FMS = 0. In TX mode, MCU shall send customized packet in bit sequence (simply called raw TXD) to GIO1 or GIO2 pin. In RX mode, the receiving raw bit streams (simply called RXD) can be configured output to GIO1 or GIO2 pin. Be aware that a customized packet shall be preceded by a 32 bits preamble to let A7130 get a suitable DC estimation voltage.
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LBA7130 Strobe CMD (SCS,SCK,SDIO) RFO TX STB strobe Strobe RF settling 10us+(PDL+TDL) GIO1 Pin - WTR (GIO1S[3:0]=0000) Modulated signals Carrier only Pin Manually back to STB Preamble + customized raw TXD Modulation auto enable GIO1 Pin - TMEO (GIO1S[3:0]=0010) 32-bits preamble GIO2 Pin - TXD (GIO2S[3:0]=1001) T1 T0 T4 T3 Figure 11.
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LBA7130 Figure 11.6 State diagram of Direct Mode Oct., 2012, Version 0.
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LBA7130 12. Crystal Oscillator A7130 needs external crystal or external clock that is either 16 MHz (or 18MHz) to generate internal wanted clock. Relative Control Register Clock Register (Address: 0Dh) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Clock W R CGC1 IFS1 CGC0 IFS0 GRC3 GRC3 GRC2 GRC2 GRC1 GRC1 GRC0 GRC0 CGS -- XS -- 12.1 Use External Crystal Figure 12.1 shows the connection of crystal network between XI and XO pins.
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LBA7130 13. System Clock A7130 supports different crystal frequency by programmable “Clock Register”. Based on this, three important internal clocks FCGR , FDR and FSYCK are generated. (1) FXTAL: Crystal frequency. (2) FXREF: Crystal Ref. Clock = FXREF * (DBL+1). (3) FCGR: Clock Generation Reference = 2MHz = FXREF / (GRC+1). (4) FSYCK: System Clock is related to FIF and FDR. (6) FDR: Data Rate Clock = FIF / (SDR+1). Data Rate 4Mbps 4Mbps DBL (0Fh) 0 (FIFO mode) 1 (Direct mode) FCGR 2MHz 2MHz CLK Gen.
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LBA7130 14. Transceiver LO Frequency A7130 is a half-duplex transceiver with embedded PA and LNA. For TX or RX frequency setting, user just needs to set up LO (Local Oscillator) frequency for two ways radio transmission. To target full range of 2.4GHz ISM band (2408 MHz to 2468 MHz), A7130 applies offset concept by LO frequency F LO = FLO_BASE + F OFFSET. Therefore, this device is easy to implement frequency hopping and multi-channels by just ONE register setting, PLL Register I (CHN [7:0]).
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LBA7130 3 4 5 6 RRC BIP[8:0] BFP[15:0] FLO_BASE 0 0x096 0x0004 2400.001 MHz If so, FPFD= 16MHz To get FLO_BASE =2400 MHz To get FLO_BASE ~ 2400.001 MHz LO Base frequency DBL = 1 for Direct mode STEP ITEMS 1 FXTAL 2 DBL 3 RRC 4 BIP[8:0] 5 BFP[15:0] 6 FLO_BASE VALUE 16 MHz 1 0 0x04B 0x0002 2400.001 MHz NOTE Crystal Frequency Enable double function If so, FPFD= 16MHz To get FLO_BASE =2400 MHz To get FLO_BASE ~ 2400.001 MHz LO Base frequency Table 14.
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LBA7130 14.2.1 Auto IF Exchange A7130 supports Auto IF offset function by setting AIF = 1. In such case, FTXRF between master and slave is the same so that there is only one carrier frequency (Fcarrier) during communications. Meanwhile, FRXLO during TRX exchanging is auto shifted FIF. See below Figures and Table 14.3 for details. Master AIF=1 and ULS=0, FRXLO is auto shifted lower than FTXRF for a (FIF).
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LBA7130 14.2.2 Fast Exchange Fast exchange can reduce the PLL settling time during TRX exchanging because FRXLO and FTXRF are kept to the same FLO in either master or slave side. However, there are two on-air frequency (FCarrier (master), FCarrier (slave)) during communications. In such case, user has to control ULS =0 in master side and ULS = 1 in slave side for two ways radio. See below Figures and Table 14.4 for details. Master AIF=0 and ULS=0, Master is set to up side band.
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LBA7130 14.3 Auto Frequency Compensation The AFC function (Auto Frequency Compensation) supports to use low accuracy crystal (±50 ppm) on A7130 without sensitivity degradation. The AFC concept is automatically fine tune RX LO frequency (FRXLO). User can read AC [14:0] to know the compensation value of FRXLO. F XTAL X (DBL+1) AC[14:0]/ 2 16 0 BIP[8:0] + BFP[15:0]/ 2 16 CHN / [4*(CHR+1)] F LO_BASE + F LO F PFD / (RRC[1:0]+1) VCO PFD 1 Divider 0 AFC F LO + F OFFSET Figure 14.
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LBA7130 16. FIFO (First In First Out) A7130 has the separated physical 64-bytes TX and RX FIFO inside the device. To use A7130’s FIFO mode, user just needs to enable FMS =1. For FIFO accessing, TX FIFO (write-only) and RX FIFO (read-only) share the same register address 05h. TX FIFO represents transmitted payload. On the other hand, RX circuitry synchronizes ID Code and stores received payload into RX FIFO. 16.1 TX Packet Format in FIFO mode 16.1.
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LBA7130 a u to ac k /re se n d P r e a m b le 4 b y te s d y n a m ic F IF O ID c o d e FC B FEP 4 b yt e s 1 ~ 4 b y te s 1 2 b i ts P H Y H e a d e r ( s e lf - g e n e r a te d ) P a y lo a d P h y . 6 4 b y te s (C R C ) 2 b yt e s M A C H e a d e r ( s e lf - g e n e r a te d ) Figure 16.2 TX packet format of advanced FIFO mode. FCB: If FCL[1:0] ≠00, FCB header is enabled to support ACK FIFO by (FCB1~FCB3). The FCB is frame control byte.
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LBA7130 FEC (Forward Error Correction): 1. 2. FEC is enabled by FECS= 1. Payload and CRC value (if CRCS=1) are encoded by (7, 4) Hamming code. Each 4-bits (nibble) of payload is encoded into 7-bits code word and delivered out automatically. (ex., 64 bytes payload will be encoded to 128 code words, each code word is 7 bits.) RX circuitry decodes received code words automatically. Each code word can correct 1-bit error. Once 1-bit error occurred, FECF=1 (00h). 3. Data Whitening: 1.
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LBA7130 16.4.1 Easy FIFO In Easy FIFO mode, max FIFO length is 64 bytes. FIFO length is equal to ( FEP [11:0] +1 ) where FEP [11:0] is max 0x003F. User just needs to control FEP [11:0] (03h) and disable PSA and FPM as shown below. TX-FIFO (byte) 1 8 16 32 64 RX-FIFO (byte) 1 8 16 32 64 FEP[11:0] (03h) 0x00 0x07 0x0F 0x1F 0x3F PSA[5:0] (04h) 0 0 0 0 0 FPM[1:0] (04h) 0 0 0 0 0 Table 16.2 Control registers of Easy FIFO Procedures of TX FIFO Transmitting 1.
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LBA7130 16.4.2 Segment FIFO In Segment FIFO, TX FIFO length is equal to (FEP [11:0] － PSA [5:0]＋1). FPM [1:0] should be zero. This function is very useful for button applications. In such case, each button is used to transmit fixed code (data) every time. During initialization, each fixed code is written into corresponding segment FIFO once and for all. Then, if button is triggered, MCU just assigns corresponding segment FIFO (PSA [5:0] and FEP [11:0]) and issues TX strobe command. Table 16.
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LBA7130 Figure 16.6 Segment FIFO Mode Oct., 2012, Version 0.
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LBA7130 16.4.3 FIFO Extension A7130 supports FIFO extension up to 4K bytes from the 64 bytes physical TX FIFO and RX FIFO. The FIFO extension length is configured by (FEP [11:0] +1 and PSA [5:0] =0). FPM [1:0] is used to set the FPF threshold which FPF is FIFO Pointer Flag to inform MCU the timing of reading RX FIFO and refilling TX FIFO. Please be notice, SPI speed is important to prevent error operation (over-write) in FIFO extension mode. We recommend the min.
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LBA7130 Figure 16.7 TX FIFO Extension Oct., 2012, Version 0.
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LBA7130 Procedures of RX FIFO Reading 1. Initialize all control registers (refer A7130 reference code). 2. Set FEP [11:0] = 0x0FF for 256-bytes FIFO extension. 3. Set FPM [1:0] = [11b] for FPF threshold. 4. Set CKO Register = 0x12 5. Issue Strobe command – RX FIFO read pointer reset. 6. Issue RX Strobe command. 7. MCU monitors FPF from A7130’s CKO pin. 8. FPF triggers MCU to read 1st 48-bytes RX FIFO. 9. Monitor FPF. 10. FPF triggers MCU to read 2nd 48-bytes RX FIFO. 11. Monitor FPF. 12.
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LBA7130 Figure 16.8 RX FIFO Extension Mode Oct., 2012, Version 0.
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LBA7130 17. ADC (Analog to Digital Converter) A7130 has built-in 8-bits ADC for RSSI measurement and internal thermal sensor by enabling ADCM. User can just use the recommended va lues of ADC from Tab le 17.1. P lease noted tha t ADC clock can be selected by s etting FSARS (4MHz or 8MHz). The ADC converting time is 20 x ADC clock periods. XADS (1Fh) 0 RSS (1Ch) 1 ARSSI (01h) 1 ADCM ERSSM FSARS (01h) (1Ch) (1Fh) 1 1 0 CDM (1Fh) 1 Standby Mode RX Mode Thermal sensor RSSI Table 17.
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LBA7130 Auto RSSI measurement for TX Power of the coming packet: 1. 2. 3. 4. 5. Set wanted FRXLO. Set recommend values of Table 17.1. Enable ADCM = 1. Send RX Strobe command. Once frame sync (FSYNC) is detected or exiting RX mode, user can read digital RSSI value from ADC [7:0] for TX power of the coming packet.
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LBA7130 18. Battery Detect A7130 has a built-in battery detector to check supply voltage (REGI pin). The detecting range is 2.0V ~ 2.7V into 8 levels. Battery detect Register (Address: 2Ch) Name R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Battery detect W R LVR -- RGV1 RGV1 RGV0 RGV0 QDS BDF BVT2 BVT2 BVT1 BVT1 BVT0 BVT0 BD_E BD_E BVT [2:0]: Battery voltage detect threshold. [000]: 2.0V. [001]: 2.1V. [010]: 2.2V. [011]: 2.3V. [100]: 2.4V. [101]: 2.5V. [110]: 2.6V. [111]: 2.7V.
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LBA7130 19. Auto-ack and auto-resend A7130 supports auto-resend and auto-ack scheme by enable EAK = 1 (auto-ack) and EAR = 1 (auto-resend). In application points of view, this feature is also ok to enable together with other feature options like FCB and/or EDRL (dynamic FIFO). 19.1 Basic FIFO plus auto-ack auto-resend Set EAF = 0, EAK = 1 and EAR = 1 to enable auto-ack and auto-resend. Please refer to the below TX and ACK packet format of the sender and the receiver site respectively. 19.
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LBA7130 Oct., 2012, Version 0.
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LBA7130 19.3 WTR Behavior during auto-ack and auto-resend If auto-ack and auto-resend are enabled (EAR = EAK = 1), WTR represents a completed transmission period and CWTR is a debug signal which represents the cyclic TX period and cyclic RX period. Please refer to the below timing diagrams for details. The sender site (auto-resend) The receiver site (auto-ack) Remark: Refer to 3Bh for ARD[7:0] setting (auto resend delay). Refer to 3Fh for RND[7:0] setting (random seed for resend interval).
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LBA7130 19.6 Examples of auto-ack and auto-resend Once EAK and EAR are enabled, below case 1 ~ case 3 illustrate the most common cases as a timing reference (assume ARD = 800 us) in two ways radio communications. Always success Success in second packet Oct., 2012, Version 0.
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LBA7130 always resend failure Oct., 2012, Version 0.
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LBA7130 20. RC Oscillator A7130 has an internal RC oscillator to supports WOR (Wake On RX) and TWOR (Timer Wake On RX) function. RCOSC_E (09h) is used to enable RC oscillator. WORE (01h) is used to enable WOR function and TWORE (09h) is used to enable TWOR function. After done calibrations of RC oscillator, WOR and TWOR function can be operated from -40℃ to 85℃. Parameter Calibrated Freq. Sleep period RX period Operation temperature Min 3.8K 7.82 0.244 -40 Max 4.2K 8007.
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LBA7130 20.2 TWOR Function The RC oscillator inside A7130 can also be used to supports programmable TWOR (Timer Wake-On, TWORE=1) function which enables A7130 to output a periodic square wave from GIO1 (or GIO2). The duty cycle of this square wave is set by WOR_AC (08h) or WOR_SL (08h and 07h) regarding to TSEL (09h). User can use this square wave to wake up MCU or other purposes. 21. AES128 Security Packet A7130 has a built-in AES128 co-processor to generate a security packet by a general purpose MCU.
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LBA7130 22. Application circuit 22.1 MD7 0-A01 AMICCOM’s ref. design module, MD7130-A01, max 5 dBm output power, application circuit example. 1 3 GIO1 16 SDIO 12 XO XI C7 2.2uF J3 CON/2P 2.0 SCK SCS 11 SCS 9 VDD_A 1 2 A7130 10 6 RFC CON/2P 2.0 SDIO 14 13 SCK VDD_PLL 5 J2 15 VDD_D A7130PKG RFO C5 100pF 1 2 GIO1 GIO2 17 GIO2 CKO CKO VIN 18 BP_BG RFI 4 REGI VDD_A GND CP C15 1.8pF L2 2.7nH J1 1 2 3 4 5 6 7 8 9 10 CON/10P 2.
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LBA7130 22.2 MD7 0-F07 AMICCOM’s ref. design module, MD7130-F07, typical 17 dBm output power together with a range extendor A7700. 4 3 1 C10 1pF C 16 GIO1 GIO1 18 CKO 17 GIO2 SDIO RFI 4 GIO2 19 REGI33 GND RFC C29 100pF 14 SDIO C20 2.2uF 13 VDD_D A7130PKG RFO 5 15 12 SCK SCK SCS 11 SCS C XO L9 3.3nH 47 U1 BP_BG XI R1 PA_IN L10 3.3nH 3 D BP_RSSI VDD_PLL C16 1pF LNA_OUT 2 C18 2.2uF CKO C2 100pF VDD_A C3 1nF 20 VDD_A C5 4.
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LBA7130 23.
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LBA7130 25. Package Information QFN 20L (4 X 4 X 0.8mm) Outline Dimensions TOP VIEW BOTTOM VIEW 0.25 C D D2 11 11 15 L 15 16 10 10 e E E2 16 20 6 0.25 C 20 6 1 5 5 e b 1 0.10 M C A B Seating Plane Symbol A3 A1 A // 0.10 C C Dimensions in inches Dimensions in mm Min Nom Max A 0.028 0.030 0.032 0.70 0.75 0.80 A1 0.000 0.001 0.002 0.00 0.02 0.05 A3 Min 0.008 REF Nom Max 0.203 REF b 0.007 0.010 0.012 0.18 0.25 0.30 D 0.154 0.158 0.161 3.90 4.
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LBA7130 26. Top Marking Information A71C30AQFI ¡ ¡ ¡ ¡ ¡ ¡ Part No. Pin Count Package Type Dimension Mark Method Character Type : A71C30AQFI : 20 : QFN : 4*4 mm : Laser Mark : Arial J 7 0 C1 K L C2 F NNNNNNNNN Y Y WW X B D G C3 A I v CHARACTER SIZE : (Unit in mm) A : 0.55 B : 0.36 C1 : 0.25 C3 : 0.2 D : 0.03 :DATECODE Y YWW X : PKG HOUSE ID N N N N N N N N N : LOT NO. (max. 9 characters) C2 : 0.3 F=G I=J K=L 0.6 5 0.8 0 1.6 0 0.6 8 Oct., 2012, Version 0.
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LBA7130 27. Reflow Profile Actual Measurement Graph Oct., 2012, Version 0.
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LBA7130 28. Tape Reel Information Cover / Carrier Tape Dimension TYPE 20 QFN 4*4 24 QFN 4*4 32 QFN 5*5 QFN3*3 / DFN-10 20 SSOP 24 SSOP P 8 8 8 4 12 12 A0 4.35 4.4 5.25 3.2 8.2 8.2 B0 4.35 4.4 5.25 3.2 7.5 8.8 TYPE 20 QFN (4X4) 24 QFN (4X4) 32 QFN (5X5) QFN3*3 / DFN-10 20 SSOP 24 SSOP Oct., 2012, Version 0.6 (PRELIMINARY) P0 4.0 4.0 4.0 4.0 4.0 4.0 P1 2.0 2.0 2.0 2.0 2.0 2.0 K0 1.1 1.4 1.1 0.75 2.5 2.1 t 0.3 0.3 0.3 0.25 0.3 0.3 87 D0 1.5 1.5 1.5 1.5 1.5 1.5 D1 1.5 1.5 1.5 1.5 1.5 E 1.75 1.
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LBA7130 REEL DIMENSIONS UNIT IN mm TYPE G N 20 QFN(4X4) 24 QFN(4X4) 32 QFN(5X5) DFN-10 12.8+0.6/-0.4 100 REF 48 QFN(7X7) 16.8+0.6/-0.4 28 SSOP (150mil) 20 SSOP 24 SSOP 20.4+0.6/-0.4 16.4+2.0/-0.0 100 REF 100 REF 100 REF T M D K L 18.2(MAX) 1.75±0.25 13.0+0.5/-0.2 2.0±0.5 R 330＋ 20.2 0.00/-1.0 330＋ 22.2(MAX) 1.75±0.25 13.0+0.5/-0.2 2.0±0.5 0.00/-1.0 20.2 330＋ 25(MAX) 1.75±0.25 13.0+0.5/-0.2 2.0±0.5 0.00/-1.0 20.2 330＋ 22.4(MAX) 1.75±0.25 13.0+0.2/-0.2 1.9±0.4 0.00/-1.0 20.
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LBA7130 29. Product Status Data Sheet Identification Objective Product Status Planned or Under Development Definition This data sheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary Engineering Samples and First Production This data sheet contains preliminary data, and supplementary data will be published at a later date.
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Modular Approal: The LBA 7130RF module is designed to comply with the FCC statement. FCC ID is OIE51402TR. The host system using LBA 7130RF, should have label indicated FCC ID: OIE51402TR. This radio module must not installed to co-locate and operating Simultaneously with other radios in host system, additional testing and equipment authorization may be required to operating simultaneously with other radio FCC Statement： 1. This device complies with Part 15 of the FCC Rules.