Publication TSM 20-319 TECHNICAL MANUAL 1KW UHF INTERNALLY D IPLEXED TV TRANSMITTER MX1000U SERIES LARCAN INC.
INTRODUCTION This manual describes the LARCAN model MX1000U, internally diplexed UHF television transmitter. LARCAN all-solid-state 1 kW UHF transmitters are designed to operate conservatively at 1 kW peak sync visual/vision RF power and 100W average aural/sound single carrier RF power, with superb performance, reliability and operating economy.
Facilities are provided on the control board for telemetry, status, and control connections to and from a remote control system. These are available on 25 pin D-sub connector. For remote control operation, simply press the REMOTE switch (LED illuminated). This places +12V on Remote Enable line and allows the transmitter to be turned on and off via remote control.
• • • • • • • • • operating power in achieved. Use a thru-line type Wattmeter to measure the transmitter power. Select FWD on the analog meter select switch and adjust R164 on the control board until the forward power meter (analog meter) reads 100%. To calibrate the aural power, refer to the RF detector board description and setup procedure. Calibration of the reflected power metering and the VSWR cutback and trip is detailed next.
TABLE OF CONTENTS 1. 2. INTRODUCTION .........................................................................................................................1 CIRCUIT DESCRIPTION..............................................................................................................2 Visual Forward And Combined Reflected Circuit Description ..............................................................2 Aural Forward Metering............................................................................
Figure 1: RF Detector Board 2. CIRCUIT DESCRIPTION Drawing references: 41D1607 sheet 1 (Figure 3), and 41D1607S sheet 1 (Figure 4). The visual/aural RF Detector board is fitted with two RF detectors, which respond to RF samples fed from RF directional couplers mounted on transmission lines in the amplifier cabinets and/or on external probe sections. The modulation envelope blanking level is measured because it remains constant, regardless of the picture content of the transmission.
porch. The detected video signal is phase split by Q2 (Q7) to produce two 180° out of phase signals. The inverted video signal, after being buffered by Q11(Q13), is fed to input pin 11 of sync separator Ul (U8). Ul (U8), pin 7 is an open collector "mute" output, which switches off when adequate horizontal sync pulses matching the setting of R28 (R57) are present, lighting CR2 (CR4) the "sync ok" LED. If a TV sync signal is not detected, pin 7 collector goes low, and CR2 (CR4) is turned off.
requires an external amplifier, and the exciter aural output may be used as an unmodulated source if required (A LARCAN exciter visual/vision section can not deliver unmodulated RF). TEST PROCEDURE • • For test setup, see Figure 2. 1. 2. 3. 4. 5. 6. 7. 8. TEST EQUIPMENT REQUIRED 12 V power supply UHF preamplifier (approx 200mWo/p). Video Generator. Modulator. UHFUpconverter. Oscilloscope. Spectrum Analyzer. VHF / UHF Two Way Splitter. Connect board under test to power supply.
Figure 2. Test Setup For Visual + Aural RF Detector Assembly.
TABLE OF CONTENTS 1. 2. INTRODUCTION .........................................................................................................................1 CIRCUIT DESCRIPTION..............................................................................................................1 Front End Preamp. ........................................................................................................................1 IPA Module .....................................................................
modified. Doing so without prior authorization from factory service personnel will void any warranty. When the detected voltage rises above the preset level, the output of the comparator U3D goes high, and forces transistor Q1 to the "on" state through diode CR7. Other inputs to Q1 include the reflected (VSWR) signal, an external mute signal and a power-up delay circuit consisting of U5D configured as a comparator along with R47 through R50 and C20.
Drain current of the two FETs is sampled by the voltage drop across R7. When this voltage exceeds approximately 0.5V at normal operating temperature (about 1.5 amps total FET current), Q3 begins conduction and feeds voltage to pin 2 of the regulator to start its current foldback/limiter circuit. The regulator reduces its output voltage, which in turn reduces the bias on the FETs, they decrease their drain currents, reducing the voltage drop across R7 and over-current protection is achieved.
provides adjustment for balance between Q1 and Q2. Thermistors R21 and R22 provide thermal stability for the bias. MODULE I NTERFACE BOARD. This PC board is located on the rear of each PA module. The RF input and DC input to the module enters via this interface board. Four fuses are located on this board. Three fuses are in line with the 3 output PA pallets and one with the front end, IPA and driver modules.
The front panel current meter will give an indication of the current drawn by the modules in comparison to one another both under drive conditions and under static bias conditions. Check the current under drive conditions for overdrive situations and under static bias conditions (no drive) for amplifier stage failure. Check for potential connector problems causing either no drive to a module (input connector) or VSWR (output connector) problems.
• • • • • Increase RV3 clockwise slowly and check that the maximum current limits itself at 1.6 ±0.1 Amp but do not allow current to go above 2 amps while performing this test. Reset RV3 to achieve 6.5 ±0.2 volts measured at the junction of R5 and RV100. Check balance of the two transistors with a voltmeter connected between the hot sides of C105 and C115; difference voltage should be less than 3 mV. Apply RF drive (max.
TABLE OF CONTENTS 1. 2. 3. 4. INTRODUCTION .............................................................................................................1 BLOWER REPLACEMENT ..............................................................................................1 COMBINER AND REJECT LOAD .....................................................................................1 THERMAL SWITCH AND AIR SWITCH ............................................................................2 Thermal Switch .......
are located in the module housing on an assembly similar to the module assembly. The Reject load assembly is within the cooling air plenum and comprises all three reject loads for the combiners. This reject load assembly is not removable when the transmitter is under power and as such incorporates SMA connectors and is held in place additionally by screws through the rear of the module housing. A sample of the input to each of the loads is provided on the front panel of the reject load assembly.
TABLE OF CONTENTS 1. 2. 3 INTRODUCTION .............................................................................................................................1 CIRCUIT DESCRIPTION..................................................................................................................1 TEST AND TROUBLESHOOTING....................................................................................................1 General.............................................................................
shift. The bulk of the phase relationship between the signal is developed within the hybrid splitters themselves. Additionally, the gain controls on the splitter is only for fine matching of the module outputs. TROUBLESHOOTING If trouble is suspected with the splitter unit itself, the following checks may be done to pinpoint the cause of failure. • • • • • Turn off the transmitter With +12V connected to E1, verify that there is +8V (±0.1V) at pin 3 of VR1. Disconnect the AGC signal to E2.
* * * * R97 R98 C37 R95 R96 C36 R93 R94 C35 R91 R92 C34 R89 R90 C33 R87 R88 C32 R85 R86 C31 * * * * * * R83 R84 C30 R81 R82 C29 R79 R80 C28 R77 R78 C27 R75 R76 C26 R73 R74 C25 * * * * * * * * Rx Ry Cx FIGURE 1 4 PWR U2 - U6 11
TABLE OF CONTENTS 1. INTRODUCTION .............................................................................................................1 MX1000 Power supply. ........................................................................................................1 Linear Regulator..................................................................................................................1 2. CIRCUIT DESCRIPTION.....................................................................................
2. CIRCUIT DESCRIPTION The linear regulator assembly incorporates the following circuitry: • A semiconductor-controlled rectifier bridge, the input filter capacitor and power resistors (Q1, C1 and R63, R64 respectively). This circuitry is shown in block A on the schematic diagram. • The Voltage Regulator itself (block B). • The control circuitry (block C,D,E,F,G )which provides a few different functions including over-current protection, over-voltage protection and power-on and reset functions.
as that of the overcurrent circuitry with a couple of exceptions. One of the common causes of failure in a series linear regulator is the short circuit of the series pass transistor. Once the pass transistor has shorted, there is no way to shut down the regulator output (to prevent over-voltage damage to the power amplifiers), hence the SCR bridge that effectively disconnects the entire regulator from the transformer secondary.
the output of U8 (pin8) to go high. This triggers flip-flop U10a. Once set, the flip-flop output (pin 6) stays high until a reset pulse clears the flip-flop. The output of the flip-flop activates a yellow LED (over-voltage indicator CR5), the over-voltage counter, U14b, the ‘trip recorded’ circuit of U29b and the regulator shutdown circuitry of U25d.
Additionally, the main control board of transmitter can issues a reset command on pin 1 of connector J1 (operator pressing tx front panel reset button). This external reset command will only have an effect only if an overload trip has been recorded and is disregarded otherwise. In this case U19 activates relay K2. 3. TESTING AND TROUBLESHOOTING With the exception of replacing the pass transistor in this circuit, repair of the circuitry on these units in the field is not recommended.
TABLE OF CONTENTS 1. 2. 3. 4. 1. INTRODUCTION .........................................................................................................................1 CIRCUIT DESCRIPTION..............................................................................................................1 TESTING AND TROUBLESHOOTING..........................................................................................2 PARTS LIST.................................................................................
(R16/C11). When the voltage across the capacitor reaches a predetermined level as set by the voltage divider R10/R11 (R13/R14), the output of comparator UlA (UlB) goes high causing the solid state relay K7 (K5) to turn on, shorting out the surge limiting resistors. 3. TESTING AND TROUBLESHOOTING This board is essentially an interconnect circuit for the transmitter and, as such there are not many circuits on the board to require service.
DS11 R46 J8-37 R45 TX ON CMD L1 +12V L1 L1 1uH DS12 L2 9 11 8 L2 THERMAL 1 FAIL J13 1 2 R1 NC 1 2 NC J15 220uF NC CR9 16 1 JP1 J8-39 BLOWER ON CMD 9 8 11 K3 6 6 K2 2 2 K1 6 J7 1N4001 K6 DS2E-S-DC12V 1 2 CR8 +12V R41 16 1 4 E1 K5 DS2E-S-DC12V R36 E8 51K 9 6 E2 8 11 TO RESISTOR 1 E7 EMERGENCY INTERLOCK +12V 13 DS5 ON CMD TO BLOWER 20K DS9 13 T92S11A12-240 4 9 1 8 4 9 1 8 4 T92S11A12-240 1N4001 51K 2 THERMAL 2 FAIL T92S11A12-240 9 1 R2 8
M8 -12V M6 M3 +12V +5V M9 1 +12V R7 L3 L4 L5 M7 M5 M4 M1 +5V C7 2K7 DS3 J3 .1uF U3 R22 7K5 PS1 FAIL 1 1 8 8 2 2 7 7 R29 3 3 6 6 4 4 5 5 F2 J1-1 L1 J8 L2 J1-2 2K -12V J8-31 PS1 STATUS 1 2 3 4 5 6 7 8 F1 CR3 80SQ040 +12V R23 MC34161 1K CR2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 L2 -12V 8K2 L7 CR1 80SQ040 +12V R24 +5V C8 2K7 DS4 F4 PS2 FAIL .
TABLE OF CONTENTS 1. 2. INTRODUCTION .............................................................................................................1 CIRCUIT DESCRIPTION..................................................................................................1 General...............................................................................................................................1 On/Off Control And Interlock Functions . ...................................................................
the MX1000 was designed for dual uses. On the MX1000, this board is configured to control a single transmitter. In another configuration (internally referred to as Group-2), this board controls dual PA/Power supply cabinets. ON/O FF CONTROL A ND INTERLOCK F UNCTIONS (P AGE 1 OF T HE SCHEMATIC ). The ON/OFF state of the transmitter is determined by the state of the latching relay K6.
AGC A ND VSWR PROTECTION (P AGE 4 OF T HE SCHEMATIC). The AGC circuitry is designed to maintain the power of the transmitter at a particular power level, however the AGC circuit is also used to generate cutback protection in the event of excessive output VSWR. Output power is sampled and detected by the RF detector board and fed to the AGC circuitry J8. U35A buffers the voltage and feeds the metering display circuitry through calibration pot R164.
issued, causing the VSWR trip led to record the VSWR trip. Now, once K11 trips, the input capacitor to U31 A will start to charge. When it passes +5V, relay K11 will be set back to it's original state and the transmitter will turn on again. In this way, a momentary VSWR will cause the transmitter to trip off and then restart. However, each time relay K11 trips, the monostable IC U30B sends a pulse to slightly charge capacitor C92.
arming voltage is present and the grounding of a remote control input will result in that command being issued. A remote reset command on J11-5 will cause the opto U24 to send a reset command. This reset is split into an active low and an active high reset by transistors U20 B and D. Connectors J12, J13, J14, and J15 bring information from the PA's to the remote interface. On those connectors pin 3 brings the cutback voltage, and pin 5 brings a RF OK indication.
• • • • • • • • • • • On power-up the LEDs on the VIS switch for POWER METERING should be lit as should the LED on the PA1 switch for METERING. When a switch button is pressed the corresponding LED should illuminate. Select the VIS metering function on the POWER METERING section. Connect a variable power supply set to 4 volts to J8-9. Adjust R164 for a reading of 100% on the power meter. R219 may need adjustment in order to get the correct deflection on the meter. Select the RFL metering function.
• • • • • • • • Press the REMOTE switch to set the control into ‘Remote’ mode. The LED on the REMOTE switch should be illuminated. Press the OFF switch. The OFF LED will illuminate. Verify that when the ON switch is pressed, there is no change in state. Set the control back to ‘remote’ mode. Ground J11-7, and verify that the OFF LED turns on. Ground J11-6 and verify that the ON LED turns on and the OFF LED is extinguished.
• • • • • Adjust R137 and verify that DS6 can be turned on and off by this adjustment. Apply +4V to J8-9. Adjust R128 for 4.0 Volts at U28-9. Apply +4V to J8-6. The VSWR TRIP LED should illuminate and the VSWR L/O LED will illuminate after a few seconds. Remove the voltage from J8-6. Press RESET to clear the VSWR TRIP and VSWR L/O LEDs. Briefly touching +4V to J8-6 and removing it 3 times within a few seconds will cause theVSWR L/O LED to come on and stay on until RESET is pressed.
VSWR OUT TRIP (SH.4) 1 1 4 4 3 4 3 LOCAL/REMOTE 6 5 6 5 8 7 8 7 S10 3 1 5 6 2 R62 1K MMPQ2222A TQ2SA-L2-12V U17D HSMS-2800 9 CR22 HSMS-2800 8 1 16 7 2 1 14 6 5 R107 330pF C84 1K U26A MOCD207 R105 1K5 DS9 U15B MOCD207 +12V J11-23 Cab 1 Air Ok (SH.6) 1 5 CR20 HSMS-2800 J11-24 Cab 2 Temp Ok (SH.6) U26B MOCD207 R101 1K5 4 4 R104 330pF C82 1K 5 3 6 1K5 3 R103 CAB 2 TEMP 2 REMOTE ON CMD J11-6 (SH.
+12V +12V +12V TQ2SA-L2-12V 9 7 +12V 3 R39 R244 2 1 4K7 1K Q5 MSD601 3 R34 R245 2 1 4K7 1K Q6 MSD601 +5V Ain Bin Cin Din Ein S4 6 5 8 7 10 9 2 1 4 3 S2 6 5 PA4 8 7 10 9 2 1 4 3 S9 6 5 AGC V 8 7 10 9 2 1 4 3 S7 6 5 PA5 8 7 10 9 2 1 4 3 S5 6 5 PA6 8 7 10 9 2 1 4 3 6 5 8 7 10 9 2 1 4 3 6 5 8 7 7 R33 C31 1K 1000pF 2 1K Q8 MSD601 3 R19 R246 2 1 4K7 1K Q7 MSD601 3 R11 R248 2 1 4K7 1K Q9 MSD601 JP1 14 4 +5V 2
+12V +12V R156 51K R151 1 1K Q14 MSD601 3 R192 R254 2 1 4K7 1K Q15 MSD601 4 3 S18 6 5 OVERALL AURAL 8 7 10 9 2 1 4 3 S25 6 5 CAB 1 VIS 8 7 10 9 2 1 4 3 S22 6 5 CAB 1 REFL 8 7 10 9 2 1 4 3 6 5 8 7 4 1 14 3 12 5 Ain Bin Cin Din Ein 7 OsciIn OscOut 10 9 2 1 4 3 6 5 8 7 3 R149 1K Q16 10 9 2 1 4 3 6 5 8 7 10 9 2 1 4 3 6 5 8 7 1 MSD601 R255 2 4K7 3 R158 1K Q18 1 MSD601 R257 2 4K7 1 14 3 12 5 S24 CAB 1 AUR 7 R199 U36 4
+12V TQ2SA-L2-12V K10 10 6 VSWR TRIP 9 8 7 +12V 2 DS13 3 R112 4 1 2K 5 100K 5K U29B R139 7 10K LM324 R132 R145 470K U29D 12 6 5 R144 3K6 10K U28B LM324 7 CR28 HSMS-2800 1 10K 5 4 3 1 2 16 CR26 HSMS-2800 U30A R152 6 4K7 & 13 U33B MMPQ2222A R CX RX/CX 7 14528 C89 +12V 12 11 10K R178 U33D R190 2K R187 9 9 2 1 4 3 6 5 8 7 2K U43 X9C103P +12V 6 - U31B 7 LM324 5 R150 3K 11 10K U33C R154 1K 12 Active High Reset (SH.1) CV THR U41 555 6 LOCAL ARM (SH.
+12V 4 PA1 I SH.2 R15 1K R221 1K 3 + 2 U2A C19 330pF - R14 1K 1K C51 PA2 I SH.2 330pF R18 CR32 HSMS-2800 J3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 HSMS-2800 CR4 1K 330pF 5 + 7 6 -U2B LM324 C24 330pF R16 C18 R229 1K 1K 330pF C21 330pF R230 10 + 8 U2C 9 LM324 R231 C12 R233 1K 1K 330pF C15 330pF 12 + 14 13 -U2D LM324 HSMS-2800 PA5 I SH.2 CR3 CR1 HSMS-2800 C6 R4 1K 330pF PA6 I SH.
C41 1K 330pF 13 - LM324 430 C46 U12A MOCD207 LM324 330pF 1K 11 4 4 C59 330pF R45 430 C38 330pF 1K5 C64 330pF C60 330pF 5 + 6 - LM324 74HC08 10 + 9 - 9 1K5 7 C70 330pF LM324 430 C67 330pF 5 1K5 C37 330pF gnd M7 gnd 14 14 7 4 7 1 gnd 1 M4 1 gnd 1 M1 1 M9 gnd gnd M6 1 M10 J15 U25B MOCD207 M8 1 M5 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 13 74HC08 7 U5B MOCD207 gnd R47 330pF R70 12 U46B MOCD207 M2 U11A MOCD207 C43 U14C 14 LM324 14 14 C48 330pF +
TABLE OF CONTENTS 1. 2. INTRODUCTION .............................................................................................................1 OUTPUT ALIGNMENT.....................................................................................................1 Required Equipment: ...........................................................................................................1 Procedure..........................................................................................................
6. Set L103 and L105 for minimum insertion loss. 7. Flatten the response using L101 and L107. 8. Set L201 and L202 for the out-of-band ± difference beats. Note: Notch filters L201 and/or L202 may or may not be present. If both filters are present, try each notch on both sides as one combination may have less adverse effects on the bandpass than the other. Figure 1. Sweep Alignment Test Set-up 9. 10. Re-flatten the response using L101 and L102. Set width of filter using L103 and L105.
Figure 2. Ideal NTSC Response 11. 12. Adjusting L105 and L107 interactively with each other, tune for proper bandwidth and best out-of-band rejection. Adjusting L103 and L101 interactively with each other, tune for proper bandwidth and best out-of-band rejection. Figure 3. Return Loss Set-up 13. 14. Configure the equipment for return loss measurements, as shown in Figure 3. Return loss should be 30 dB at carriers (Reference Figure 4). Figure 4. Ideal Return Loss 15.
17. If the response is acceptable (less than 0.8 dB loss), return to the return loss setup and lock down all adjustments on the bandpass filter. 18. Notches should be locked down after performing the final fine adjustment with a television signal. 3. OUTPUT CHANNELING INFORMATION BPF Lines 3 ea. • 470-600 MHz Part Number 6920-6008 • 600-806 MHz Part Number 6920-6009 Notch Filter Line Discs 2 ea.
