Cinterion® PLS8-X/PLS8-V Hardware Interface Description Version: 03.016 DocId: PLS8-X_PLS8-V_HD_v03.016 M2M.GEMALTO.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 2 of 105 2 Document Name: Cinterion® PLS8-X/PLS8-V Hardware Interface Description Version: 03.016 Date: 2015-12-09 DocId: PLS8-X_PLS8-V_HD_v03.016 Status Confidential / Released GENERAL NOTE THE USE OF THE PRODUCT INCLUDING THE SOFTWARE AND DOCUMENTATION (THE "PRODUCT") IS SUBJECT TO THE RELEASE NOTE PROVIDED TOGETHER WITH PRODUCT. IN ANY EVENT THE PROVISIONS OF THE RELEASE NOTE SHALL PREVAIL.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 3 of 105 Contents 105 Contents 0 Document History ....................................................................................................... 8 1 Introduction ................................................................................................................. 9 1.1 Supported Products ........................................................................................... 9 1.2 Related Documents ...................
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 4 of 105 Contents 105 3.13 Control Signals................................................................................................. 45 3.13.1 PWR_IND Signal ................................................................................ 45 3.13.2 Behavior of the RING0 Line ................................................................ 45 3.13.3 Remote Wakeup ...........................................................................
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 5 of 105 Contents 105 7.3 Packaging ........................................................................................................ 90 7.3.1 Tape and Reel .................................................................................... 90 7.3.1.1 Orientation........................................................................... 90 7.3.1.2 Barcode Label ..................................................................... 91 7.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 6 of 105 Tables 105 Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Directives .....................................................................................
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 7 of 105 Figures 105 Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39:
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 8 of 105 0 Document History 8 0 Document History Preceding document: "Cinterion® PLS8-X/PLS8-V Hardware Interface Description" v02.510 New document: "Cinterion® PLS8-X/PLS8-V Hardware Interface Description" Version 03.016 Chapter What is new Throughout document Added information on dead reckoning synchronization line. 1.4 Removed ECE-R 10 directive from Table 1. Updated NAPRD version in Table 2. 2.1 Added USAT as supported feature. 3.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 9 of 105 1 Introduction 15 1 Introduction The document1 describes the hardware of the two Cinterion® modules variants PLS8-V and PLS8-X, designed to connect to a cellular device application and the air interface. It helps you quickly retrieve interface specifications, electrical and mechanical details and information on the requirements to be considered for integrating further components.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 10 of 105 1.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 11 of 105 1.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 12 of 105 1.4 Regulatory and Type Approval Information 15 1.4 Regulatory and Type Approval Information 1.4.1 Directives and Standards PLS8-X/PLS8-V has been designed to comply with the directives and standards listed below.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 13 of 105 1.4 Regulatory and Type Approval Information 15 Table 4: Standards of the Ministry of Information Industry of the People’s Republic of China SJ/T 11363-2006 “Requirements for Concentration Limits for Certain Hazardous Substances in Electronic Information Products” (2006-06). SJ/T 11364-2006 “Marking for Control of Pollution Caused by Electronic Information Products” (2006-06).
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 14 of 105 1.4 Regulatory and Type Approval Information 15 1.4.2 SAR requirements specific to portable mobiles Mobile phones, PDAs or other portable transmitters and receivers incorporating a GSM module must be in accordance with the guidelines for human exposure to radio frequency energy.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 15 of 105 1.4 Regulatory and Type Approval Information 15 1.4.3 SELV Requirements The power supply connected to the PLS8-X/PLS8-V module shall be in compliance with the SELV requirements defined in EN 60950-1. 1.4.4 Safety Precautions The following safety precautions must be observed during all phases of the operation, usage, service or repair of any cellular terminal or mobile incorporating PLS8-X/PLS8-V.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 16 of 105 2 Product Concept 20 2 Product Concept 2.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 17 of 105 2.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 18 of 105 2.1 Key Features at a Glance 20 Feature Implementation USB USB 2.0 High Speed (480Mbit/s) device interface Serial interface ASC0: • 8-wire modem interface with status and control lines, unbalanced, asynchronous • Adjustable baud rate of 115,200bps to 921,600bps • Supports RTS0/CTS0 hardware flow control UICC interface 2 UICC interfaces (switchable) Supported chip cards: UICC/SIM/USIM 3V, 1.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 19 of 105 2.2 PLS8-X/PLS8-V System Overview 20 2.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 20 of 105 2.3 Circuit Concept 20 2.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 21 of 105 3 Application Interface 50 3 Application Interface PLS8-X/PLS8-V is equipped with an SMT application interface (LGA pads) that connects to the external application. The host interface incorporates several sub-interfaces described in the following sections: • • • • • • • • • • Operating modes - see Section 3.1 Power supply - see Section 3.2 RTC backup - see Section 3.5 Serial interface USB - see Section 3.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 22 of 105 3.1 Operating Modes 50 3.1 Operating Modes The table below briefly summarizes the various operating modes referred to in the following chapters. Table 6: Overview of operating modes Mode Function Normal GSM / GPRS / operation UMTS / HSPA / LTE SLEEP Power saving set automatically when no call is in progress and the USB connection is detached and no active communication via ASC0.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 23 of 105 3.2 Power Supply 50 3.2 Power Supply PLS8-X/PLS8-V needs to be connected to a power supply at the SMT application interface - 4 lines BATT+, and GND. There are two separate voltage domains for BATT+: • BATT+_RF with 2 lines for the RF power amplifier supply • BATT+ with 2 lines for the general power management.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 24 of 105 3.2 Power Supply 50 3.2.1 Minimizing Power Losses When designing the power supply for your application please pay specific attention to power losses. Ensure that the input voltage VBATT+ never drops below 3.3V on the PLS8-X/PLS8-V board, not even in a transmit burst where current consumption can rise to typical peaks of 2A. It should be noted that PLS8-X/PLS8-V switches off when exceeding these limits.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 25 of 105 3.3 Power-Up / Power-Down Scenarios 50 3.3 Power-Up / Power-Down Scenarios In general, be sure not to turn on PLS8-X/PLS8-V while it is beyond the safety limits of voltage and temperature stated in Section 6.1. PLS8-X/PLS8-V immediately switches off after having started and detected these inappropriate conditions. In extreme cases this can cause permanent damage to the module. 3.3.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 26 of 105 3.3 Power-Up / Power-Down Scenarios 50 3.3.2 Signal States after Startup Table 7 describes the various states each interface signal passes through after startup and during operation. Signals are in an initial state while the module is initializing. Once the startup initialization has completed, i.e. when the software is running, all signals are in defined state.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 27 of 105 3.3 Power-Up / Power-Down Scenarios 50 3.3.3 Turn off PLS8-X/PLS8-V Using AT Command The best and safest approach to powering down PLS8-X/PLS8-V is to issue the AT^SMSO command. This procedure lets PLS8-X/PLS8-V log off from the network and allows the software to enter into a secure state and save data before disconnecting the power supply. The mode is referred to as Power Down mode. In this mode, only the RTC stays active.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 28 of 105 3.3 Power-Up / Power-Down Scenarios 50 3.3.4 Turn off PLS8-X/PLS8-V Using IGT Line The IGT line can be configured for use in two different switching modes: You can set the IGT line to switch on the module only, or to switch it on and off. The switching mode is determined by the parameter "MEShutdown/OnIgnition" of the AT^SCFG command.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 29 of 105 3.3 Power-Up / Power-Down Scenarios 50 3.3.5 Automatic Shutdown Automatic shutdown takes effect if: • The PLS8-X/PLS8-V board is exceeding the critical limits of overtemperature or undertemperature • Undervoltage or overvoltage is detected The automatic shutdown procedure is equivalent to the power down initiated with the AT^SMSO command, i.e.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 30 of 105 3.3 Power-Up / Power-Down Scenarios 50 Table 8: Temperature dependent behavior Automatic shutdown (URC appears no matter whether or not presentation was enabled) ^SCTM_B: 2 Alert: Board equal or beyond overtemperature limit. PLS8-X/PLS8-V switches off. ^SCTM_B: -2 Alert: Board equal or below undertemperature limit. PLS8-X/PLS8-V switches off. The AT^SCTM command can also be used to check the present status of the board.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 31 of 105 3.3 Power-Up / Power-Down Scenarios 50 3.3.5.3 Undervoltage Shutdown If the measured battery voltage is no more sufficient to set up a call the following URC will be presented: ^SBC: Undervoltage. The URC indicates that the module is close to the undervoltage threshold. If undervoltage persists the module keeps sending the URC several times before switching off automatically.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 32 of 105 3.3 Power-Up / Power-Down Scenarios 50 3.3.6 Turn off PLS8-X/PLS8-V in Case of Emergency Caution: Use the EMERG_OFF line only when, due to serious problems, the software is not responding for more than 5 seconds. Pulling the EMERG_OFF line causes the loss of all information stored in the volatile memory. Therefore, this procedure is intended only for use in case of emergency, e.g.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 33 of 105 3.4 Power Saving 50 3.4 Power Saving PLS8-X/PLS8-V is able to reduce its functionality to a minimum (during the so-called SLEEP mode) in order to minimize its current consumption. This behavior is configurable by AT command: • AT^SCFG= "MEopMode/PwrSave": The power save mode is by default disabled.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 34 of 105 3.4 Power Saving 50 3.4.1 Wake-up via RTS0 RTS0 can be used to wake up PLS8-X/PLS8-V from SLEEP mode. Assertion of RTS0 (i.e., toggle from inactive high to active low) serves as wake up event, thus allowing an external application to almost immediately terminate power saving. After RTS0 assertion, the CTS0 line signals module wake up, i.e., readiness of the AT command interface.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 35 of 105 3.5 RTC Backup 50 3.5 RTC Backup The internal Real Time Clock of PLS8-X/PLS8-V is supplied from a separate voltage regulator in the power supply component which is also active when PLS8-X/PLS8-V is in Power Down mode and BATT+ is available. An alarm function is provided that allows to wake up PLS8-X/ PLS8-V. When the alarm time is reached the module wakes up to the functionality level (AT+CFUN) that was valid before power down.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 36 of 105 3.6 USB Interface 50 3.6 USB Interface PLS8-X/PLS8-V supports a USB 2.0 High Speed (480Mbps) device interface. The USB interface is primarily intended for use as command and data interface and for downloading firmware. The USB host is responsible for supplying the VUSB_IN line. This line is for voltage detection only. The USB part (driver and transceiver) is supplied by means of BATT+.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 37 of 105 3.6 USB Interface 50 3.6.1 Reducing Power Consumption (TBD.) While a USB connection is active, the module will never switch into SLEEP mode. Only if the USB interface is in Suspended state or Detached (i.e., VUSB_IN = 0) is the module able to switch into SLEEP mode thereby saving power1.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 38 of 105 3.7 Serial Interface ASC0 50 3.7 Serial Interface ASC0 PLS8-X/PLS8-V offers an 8-wire unbalanced, asynchronous modem interface ASC0 conforming to ITU-T V.24 protocol DCE signalling. The electrical characteristics do not comply with ITUT V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit or inactive state). For electrical characteristics please refer to Table 22.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 39 of 105 3.7 Serial Interface ASC0 50 Table 9: DCE-DTE wiring of ASC0 V.24 circuit DCE DTE Line function Signal direction Line function Signal direction 103 TXD0 Input TXD Output 104 RXD0 Output RXD Input 105 RTS0 Input RTS Output 106 CTS0 Output CTS Input 108/2 DTR0 Input DTR Output 107 DSR0 Output DSR Input 109 DCD0 Output DCD Input 125 RING0 Output RING Input PLS8-X_PLS8-V_HD_v03.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 40 of 105 3.8 UICC/SIM/USIM Interface 50 3.8 UICC/SIM/USIM Interface PLS8-X/PLS8-V has two UICC/SIM/USIM interfaces compatible with the 3GPP 31.102 and ETSI 102 221. These are wired to the host interface in order to be connected to an external SIM card holder. Five pads on the SMT application interface are reserved for each of the two SIM interfaces. The UICC/SIM/USIM interfaces support 3V and 1.8V SIM cards.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 41 of 105 3.8 UICC/SIM/USIM Interface 50 open: Card removed closed: Card inserted SMT application interface CCIN1 Module CCRST1 SIM / UICC 1n CCCLK1 GND CCIO1 CCVCC1 220n Figure 13: First UICC/SIM/USIM interface The total cable length between the SMT application interface pads on PLS8-X/PLS8-V and the pads of the external SIM card holder must not exceed 100mm in order to meet the specifications of 3GPP TS 51.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 42 of 105 3.8 UICC/SIM/USIM Interface 50 3.8.1 Enhanced ESD Protection for SIM Interface To optimize ESD protection for the SIM interfaces it is possible to add ESD diodes to the interface lines of the first and second SIM interface as shown in the example given in Figure 15. The example was designed to meet ESD protection according ETSI EN 301 489-1/7: Contact discharge: ± 4kV, air discharge: ± 8kV.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 43 of 105 3.9 Digital Audio Interface 50 3.9 Digital Audio Interface PLS8-X/PLS8-V has a digital audio interface that can be employed either as pulse code modulation interface (see Section 3.9.1) or as inter IC sound interface (see Section 3.10). Operation can be configured by AT command (see [1]). Default setting is pulse code modulation.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 44 of 105 3.11 Analog-to-Digital Converter (ADC) 50 3.11 Analog-to-Digital Converter (ADC) PLS8-X/PLS8-V provides three unbalanced ADC input lines: ADC1_IN, ADC2_IN and ADC3_IN. They can be used to measure three independent, externally connected DC voltages in the range of 0.3V to 3.075V. The AT^SRADC command can be employed to select the ADC line, set the measurement mode and read out the measurment results. 3.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 45 of 105 3.13 Control Signals 50 3.13 Control Signals 3.13.1 PWR_IND Signal PWR_IND notifies the on/off state of the module. For state detection an external pull-up resistor is required (cp. R1 in below Figure 16). As long as the feeding voltage is applied at the pull-up resistor, a high state of PWR_IND indicates that the module is switched off.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 46 of 105 3.13 Control Signals 50 3.13.3 Remote Wakeup If no call, data or message transfer is in progress, the external host application may shut down its own module interfaces or other components in order to save power. If a call, data, or other request (URC) arrives, the external application can be notified of this event and be woken up again by a state transition of a configurable remote wakeup line.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 47 of 105 3.13 Control Signals 50 3.13.4 Low Current Indicator (LCI) A low current indication is optionally available over a GPIO line. By default, low current indication is disabled and the GPIO pads can be configured and employed as usual. For a GPIO pad to work as a low current indicator the feature has to be enabled by AT command (see [1]: AT^SCFG: MEopMode/PowerMgmt/LCI). By default, the GPIO6 pad is configured as LCI signal.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 48 of 105 3.13 Control Signals 50 3.13.5 Network Connectivity and Technology Status Signals The STATUS line serves to indicate the module’s network connectivity state or the underlying network technology (2G or 3G/4G) and can be used to control an externally connected LED as shown in Figure 18. To operate the LED a buffer, e.g. a transistor or gate, must be included in the external application.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 49 of 105 3.13 Control Signals 50 3.13.6 700MHz Antenna Switch Control To provide for an antenna optimization over a wide frequency range, the GPIO2 (ANT_SWITCH) line can be configured as a control signal for a possible external antenna switch that is able to change between an antenna covering the 700MHz band and an antenna covering all other bands - depending on the frequency band currently being used by the module.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 50 of 105 4 GNSS Receiver 50 4 GNSS Receiver PLS8-X/PLS8-V integrates a GNSS receiver that offers the full performance of GPS/ GLONASS technology. The GNSS receiver is able to continuously track all satellites in view, thus providing accurate satellite position data. The integrated GNSS receiver supports the NMEA protocol via USB or ASC0 interface.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 51 of 105 5 Antenna Interfaces 57 5 Antenna Interfaces 5.1 GSM/UMTS/LTE Antenna Interface The PLS8-X/PLS8-V GSM/UMTS/LTE antenna interface comprises a GSM/UMTS/LTE main antenna as well as a UMTS/LTE Rx diversity/MIMO antenna to improve signal reliability and quality1. The interface has an impedance of 50.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 52 of 105 5.1 GSM/UMTS/LTE Antenna Interface 57 5.1.1 Antenna Installation The antenna is connected by soldering the antenna pads (ANT_MAIN; ANT_DRX_MIMO) and their neighboring ground pads directly to the application’s PCB.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 53 of 105 5.1 GSM/UMTS/LTE Antenna Interface 57 5.1.2 5.1.2.1 RF Line Routing Design Line Arrangement Examples Several dedicated tools are available to calculate line arrangements for specific applications and PCB materials - for example from http://www.polarinstruments.com/ (commercial software) or from http://web.awrcorp.com/Usa/Products/Optional-Products/TX-Line/ (free software).
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 54 of 105 5.1 GSM/UMTS/LTE Antenna Interface 57 Micro-Stripline This section gives two line arrangement examples for micro-stripline. Figure 21: Micro-Stripline line arrangement samples PLS8-X_PLS8-V_HD_v03.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 55 of 105 5.1 GSM/UMTS/LTE Antenna Interface 57 5.1.2.2 Routing Example Interface to RF Connector Figure 22 shows a sample connection of a module‘s antenna pad at the bottom layer of the module PCB with an application PCB‘s coaxial antenna connector. Line impedance depends on line width, but also on other PCB characteristics like dielectric, height and layer gap. The sample stripline width of 0.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 56 of 105 5.2 GNSS Antenna Interface 57 5.2 GNSS Antenna Interface In addition to the RF antenna interface PLS8-X/PLS8-V also has a GNSS antenna interface. See Section 6.5 to find out where the GNSS antenna pad is located. The GNSS pad itself is the same as for the RF antenna interface (see Section 5.1.1). It is possible to connect active or passive GNSS antennas. In either case they must have 50 impedance.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 57 of 105 5.2 GNSS Antenna Interface 57 Figure 25 shows sample circuits realizing ESD protection for a passive GNSS antenna. Module SMT interface VGNSS 100nF Not used ANT_GNSS_DC (Optional) 0R ESD protection Passive GNSS antenna 10nH ANT_GNSS To GNSS receiver Figure 25: ESD protection for passive GNSS antenna PLS8-X_PLS8-V_HD_v03.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 58 of 105 6 Electrical, Reliability and Radio Characteristics 81 6 Electrical, Reliability and Radio Characteristics 6.1 Absolute Maximum Ratings The absolute maximum ratings stated in Table 16 are stress ratings under any conditions. Stresses beyond any of these limits will cause permanent damage to PLS8-X/PLS8-V. Table 16: Absolute maximum ratings Parameter Min Max Unit Supply voltage BATT+ -0.5 +6.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 59 of 105 6.2 Operating Temperatures 81 6.2 Operating Temperatures Table 17: Board temperature Parameter Min Typ Max Unit Operating temperature range Normal temperature range Extreme temperature range +15 -30 +25 +55 +85 °C °C Extended temperature range2 -40 +95 °C Automatic shutdown3 Temperature measured on PLS8-X/PLS8-V board <-40 >+95 °C 1 1. 2. 3.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 60 of 105 6.3 Storage Conditions 81 6.2.1 Temperature Allocation Model The temperature allocation model shown in Table 18 assumes shares of a module’s average lifetime of 10 years (given in %) during which the module is operated at certain temperatures. Table 18: Temperature allocation model Module lifetime share (in %)1 1 1 5 53 35 3 1 1 Module Temperature (in °C) -40 -30 -10 20 40 70 85 95 1.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 61 of 105 6.4 Reliability Characteristics 81 6.4 Reliability Characteristics The test conditions stated below are an extract of the complete test specifications.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 62 of 105 6.4 Reliability Characteristics 81 6.4.1 Bending Tests From experience with other modules an elongation of up to 200µm/m is acceptable for PLS8-X/ PLS8-V modules as a result of bending strains. Tests (based on EN 60068-2-21) showed that if applying a force of 10N at the middle of the module, i.e.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 63 of 105 6.5 Pad Assignment and Signal Description 81 6.5 Pad Assignment and Signal Description The SMT application interface on the PLS8-X/PLS8-V provides connecting pads to integrate the module into external applications. Table 21 lists the pads’ assignments. Figure 28 (bottom view) and Figure 29 (top view) show the connecting pads’ numbering plan.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 64 of 105 6.5 Pad Assignment and Signal Description 81 Table 21: Overview: Pad assignments1 Pad No. Signal Name Pad Signal Name No. Pad No.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 65 of 105 6.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 66 of 105 6.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 67 of 105 6.5 Pad Assignment and Signal Description 81 Please note that the reference voltages listed in Table 22 are the values measured directly on the PLS8-X/PLS8-V module. They do not apply to the accessories connected. Table 22: Signal description Function Signal name IO Power sup- BATT+_RF ply BATT+ I I Power sup- GND ply External VEXT supply voltage O Signal form and level Comment VImax = 4.2V VInorm = 3.8V VImin = 3.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 68 of 105 6.5 Pad Assignment and Signal Description 81 Table 22: Signal description Function Signal name IO Signal form and level Comment RTC backup VDDLP O VOmax = 3.20V while BATT+ =>3.3V RI = 1.8k If unused keep line open. I VI = 1.5V…3.25V at Imax= 10µA while BATT+ = 0V Connectivity status STATUS O VOLmax = 0.45V at I = 2mA VOHmin = 1.35V at I = -2mA VOHmax = 1.85V Status signalling e.g. with ext.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 69 of 105 6.5 Pad Assignment and Signal Description 81 Table 22: Signal description Function Signal name IO Signal form and level Comment 1.8V SIM card interface CCRST1 CCRST2 O VOLmax = 0.45V at I = 2mA VOHmin = 1.35V at I = -2mA VOHmax = 1.85V CCIO1 CCIO2 I/O RI 4.8...9.5k VILmax = 0.62V VILmin = -0.3V VIHmin = 1.20V VIHmax = 2.1V Maximum cable length or copper track should be not longer than 100mm to SIM card holder.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 70 of 105 6.5 Pad Assignment and Signal Description 81 Table 22: Signal description Function Signal name IO Signal form and level Comment USB VUSB_IN VINmin = 3.0V VINmax = 5.25V If the USB interface is not used please connect this line to GND. I IItyp = 150µA IImax = 200µA Cin=1µF In case of Vripple > 10mVpp (with f>300kHz), and VBUS_IN driven in the voltage range 4.08V...4.11V, use of an RC filter 1k/100nF is required.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 71 of 105 6.5 Pad Assignment and Signal Description 81 Table 22: Signal description Function Signal name IO Signal form and level Comment Low Current Indication GPIOx O VOLmax = 0.45V at I = 2mA VOHmin = 1.35V at I = -2mA VOHmax = 1.85V If the feature is enabled (see Section 3.13.4). I VIHmax = 2V RPD= appr. 100k If the feature is disabled (see Section 3.13.4). Remote host wakeup GPIOx O VOLmax = 0.45V at I = 2mA VOHmin = 1.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 72 of 105 6.6 Power Supply Ratings 81 6.6 Power Supply Ratings Table 23 and Table 24 assemble various voltage supply and current consumption ratings of the module. Table 23: Voltage supply ratings Description BATT+ Supply voltage Conditions Min Typ Directly measured at Module. 3.3 Voltage must stay within the min/max values, including voltage drop, ripple, spikes 3.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 73 of 105 6.6 Power Supply Ratings 81 Table 24: Current consumption ratings1 Description IBATT+ 2 EDGE Data transfer Average GSM / GPRS supply cur- GSM850/900; PCL=5; 1Tx/ 4Rx rent (GNSS off) Peak current during GSM transmit burst IBATT+ 2 Conditions Typical rating Unit ROPR=8 (max. reduction) 220 mA EDGE Data transfer ROPR=8 GSM850/900; PCL=5; 2Tx/ (max.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 74 of 105 6.6 Power Supply Ratings 81 Table 24: Current consumption ratings1 Description IBATT+ 2 Average UMTS supply current (GNSS off) Conditions 3 SLEEP @ DRX=9 USB disconnected 1.8 mA USB disconnected 2.1 mA SLEEP @ DRX=6 USB disconnected 3.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 75 of 105 6.6 Power Supply Ratings 81 Table 24: Current consumption ratings1 Description IBATT+ 2 Conditions Typical rating Unit Average LTE / LTE active (UART / USB active); @DRX=6 & GNSS supply cur- GNSS NMEA output off rent (GNSS on) LTE active (UART / USB active); @DRX=6 & GNSS NMEA output on4 65 mA 85 mA IVUSB_IN USB typical and maximum ratings are mentioned in Table 22: VUSB_IN. 1. 2. 3. 4. 5.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 76 of 105 6.7 RF Antenna Interface Characteristics 81 6.7 RF Antenna Interface Characteristics Table 25: RF Antenna interface GSM / UMTS/LTE (at operating temperature range1)2 Parameter LTE connectivity Conditions 3 Receiver Input Sensitivity @ ARP (ch. bandwidth 5MHz) RF Power @ ARP with 50 Load Min. Typical Max. Unit LTE 700 Band 17 -97 -102 dBm LTE 700 Band 13 TBD. TBD.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 77 of 105 6.7 RF Antenna Interface Characteristics 81 Table 25: RF Antenna interface GSM / UMTS/LTE (at operating temperature range1)2 Parameter RF Power @ ARP with 50 Load (ROPR=4, i.e.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 78 of 105 6.7 RF Antenna Interface Characteristics 81 Table 25: RF Antenna interface GSM / UMTS/LTE (at operating temperature range1)2 Parameter RF Power @ ARP with 50 Load (ROPR=6) Conditions GPRS, 1 TX EDGE, 1 TX GPRS, 2 TX EDGE, 2 TX GPRS, 3 TX EDGE, 3 TX GPRS, 4 TX EDGE, 4 TX RF Power @ ARP with 50 Load (ROPR=7) GPRS, 1 TX EDGE, 1 TX GPRS, 2 TX EDGE, 2 TX GPRS, 3 TX EDGE, 3 TX GPRS, 4 TX EDGE, 4 TX Min. Typical Max.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 79 of 105 6.7 RF Antenna Interface Characteristics 81 Table 25: RF Antenna interface GSM / UMTS/LTE (at operating temperature range1)2 Parameter RF Power @ ARP with 50 Load (ROPR=8, i.e., max. reduction) Conditions GPRS, 1 TX EDGE, 1 TX GPRS, 2 TX EDGE, 2 TX GPRS, 3 TX EDGE, 3 TX GPRS, 4 TX EDGE, 4 TX 1. 2. 3. Min. Typical Max.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 80 of 105 6.8 GNSS Interface Characteristics 81 6.8 GNSS Interface Characteristics The following tables list general characteristics of the GNSS interface. Table 26: GNSS properties Parameter Conditions Frequency GPS GLONASS Tracking Sensitivity Acquisition Sensitivity Min. 1. 2. 3. 4. Unit 1575.42 MHz 1597.551 1605.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 81 of 105 6.9 Electrostatic Discharge 81 6.9 Electrostatic Discharge The module is not protected against Electrostatic Discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates a PLS8-X/PLS8-V module.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 82 of 105 7 Mechanics, Mounting and Packaging 94 7 Mechanics, Mounting and Packaging 7.1 Mechanical Dimensions of PLS8-X/PLS8-V Figure 30 shows a 3D view1 of PLS8-X/PLS8-V and provides an overview of the board's mechanical dimensions. For further details see Figure 31. Length: 33mm Width: 29mm Height: 2.95mm Top view Bottom view Figure 30: PLS8-X/PLS8-V – top and bottom view 1.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 83 of 105 7.1 Mechanical Dimensions of PLS8-X/PLS8-V 94 Internal use; Not to be soldered Figure 31: Dimensions of PLS8-X/PLS8-V (all dimensions in mm) PLS8-X_PLS8-V_HD_v03.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 84 of 105 7.2 Mounting PLS8-X/PLS8-V onto the Application Platform 94 7.2 Mounting PLS8-X/PLS8-V onto the Application Platform This section describes how to mount PLS8-X/PLS8-V onto the PCBs, including land pattern and stencil design, board-level characterization, soldering conditions, durability and mechanical handling. For more information on issues related to SMT module integration see also [3].
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 85 of 105 7.2 Mounting PLS8-X/PLS8-V onto the Application Platform 94 The stencil design illustrated in Figure 33 and Figure 34 is recommended by Gemalto M2M as a result of extensive tests with Gemalto M2M Daisy Chain modules. Figure 33: Recommended design for 110 micron thick stencil (top layer) Figure 34: Recommended design for 150 micron thick stencil (top layer) PLS8-X_PLS8-V_HD_v03.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 86 of 105 7.2 Mounting PLS8-X/PLS8-V onto the Application Platform 94 7.2.1.2 Board Level Characterization Board level characterization issues should also be taken into account if devising an SMT process. Characterization tests should attempt to optimize the SMT process with regard to board level reliability.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 87 of 105 7.2 Mounting PLS8-X/PLS8-V onto the Application Platform 94 7.2.3 7.2.3.1 Soldering Conditions and Temperature Reflow Profile Figure 35: Reflow Profile Table 29: Reflow temperature ratings1 Profile Feature Pb-Free Assembly Preheat & Soak Temperature Minimum (TSmin) Temperature Maximum (TSmax) Time (tSmin to tSmax) (tS) 150°C 200°C 60-120 seconds Average ramp up rate (TSmax to TP) 3K/second max.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 88 of 105 7.2 Mounting PLS8-X/PLS8-V onto the Application Platform 94 7.2.3.2 Maximum Temperature and Duration The following limits are recommended for the SMT board-level soldering process to attach the module: • A maximum module temperature of 245°C. This specifies the temperature as measured at the module’s top side. • A maximum duration of 30 seconds at this temperature.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 89 of 105 7.2 Mounting PLS8-X/PLS8-V onto the Application Platform 94 7.2.4 7.2.4.1 Durability and Mechanical Handling Storage Life PLS8-X/PLS8-V modules, as delivered in tape and reel carriers, must be stored in sealed, moisture barrier anti-static bags. The shelf life in a sealed moisture bag is an estimated 12 months.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 90 of 105 7.3 Packaging 94 7.3 Packaging 7.3.1 Tape and Reel The single-feed tape carrier for PLS8-X/PLS8-V is illustrated in Figure 36. The figure also shows the proper part orientation. The tape width is 44mm and the PLS8-X/PLS8-V modules are placed on the tape with a 40mm pitch. The reels are 330mm in diameter with 100mm hubs. Each reel contains 500 modules. 7.3.1.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 91 of 105 7.3 Packaging 94 7.3.1.2 Barcode Label A barcode label provides detailed information on the tape and its contents. It is attached to the reel. Barcode label Figure 38: Barcode label on tape reel PLS8-X_PLS8-V_HD_v03.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 92 of 105 7.3 Packaging 94 7.3.2 Shipping Materials PLS8-X/PLS8-V is distributed in tape and reel carriers. The tape and reel carriers used to distribute PLS8-X/PLS8-V are packed as described below, including the following required shipping materials: • Moisture barrier bag, including desiccant and humidity indicator card • Transportation bag 7.3.2.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 93 of 105 7.3 Packaging 94 Figure 40: Moisture Sensitivity Label PLS8-X_PLS8-V_HD_v03.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 94 of 105 7.3 Packaging 94 MBBs contain one or more desiccant pouches to absorb moisture that may be in the bag. The humidity indicator card described below should be used to determine whether the enclosed components have absorbed an excessive amount of moisture. The desiccant pouches should not be baked or reused once removed from the MBB.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 95 of 105 8 Sample Application 97 8 Sample Application Figure 42 shows a typical example of how to integrate an PLS8-X/PLS8-V module with an application. The PWR_IND line is an open collector that needs an external pull-up resistor which connects to the voltage supply VCC µC of the microcontroller.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 96 of 105 8 Sample Application 97 PLS8x Current limiter <60mA VGNSS VDDLP 10µF ** See Section 3.8.1 for details on enhanced ESD protection Figure 42: PLS8-X/PLS8-V sample application PLS8-X_PLS8-V_HD_v03.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 97 of 105 8.1 Sample Level Conversion Circuit 97 8.1 Sample Level Conversion Circuit Depending on the micro controller used by an external application PLS8-X/PLS8-V‘s digital input and output lines (i.e., ASC0 lines) may require level conversion. The following Figure 43 shows a sample circuit with recommended level shifters for an external application‘s micro controller (with VLOGIC between 3.0V...3.6V).
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 98 of 105 9 Reference Approval 100 9 Reference Approval 9.1 Reference Equipment for Type Approval The Gemalto M2M reference setup submitted to type approve PLS8-X/PLS8-V is shown in Figure 44. The module (i.e., the evaluation module) is connected to the DSB75 by means of a flex cable and a special DSB75 adapter. The GSM/UMTS/LTE test equipment is connected via edge mount SMA connectors soldered to the module’s antenna pads.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 99 of 105 9.2 Compliance with FCC and IC Rules and Regulations 100 9.2 Compliance with FCC and IC Rules and Regulations The Equipment Authorization Certification for the Gemalto M2M modules reference application described in Section 9.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 100 of 105 9.2 Compliance with FCC and IC Rules and Regulations 100 Note: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules and with Industry Canada licence-exempt RSS standard(s). These limits are designed to provide reasonable protection against harmful interference in a residential installation.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 101 of 105 10 Appendix 104 10 Appendix 10.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 102 of 105 10.1 List of Parts and Accessories 104 Table 32: Molex sales contacts (subject to change) Molex For further information please click: http://www.molex.com Molex Deutschland GmbH Otto-Hahn-Str. 1b 69190 Walldorf Germany Phone: +49-6227-3091-0 Fax: +49-6227-3091-8100 Email: mxgermany@molex.com American Headquarters Lisle, Illinois 60532 U.S.A.
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 103 of 105 10.2 Mounting Advice Sheet 104 10.2 Mounting Advice Sheet To prevent mechanical damage, be careful not to force, bend or twist the module. Be sure it is soldered flat against the host device (see also Section 7.2). The advice sheet on the next page shows a number of examples for the kind of bending that may lead to mechanical damage of the module (the module as part of an external application is integrated into a housing).
Cinterion® PLS8-X/PLS8-V Hardware Interface Description Page 104 of 105 10.2 Mounting Advice Sheet 104 PLS8-X_PLS8-V_HD_v03.
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