Specifications

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About This Guide

This document provides the specifications for the ESP01 module.

The document structure is as follows:

Chapter

Title

Subject

Chapter 1

Preface

An overview of ESP01

Chapter 2

Pin Definitions

Device pinout and pin descriptions

Chapter 3

Functional Description

Description of major functional modules

Chapter 4

Peripherals and Sensors

Description of peripherals

Chapter 5

Electrical Characteristics

Electrical characteristics and specifications of ESP01

Release Notes

Date

Version

Release notes

2017.10

V1.0

First release.

Documentation Change Notification

Certification

Disclaimer and Copyright Notice

Summary of content (17 pages)

PAGE 1
About This Guide This document provides the specifications for the ESP01 module.
PAGE 2
1 . OVERVIEW 1. Overview ESP01 is a powerful, generic Wi-Fi MCU module that targets a wide variety of applications, ranging from low-power sensor networks to the most demanding tasks, such as voice encoding, music streaming and MP3 decoding. ESP01 integrates a U.FL connector. At the core of this module is the ESP32-D0WD chip*. The chip embedded is designed to be scalable and adaptive.
PAGE 3
1 . OVERVIEW Categories Items Specifications SD card, UART, SPI, SDIO, I2C, LED PWM, Motor Module interface PWM, I2S, IR GPIO, capacitive touch sensor, ADC, DAC, LNA preamplifier Hardware On-chip sensor Hall sensor, temperature sensor On-board clock 40 MHz crystal Operating voltage/Power supply 2.7 ~ 3.
PAGE 4
2 . PIN DEFINITIONS 2. Pin Definitions 2.1 Pin Layout Keepout Zone GND 38 1 GND 2 3V3 IO23 37 3 EN IO22 36 4 SENSOR_VP TXD0 35 5 SENSOR_VN RXD0 34 6 IO34 IO21 33 7 IO35 NC 32 8 IO32 IO19 31 9 IO33 IO18 30 10 IO25 IO5 29 11 IO26 IO17 28 12 IO27 IO16 27 13 IO14 IO4 26 14 IO12 IO0 25 GND IO13 SD2 SD3 CMD CLK SD0 SD1 IO15 IO2 15 16 17 18 19 20 21 22 23 24 39: GND Figure 1: ESP01 Pin layout 2.2 Pin Description ESP01 has 38 pins.
PAGE 5
2 . PIN DEFINITIONS Name No.
PAGE 6
2 . PIN DEFINITIONS 2.3 Strapping Pins Please refer to ESP01 schematics. ESP32 has five strapping pins, which can be seen in Chapter 6 Schematics: • MTDI • GPIO0 • GPIO2 • MTDO • GPIO5 Software can read the value of these five bits from the register ”GPIO_STRAPPING”.
PAGE 7
3 . FUNCTIONAL DESCRIPTION 3. Functional Description This chapter describes the modules and functions integrated in ESP01. 3.1 CPU and Internal Memory ESP32-D0WD contains two low-power Xtensa® 32-bit LX6 microprocessors. The internal memory includes: • 448 kB of ROM for booting and core functions. • 520 kB (8 kB RTC FAST Memory included) of on-chip SRAM for data and instruction.
PAGE 8
3 . FUNCTIONAL DESCRIPTION 3.4 RTC and Low-Power Management With the use of advanced power management technologies, ESP32 can switch between different power modes (see Table 5). • Power modes – Active mode: The chip radio is powered on. The chip can receive, transmit, or listen. – Modem-sleep mode: The CPU is operational and the clock is configurable. The Wi-Fi base- band and radio are disabled. – Light-sleep mode: The CPU is paused.
PAGE 9
3 . FUNCTIONAL DESCRIPTION Power mode Description Power consumption Max speed 240 MHz: 30 mA ~ 50 mA Modem-sleep The CPU is powered on. Normal speed 80 MHz: 20 mA ~ 25 mA Slow speed 2 MHz: 2 mA ~ 4 mA Light-sleep - 0.8 mA The ULP co-processor is powered on. 150 µA ULP sensor-monitored pattern 100 µA @1% duty RTC timer + RTC memory 10 µA Hibernation RTC timer only 5 µA Power off CHIP_PU is set to low level, the chip is powered off 0.
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4 . PERIPHERALS AND SENSORS 4. Peripherals and Sensors 4.
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4 . PERIPHERALS AND SENSORS Interface Signal Pin Function PWM0_OUT0~2 PWM1_OUT_IN0~2 Three channels of 16-bit timers generate PWM0_FLT_IN0~2 Motor PWM PWM1_FLT_IN0~2 PWM0_CAP_IN0~2 PWM waveforms. Each channel has a pair Any GPIOs* of output signals, three fault detection signals, three event-capture signals, and PWM1_CAP_IN0~2 three sync signals. PWM0_SYNC_IN0~2 PWM1_SYNC_IN0~2 LED PWM ledc_hs_sig_out0~7 ledc_ls_sig_out0~7 Any GPIOs* 16 independent channels @80 MHz clock/RTC CLK.
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4 .
PAGE 13
4 . PERIPHERALS AND SENSORS Interface Parallel QSPI Signal Pin SPIHD SHD/SD2 SPIWP SWP/SD3 SPICS0 SCS/CMD SPICLK SCK/CLK SPIQ SDO/SD0 SPID SDI/SD1 HSPICLK IO14 HSPICS0 IO15 HSPIQ IO12 HSPID IO13 HSPIHD IO4 HSPIWP IO2 VSPICLK IO18 VSPICS0 IO5 VSPIQ IO19 VSPID IO23 VSPIHD IO21 VSPIWP IO22 SPI Quad SPI that can be connected to the external flash and SRAM Standard SPI consists of clock, HSPID_in/_out chip-select, MOSI and MISO.
PAGE 14
4 .
PAGE 15
5. Electrical Characteristics 5.1 Absolute Maximum Ratings Table 8: Absolute Maximum Ratings Parameter Symbol Min Typ Max Unit Power supply VDD 2.7 3.3 3.6 V IV DD 0.5 - - A Input low voltage VIL -0.3 - 0.25×VIO1 V Input high voltage VIH 0.75×VIO - VIO +0.3 V Input leakage current IIL - - 50 nA Input pin capacitance Cpad - - 2 Output low voltage VOL - - 0.1×VIO Output high voltage VOH 0.
PAGE 16
FCC Statement: Please take attention that changes or modification not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.
PAGE 17
(4) Installation Notice to Host Product Manufacturer The OEM integrator is responsible for ensuring that the end-user has no manual instruction to remove or install module. The module is limited to installation in mobile application, a separate approval is required for all other operating configurations, including portable configurations with respect to §2.1093 and difference antenna configurations.