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WG7833-B0

WLAN/BT Module

TI WiLink8 IEEE 802.11a/b/g/n

BT/BLE Solution

Datasheet

Revision 0.3

Summary of content (54 pages)

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Doc No: WG7833-B0-DTS-R03 Index 1. 2. OVERVIEW ................................................................................................................................... 4 1.1. MODELS FUNCTIONAL BLOCKS ................................................................................................ 4 1.2. GENERAL FEATURES ................................................................................................................. 4 FUNCTIONAL FEATURES .....................................
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Doc No: WG7833-B0-DTS-R03 4.3.10. BT EDR Transceiver - Spurs ..................................................................................... 25 4.4. BT LE RF PERFORMANCE ........................................................................................................... 26 4.4.1. BT LE Receiver Characteristics, In-Band Signals ....................................................... 26 4.4.3. BT LE Transmitter Characteristics ......................................................................
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Doc No: WG7833-B0-DTS-R03 11. HISTORY CHANGE ............................................................................................................... 50 Copyright © JORJIN TECHNOLOGIES INC. 2015 http://WWW.JORJIN.COM.
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Doc No: WG7833-B0-DTS-R03 1. OVERVIEW WG7833/31/03/01-B0, a WiFi, BT, BLE SiP (system in package) module, is the most demanded design for mobile devices, Audio, Computer, PDA and embedded system applications with Wilink8 solution from TI. 1.1. Models Functional Blocks Model WLAN 2.4GHz WG7833-B0 V WLAN 5GHz V BT/BLE/ANT V 1.2.
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Doc No: WG7833-B0-DTS-R03 2. FUNCTIONAL FEATURES 2.1. Module Block Diagram WiLink8 VBAT_IN Power Management VIO_IN (5G only for WG7833/03-B0) 32.768KHz WL 5G TX SLOW CLK WL 5G RX OSC CLK_REQ_OUT SW BPF SW BPF WLAN 26MHz WLAN 2.4G FAST CLK TCXO BT WLAN I/F: SDIO BT (BT only for WG7833/31-B0) BT I/F: UART, PCM, I2S GPIO’s, Debug WG7833-B0 Figure 2-1. WG7833-B0 Block Diagram 2.2. Block Functional Feature 2.2.1. WLAN Features Integrated 2.
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Doc No: WG7833-B0-DTS-R03 Baseband Processor IEEE Std 802.11a/b/g/n data rates and IEEE Std 802.11n data rates with 20 or 40 MHz SISO. Fully calibrated system. Production calibration not required. Medium Access Controller (MAC) Embedded ARM™ Central Processing Unit (CPU) Hardware-Based Encryption/Decryption using 64-, 128-, and 256-Bit WEP, TKIP or AES Keys, Supports requirements for Wi-Fi Protected Access (WPA and WPA2.0) and IEEE Std 802.
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Doc No: WG7833-B0-DTS-R03 affecting BR/EDR performance 2.2.4. ANT Features Fully compliant with all ANT Protocols: ANT solution optimized for the fitness and health use-cases Simple to complex network topologies Supports high-resolution proximity pairing The ANT protocol has been designed to very power-efficient, yet is flexible enough to support various network topologies (point-to-point, star, 1-to-N, N-to-1) and data transfer modes (broadcast, broadcast with acknowledge, mass data transfer).
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Doc No: WG7833-B0-DTS-R03 3.2. Pin Description Table 3-1. Pin Description Pin No. A1 Shut Signal Name GND After Type Down Power state Up(1) Voltage Level GND Description Ground WLAN SDIO Data bit 3. Changes state to A2 WLAN_SDIO_D3 IO HiZ PU 1.8V PU at WL_EN or BT_EN assertion for card detects. Later disabled by software during initialization. (2) A3 WLAN_SDIO_CMD I/O HiZ HiZ 1.8V WLAN SDIO Command (2) A4 WLAN_SDIO_D2 IO HiZ HiZ 1.
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Doc No: WG7833-B0-DTS-R03 A19 VIO_IN POW A20 GND GND PD PD 1.8V Connect to 1.8V external VIO Ground B1 NC NC B2 NC NC B3 GPIO11 I/O PU PU 1.8V Reserved for future use. NC if not used. B4 GPIO9 I/O PU PU 1.8V Reserved for future use. NC if not used. B5 GPIO10 I/O PU PU 1.8V Reserved for future use. NC if not used. B6 GPIO12 I/O PU PU 1.8V Reserved for future use. NC if not used.
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Doc No: WG7833-B0-DTS-R03 C13 GND GND Ground C14 GND GND Ground C15 GND GND Ground C16 GND GND Ground D1 GND GND Ground D2 VBAT POW D3 NC NC D4 NC NC D5 NC NC D6 GND D7 NC D8 GND GND Ground D9 PA_DC2DC_OUT POW Internal DC2DC output VBAT GND Power supply input, 2.9 to 4.8 V Ground NC D10 GPIO4 I/O PD PD 1.8V D11 GPIO2 I/O PD PD 1.8V D12 BT_EN In PD PD 1.8V Reserved for future use. NC if not used.
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Doc No: WG7833-B0-DTS-R03 J3 GND GND Ground J4 NC NC J5 NC NC J6 NC NC J7 NC NC J8 NC NC J9 NC NC J10 CLK_REQ_OUT OUT J11 GND GND Ground J12 GND GND Ground J13 NC K1 GND K2 RF_ANT_BG K3 GND GND Ground K4 GND GND Ground K5 GND GND Ground K6 GND GND Ground K7 BT_AUD_OUT OUT K8 GND GND Ground K9 EXT_32K ANA Input Sleep clock: 32.768 KHz GND Ground PD PD 1.8V TCXO clock request out NC GND Ground RF K10 GND WLAN/BT 2.
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Doc No: WG7833-B0-DTS-R03 4. MODULE SPECIFICATION 4.1. General Module Requirements and Operation 4.1.1. Absolute Maximum Ratings (1) Parameter Value (2) Units VBAT -0.5 to 5.5 VIO -0.5 to 2.1 V Input voltage to Analog pins -0.5 to 2.1 V Input voltage limits (CLK_IN) -0.5 to VDD_IO V Input voltage to all other pins -0.5 to (VDD_IO + 0.
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Doc No: WG7833-B0-DTS-R03 4.1.2. Recommended Operating Conditions Parameter VBAT Condition (1) Sym DC supply range Min Max 2.9 4.8 1.62 1.95 Units V for all modes 1.8 V IO ring power supply voltage IO high-level input voltage VIH 0.65 x VDD_IO VDD_IO IO low-level input voltage VIL 0 0.35 x VDD_IO Enable inputs high-level input VIH_EN 1.365 VDD_IO VIL_EN 0 0.4 VOH VDD_IO -0.45 VDD_IO @ 1 mA VDD_IO -0.112 VDD_IO @ 0.3 mA VDD_IO -0.033 VDD_IO 0 0.45 @ 1 mA 0 0.112 @ 0.
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Doc No: WG7833-B0-DTS-R03 4.1.3. External Slow Clock Input (SLOW_CLK) The supported digital slow clock is 32.768 kHz digital (square wave). Parameter Condition Sym Min. Input slow clock Frequency Typ. Max. Units 32.768 KHz Input slow clock accuracy WLAN, BT +/-250 (Initial + temp + aging) ANT +/- 50 ppm Input Transition time Tr/Tf Tr/Tf - 100 ns 85 % 10% to 90% Frequency input duty Cycle 15 Input Voltage Limits 50 0.65x Vih VDD_IO VDD_IO Square Wave, Vpeak DC-coupled 0.
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Doc No: WG7833-B0-DTS-R03 Phase noise 5GHz for Measured at 1 KHz offset -128.4 dBc/Hz 26MHz, 20/40 MHz Measured at 10 KHz offset -145.4 dBc/Hz SISO Measured at 100 KHz offset -148.4 dBc/Hz (1) Power-up time is calculated from the time CLK_REQ_OUT asserted till the time the TCXO_CLK amplitude is within voltage limit specified above and TCXO_CLK frequency is within 0.1 ppm of final steady state frequency. Copyright © JORJIN TECHNOLOGIES INC. 2015 http://WWW.JORJIN.COM.
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Doc No: WG7833-B0-DTS-R03 4.2. WLAN RF Performance 4.2.1. WLAN 2.4-GHz Receiver Characteristics Parameter Condition Operation frequency range Sensitivity Min Typ 2412 Max Units 2484 MHz dBm 1 Mbps DSSS -96.3 -93.4 2 Mbps DSSS -93.2 -90.5 20MHz Bandwidth 5.5 Mbps CCK -90.6 -87.9 At < 10% PER limit 11 Mbps CCK -87.9 -85.7 6 Mbps OFDM -92 -89.2 9 Mbps OFDM -90.4 -87.7 12 Mbps OFDM -89.5 -86.8 18 Mbps OFDM -87.2 -84.5 24 Mbps OFDM -84.1 -81.4 36 Mbps OFDM -80.
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Doc No: WG7833-B0-DTS-R03 4.2.2. WLAN 2.4-GHz Transmitter Power Parameter Condition Min Typ Max Output Power 1 Mbps DSSS 15 17 – - Maximum RMS output power 2 Mbps DSSS 15 17 – measured at 1dB from IEEE 5.5 Mbps CCK 15 17 – spectral mask or EVM 11 Mbps CCK 15 17 – 6 Mbps OFDM 15 17 – 9 Mbps OFDM 15 17 – 12 Mbps OFDM 15 17 – 18 Mbps OFDM 15 17 – 24 MbpS OFDM 14 16.2 – 36 Mbps OFDM 13.1 15.3 – 48 Mbps OFDM 12.4 14.6 – 54 Mbps OFDM 11.8 13.
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Doc No: WG7833-B0-DTS-R03 4.2.3. WLAN 5-GHz Receiver Characteristics (For WG7833/03 Only) Parameter Condition Operation frequency range Min Typ 4910 Max Units 5825 MHz Sensitivity 6 Mbps OFDM – -91.5 -87.6 - 20MHz bandwidth. 9 Mbps OFDM – -89.7 -85.7 - At < 10% PER limit 12 Mbps OFDM – -88.9 -84.9 18 Mbps OFDM – -86.4 -82.4 24 Mbps OFDM – -83.3 -79.3 36 Mbps OFDM – -79.9 -75.9 48 Mbps OFDM – -75.6 -71.6 54 Mbps OFDM – -74.0 -70.5 MCS0 MM 4K – -89.8 -85.
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Doc No: WG7833-B0-DTS-R03 4.2.4. WLAN 5-GHz Transmitter Power (For WG7833/03 Only) Parameter Condition Min Typ Max Output Power 6 Mbps OFDM 14.7 16.8 – - Maximum RMS output power 9 Mbps OFDM 14.7 16.8 – measured at 1dB from IEEE 12 Mbps OFDM 14.7 16.8 – spectral mask or EVM 18 Mbps OFDM 14.7 16.8 – 24 MbpS OFDM 14.1 15.7 – 36 Mbps OFDM 13.4 15.0 – 48 Mbps OFDM 12.6 14.2 – 54 Mbps OFDM 11.6 13.4 – MCS0 MM 14.4 16.4 MCS1 MM 14.4 16.4 MCS2 MM 14.4 16.
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Doc No: WG7833-B0-DTS-R03 4.3. Bluetooth RF Performance (For WG7833/31 Only) 4.3.1. BT Receiver Characteristics, In-Band Signals Parameter Condition Min Typ Max BT Units Spec BT BR, EDR operation 2402 2480 MHz frequency range BT BR, EDR channel spacing 1 MHz BT BR, EDR input 50 Ω impedance BT BR, EDR sensitivity (1) Dirty TX on BR, BER = 0.1% -92.0 -70 EDR2, BER = 0.01% -91.5 -70 EDR3, BER = 0.01% -84.
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Doc No: WG7833-B0-DTS-R03 BR, adjacent ≥Ι±3Ι MHz -45.0 -40 EDR, adjacent ≥Ι±3Ι EDR2 -45.0 -40 MHz EDR3 -44.0 -33 BT BR, EDR RF return loss -10.0 dB (1) Sensitivity degradation up to -3dB may occur due to fast clock harmonics with dirty TX on. 4.3.2. BT Receiver Characteristics – General Blocking Condition Parameter Blocking performance over full range, according to BT specification (1) Min Typ BT spec 30-2000 MHz -6 -10 2000-2399 MHz -6 -27 2484-3000 MHz -6 -27 3-12.
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Doc No: WG7833-B0-DTS-R03 4.3.4. BT Transmitter, BR Parameter BR RF output power Min (1) Typ VBAT >= 3V 12.5 VBAT < 3V 7.0 BR Gain Control Range Max BT Spec dBm 30 BR Power Control Step 2 Units dB 8 5 2 to 8 BR Adjacent Channel Power |M-N| = 2 (2) -43.0 ≤ -20 BR Adjacent Channel Power |M-N| > 2 (2) -48.0 ≤ -40 dBm 1) Values reflect maximum power. Reduced power is available using a vendor-specific (VS) command. 2) Assumes 3dB insertion loss on external filter and traces 4.3.
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Doc No: WG7833-B0-DTS-R03 BR carrier frequency One slot packet -25 +25 < ±25 kHz drift Three and five slot packet -35 35 < ±40 kHz 15 < 20 kHz/ BR drift rate lfk+5 – fkl , k = 0 …. max 50μs BR initial carrier frequency tolerance (2) f0 – fTX -25 25 < ±75 kHz 1) Performance figures at maximum power 2) This number is added on top of the reference clock frequency accuracy 4.3.7.
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Doc No: WG7833-B0-DTS-R03 BR -134 dBm/Hz EDR -129 dBm/Hz 2nd harmonic 1.5 dBm 3rd harmonic -4 dBm 4th harmonic -10 dBm 2110-2170 MHz BT harmonics (WCDMA) 1) Meets FCC and ETSI requirements with suitable external filter 2) Performance figures at maximum power 3) Except for frequencies that corresponds to 2*RF_FREQ/3 4.3.9.
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Doc No: WG7833-B0-DTS-R03 1598-1607 MHz (GLONASS) (3) -78 dBm 1805-1880 MHz (DCS, WCDMA) -76 dBm 1930-1990 MHz (PCS) -74 dBm 2110-2170 MHz (WCDMA) -63 dBm 1) Meets FCC and ETSI requirements with suitable external filter 2) Performance figures at maximum power 3) Except for frequencies that corresponds to 2*RF_FREQ/3 4.4. BT LE RF Performance 4.4.1.
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Doc No: WG7833-B0-DTS-R03 -15 3–12.75GHz ≥ –30 1) Exceptions taken out of the total 10 allowed for fbf_1, according to the BT LE Spec 4.4.3. BT LE Transmitter Characteristics Parameter Min Typ Max BT LE Unit Spec BT LE RF output power (1) Vbat >= 3V 12.5 ≤10 dBm Vbat < 3V 870 ≤10 dBm dBm BT LE Adjacent Channel Power |M-N| = 2 (2) -51.0 ≤ –20 BT LE Adjacent Channel Power |M-N| > 2 (2) -54.0 ≤ –30 1) To reduce the maximum BLE power, use a VS command.
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Doc No: WG7833-B0-DTS-R03 4.4.5. BT LE Transceiver – Emissions See Section 4.3.8, BT BR, EDR Transceiver – Emissions. 4.4.6. BT LE Transceiver - Spurs See Section 4.3.9, BT BR Transceiver – Spurs. 4.5. ANT Performance 4.5.1. ANT Receiver Characteristics, In-Band Signals Parameter Condition ANT Operation frequency range Min 2402 ANT Channel spacing ANT Sensitivity Typ 12.72% PER (1) Max Units 2480 MHz 1 MHz -85 dBm 1) Translation from BER=0.
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Doc No: WG7833-B0-DTS-R03 4.6. POWER CONSUMPTION 4.6.1. Shutdown and Sleep Currents Parameter Power Supply Current Typ Unit uA Shutdown mode VBAT 10 All functions shut down. VIO 2 WLAN sleep mode VBAT 154 BT sleep mode VBAT 110 4.6.2. WLAN Power Currents Parameter LPM Receiver Transmitter Conditions Typ (avg) - 25C Units 2.4GHz RX LPM 43 mA 2.4GHz RX search SISO20 48 mA 2.4GHz RX search SISO40 53 mA 5GHz RX search SISO20 54 mA 5GHz RX search SISO40 58 mA 2.
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Doc No: WG7833-B0-DTS-R03 4.6.3. Bluetooth Currents Current measurements are done at the following output power: BR at 12.5dBm, EDR at 7dBm. Use Case (1) Typ Units BR Voice HV3 + sniff 11.6 mA EDR Voice 2-EV3 no retrans. + sniff 5.9 mA Sniff 1 attempt 1.28s 178 uA EDR A2DP EDR2 (master). SBC high quality – 345Kbs 10.4 mA EDR A2DP EDR2 (master). MP3 high quality – 192Kbs 7.5 mA (2) (3) 18 mA (3) 50 mA 33 mA Page or inquiry 1.28s/11.25ms 253 uA P&I Scan (P=1.28/I=2.
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Doc No: WG7833-B0-DTS-R03 4.6.5. ANT Currents Use Case Conditions Typ Units ANT Rx message mode 250ms interval 360 uA ANT Rx message mode 500ms interval 220 uA ANT Rx message mode 1000ms interval 150 uA Copyright © JORJIN TECHNOLOGIES INC. 2015 http://WWW.JORJIN.COM.
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Doc No: WG7833-B0-DTS-R03 5. HOST INTERFACE TIMING CHARACTERISTICS The following table summarizes the Host Controller interface options. All interfaces operate independently. WLAN Shared HCI for all functional BT Voice/Audio blocks except WLAN WLAN HS SDIO Over UART BT PCM The device incorporates UART module dedicated to the BT shared-transport Host Controller Interface (HCI) transport layer.
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Doc No: WG7833-B0-DTS-R03 5.2. SDIO Timing Specifications 5.2.1. SDIO Switching Characteristics – Default Rate Figure 5-1. SDIO default input timing Figure 5-2. SDIO default output timing Table 5-1. SDIO Default Timing Characteristics(1) PARAMETER(2) MIN MAX UNIT Fclock Clock frequency, CLK 0 26 MHz DC Low/high duty cycle 40 60 % tTLH Rise time, CLK 10 ns tTHL Fall time, CLK 10 ns tISU Setup dme, input valid before CLK↑ 3 Copyright © JORJIN TECHNOLOGIES INC. 2015 http://WWW.
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Doc No: WG7833-B0-DTS-R03 tIH Hold dme, input valid afer CLK↑ 2 tODLY Delay dme, CLK↓ to output valid 2.5 CI Capacitive load on outputs ns 14.8 ns 15 pF (1) To change the data out clock edge from the falling edge (default) to the rising edge, set the configuration bit. (2) Parameter values reflect maximum clock frequency. 5.2.2. SDIO Switching Characteristics – High Rate Figure 5-3. SDIO HS input timing Figure 5-4. SDIO HS output timing Copyright © JORJIN TECHNOLOGIES INC. 2015 http://WWW.
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Doc No: WG7833-B0-DTS-R03 Table 5-2. SDIO HS Timing Characteristics PARAMETER MIN MAX UNIT Fclock Clock frequency, CLK 0 50 MHz DC Low/high duty cycle 40 60 % tTLH Rise time, CLK 3 ns tTHL Fall time, CLK 3 ns tISU Setup dme, input valid before CLK↑ 3 ns tIH Hold dme, input valid afer CLK↑ 2 ns tODLY Delay dme, CLK↓ to output valid 2.5 CI Capacitive load on outputs 14 ns 10 pF 5.3.
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Doc No: WG7833-B0-DTS-R03 5.3.1. UART 4-Wires Interface – H4 The interface includes four signals: TXD, RXD, CTS and RTS. Flow control between the host and the Device is byte-wise by hardware. ( See Figure 5-5 ) Figure 5-5. HCI UART Connection When the UART RX buffer of the device passes the flow-control threshold, the buffer sets the UART_RTS signal high to stop transmission from the host. When the UART_CTS signal is set high, the device stops transmitting on the interface.
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Doc No: WG7833-B0-DTS-R03 CTS low to TX_DATA off Hardware flow control t4 1 CTS High Pulse Width t6 1 RTS low to RX_DATA on t1 0 RTS high to RX_DATA off Interrupt set to 1/4 FIFO STR-Start bit; bit 2 us t2 16 D0..Dn - Data bits (LSB first); PAR - Parity bit (if used); Byte Bytes STP - Stop bit Figure 5-7. UART Data Frame 5.5. Bluetooth Codec-PCM(Audio) Timing Specifications Figure 5-8 shows the Bluetooth codec-PCM (audio) timing diagram.
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Doc No: WG7833-B0-DTS-R03 Table 5-6. Bluetooth Codec-PCM Slave Timing Characteristics Parameter Symbol Min Cycle time Tclk 81 (12.288MHz) High or low pulse width Tw 35% of Tclk min AUD_IN setup time tis 5 AUD_IN hold time tih 0 AUD_OUT propagation time top 5 AUD_FSYNC_OUT propagation time top 0 Capacitive loading on outputs Cl Copyright © JORJIN TECHNOLOGIES INC. 2015 http://WWW.JORJIN.COM.
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Doc No: WG7833-B0-DTS-R03 6. CLOCK AND POWER MANAGEMENT The slow clock is a free-running, 32.768 kHz clock supplied from an external clock source. The clock is connected to the RTC_CLK pin and is a digital square-wave signal in the range of 0 to 1.8V nominal 6.1. Reset-Power-Up System After VBAT and VIO are fed to the device and while BT_EN and WL_EN are deasserted (low), the device is in SHUTDOWN state, during which functional blocks, internal DC-DCs, and LDOs are disabled.
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Doc No: WG7833-B0-DTS-R03 6.3. Bluetooth/BLE/ANT Power-Up Sequence Figure 6-2 shows the Bluetooth/BLE/ANT power-up sequence. Figure 6-2 Bluetooth/BLE/ANT power-up sequence Copyright © JORJIN TECHNOLOGIES INC. 2015 http://WWW.JORJIN.COM.
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Doc No: WG7833-B0-DTS-R03 7. REFERENCE SCHEMATIC 7.1. Module Reference Design VIO_IN Must reserve PU cricuit for Debug. R1 NL_10K RES1005 WLAN_IRQ_1V8 VDD_TCXO_OUT TCXO1 TCXO/2016/26MHz TCXO-2.0X1.6 3 GND OUT 4 VCC GND WL_EN_1V8 C1 33pF CAP1005 R2 0R RES1005 50 ohms single ended VBAT_IN R3 1 BT_EN_1V8 0R RES1005 J1 U.FL-R-SMT-1(10) U.
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Doc No: WG7833-B0-DTS-R03 8. DESIGN RECOMMENDATIONS 8.1. Design Note on Debug Port Pin# C6, C4 serve as WLAN and BT debug port, respectively. So test points for these two signals should be reserved for debugging purpose. Pin# C11 (WLAN_IRQ) needs to be pulled high via 10Kohm and use Pin# D11, C7 (WL_RS232_RX, WL_RS232_TX) as hardware interface to communicate with system platform and TI RTTT test utility for WLAN RF performance test, debug and manufacturing application. 8.2.
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Doc No: WG7833-B0-DTS-R03 Isolate different power traces with Ground plane Ground Having a complete Ground and more GND vias under module in layer1 for system stable and thermal dissipation. Have a complete Ground pour in layer 2 for thermal dissipation. Increase the GND pour in the 1st layer, move all the traces from the 1st layer to the inner layers if possible. Move GND vias close to the pad.
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Doc No: WG7833-B0-DTS-R03 9. PACKAGE INFORMATION 9.1. Module Mechanical Outline 12.8±0.1 mm 1.63±0.1 mm 12.0±0.1 mm Figure 9-1. Module mechanical outline Copyright © JORJIN TECHNOLOGIES INC. 2015 http://WWW.JORJIN.COM.
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Doc No: WG7833-B0-DTS-R03 Figure 9-2. Module pad dimensions *We recommend adopting the same dimensions listed above for building PCB footprint. ** Pad tolerance as +/- 30um 9.2. Ordering Information Part number: WG7833-B0 Copyright © JORJIN TECHNOLOGIES INC. 2015 http://WWW.JORJIN.COM.
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Doc No: WG7833-B0-DTS-R03 9.3. Package Marking PIN-1 Marking Figure 9-3. Package Marking Date Code: YYWWSSFAX YY = Digit of the year, ex: 2011=11 WW = Week (01~52) SS = Serial number from 01 ~99 match to manufacture’s lot number F = Reserve for internal use A = Module version from A to Z X = Chip version Copyright © JORJIN TECHNOLOGIES INC. 2015 http://WWW.JORJIN.COM.
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Doc No: WG7833-B0-DTS-R03 10. SMT AND BAKING RECOMMENDATION 10.1. Baking Recommendation Baking condition： - Follow MSL Level 4 to do baking process. - After bag is opened, devices that will be subjected to reflow solder or other high temperature process must be a) Mounted within 72 hours of factory conditions <30°C/60% RH, or b) Stored at <10% RH. Devices require bake, before mounting, if Humidity Indicator Card reads >10% If baking is required, Devices may be baked for 8 hrs. at 125 °C. 10.2.
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Doc No: WG7833-B0-DTS-R03 Note: (1) Reflow soldering is recommended two times maximum. (2) Add Nitrogen while Reflow process： SMT solder ability will be better. Stencil thickness：： 0.1~ 0.13 mm (Recommended) Soldering paste (without Pb)：： Recommended SENJU N705-GRN3360-K2-V can get better soldering effects. 11. HISTORY CHANGE Revision Date Description R 0.1 2014/08/28 New Released R 0.2 2014/09/29 Modify the module thickness from 1.7±0.05 mm to 1.63±0.1 mm Modify the package marking. R 0.
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Doc No: WG7833-B0-DTS-R03 FCC WARING STATEMENT This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
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Doc No: WG7833-B0-DTS-R03 install or remove this RF module in the user manual of the end product. The user manual which is provided by OEM integrators for end users must include the following information in a prominent location. 1.
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Doc No: WG7833-B0-DTS-R03 NCC WARING STATEMENT Article 12 Without permission, any company, firm or user shall not alter the frequency, increase the power, or change the characteristics and functions of the original design of the certified lower power frequency electric machinery.