Instrument Specialties Company, Inc.
ALUM, INL. Mixed Signal ICs DATA BULLETIN Tem MX91 9B 4-Level FSK Modem Data Pump PRELIMINARY INFORMATION Features Applications + 4-Level Root Raised Cosine FSK Modulation » Wireless Data Terminals « Half Duplex, 4800 to 19.
CONTENTS Section : Page 1 BOCK Diagram rresnansanans revemesansnrane sores rnssrernsnnss 8 2 SIGNAL LIB ceucureecurcremrrmssucanss sacs cornrow care mass assassin aan saran eonraesnanans extemporaneousness — 3 External COMPONENTS. ...ccoaerscrmssrcsmrenmns aces sass manana tams again is sons sensation sereneness 8 4 General Description ceseuseimasaransen @ 4.1 Description of Blocks representatives @ 4.1.1 Data Bus Buffers pn 4.1.2 Address and R/W Decode 4.1.3 Status and Data Quality Register: 4.
5215 TB: Transmit Intermediate Block. evict sins saneness ern 1 9 452.16 TLB: Transmit Last 45217 T4S: Transmit 4 Symbols... 45218 RESET: Stop any current action 452.19 Task Timing 45220 RRC Filter Delay 453 Control Register... 45.31 Control Register B7, Bi pn Clock Division Ratio 453.2 Control Register BS, B4: STOL Frame Sync Tolerance to Inexact Marches 4533 Control Register B3, B2: LEVERS Level Measurement 4534 Control Register B1, BO: PL LBW Phase-Lacked Loop Bandwidth Modes . 4.54 Mode 454.
.6 Received Signal QUAY MORTON vermin seemliness sms censers sis ssa sass chess assesses 39 6 Performance Specification 6.1 Electrical Performance 6.1.1 6.12 6.1.3 6.1.4 6.15 6.1.6 6.2 Packaging Absolute Maximum Ratings Operating Limits... Operating Characteristics Operating Characteristics Notes: Timing... Typical Bit Error Rat M-COM, Inc.
Figure figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: “figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figures Page Block Diagram Recommended External Components Typical Modem uC connections ..
1 Block Viagra m DATA TG « STATUS QUALITY REGISTER ASTER COMMAND MODE CONTROL J DATA REGISTER REGISTER REGISTER Jy D4 BUFFERS ii D5 & DATA BE Dé = BUFFER zor CRC 2 T I GENERATOR Ww as CHECKER pi oppress ENCODER/ pe DECODER DECODE INTERLEAVE/ FRAME “ DE-INTERLEAVE | | SYNC DETECT oo Vivas ¥ JH Tx Symbols Fix Symbols Vss DROPOUT T Dot x } Fix Input Amp : Fx LEVEL/CLOCK 1 Visas — 1 no [Rx] EXTRACTION DOG | FAIN Me = LOW PASS I~ 1 NAAN FILTER ITAL Rx TT f CLOCK Vase ey < OSCILLATOR I DIVIDERS Tx Output Buffer C
2 Signal List Pin No. Signal Type Description 1 RG output | A ‘wire-OR able’ output for connection to the host Cu's Interrupt Request input. When active, this output has a low impedance pull down to Vs. It has a high impedance when inactive. 2 D7 BUS 3 D6 BUS 4 05 BUS 5 D4 BUS Pins 2-9 (D7-D0) are 8-bit, bi-directional, 3-state 6 D3 BUS iC interface data lines 7 D2 BUS 8 D1 BUS 9 Do BUS 10 RD input | Read. An active low logic level input used to control the reading of data from the modem into the host uC.
3 External Components Von C1 Foe TIMEOUT Discriminator W ps Vans To Tx Frequency wo TOUT Ra Modulator LT pi «—»5 Mx819B [noc STIR u py «—»8 +339 16 XIE, fellatio Z WH 11 14 [arm Fd Ver c 7] ANTICLOCKWISE Q Cs 12 affects— cal TAC v Figure 2: Recommended External Components Component | Notes | Value | Tolerance Component | Notes | Value | Tolerance Ri 1 120% 100k0 +20% ce 5 +20% R4 100kQ +20% +20% C3 3 £20% Xi 28 Recommended External Component Notes: 1. See Sectionalism. 2.
4 General Description 4.1 Description of Blocks 1.1.1 Data Bus Buffers Eight bi-directional 3-state logic level buffers between the modem's internal registers and the host PC's data bus lines. 4.1.2 Address and R/W Decode This block controls the transfer of data bytes between the pC and the mode's internal registers according to the state of the Write and Read Enable inputs (WIT and RD }, the Chip Select input (C5 ), and the Register Address inputs AB and A1.
4.1.10 Rx Input Amp This amplifier allows the received signal input to the modem to be set to the optimum level by suitable selection of the external components R1 and A2. The value of R1 should be calculated to give 0.2 x Vpp voluptuous at the BADMOUTH pin for sequence. A capacitor may be placed in series with R1 if ac coupling of the received signal is desired (see Section 5.
Frequency / Bit Rate Figure 5: RRC Filter Frequency Response vs. Bit Rate {including the external RC filter R4/C5) 0 E— Frequency / Symbol Rate Figure 6: RAC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/CS) 4.1.12 Tx Output Buffer This is a unity gain amplifier used in the transmit mode to buffer the output of the Tx low pass filter.
4.1.13 Rx Level/Clock Extraction These circuits, which operate only in receive mode, derive a symbol rate clock from the received signal and measure the received signal amplitude and DC offset. This information is then used to extract the received 4-level symbols and also to provide an input to the received Data Quality measuring circuit, The textual capacitors C6 and C7 form part of the deceived signal level measuring circuit.
Accordingly, 1 byte = 4 symbols = 8 bits, and one byte translates to four symbols for the T4S and R4S tasks and six bytes translates to twenty-four symbols for the T24S task described in Section 4.5.2. MSB LSB Bits: Symbols: sent first sent last 2. FEC way: (more complicated) essentially translates groups of 3 binary bits to pairs of 4-level symbols using a Forward Error Correcting coding scheme for the block oriented tasks THB, TIB, TLB, RHB, and RIB described in Section 456.2.
4.4 Frame Structure Figure 7 shows how an over-air message frame may be constructed from a sequence of: a Symbol Sync pattern _ (preamble), a Frame Sync pattern, and one or more ‘Header, ‘intermediate’ or ‘Last’ blocks. \ Header Block Intermediate Block Last Block : \ Be 24655100312) 110 706151413121 10, DELAY binary data stored 3 11 Data Bytes [] [1 Data Bytes K] Darla Bros [4 in MX9798 data block memory configured header named, East block by MX9198 7 0) task being executed.
received correctly can be identified as such, and do not need to be re-transmitted. These, and some other possible frame structures, are shown in Figure 8. A SYMBOL | FRAME ” “| syn | sync HEADER BLOCKS 8 'symbol | FRAME . TAT "1 syn G | syn C INTERMEDIATE’ BLOCKS BLOCK C ['Sheol | FRAME ; “| syn | syn INTERMEDIATE’ BLOCKS ..
and extract symbols from the received signal, supplying them to the DE-interieave buffer, otherwise these received symbols are ignored. ass Command Register B7: MASC Acquire Symbol Clock "his bit has no effect in transmit mode. in receive mode, when a byte with the MASC bit set to '1' is written to the Command Register, and TASK is not set to RESET, it initiates an automatic sequence designed to achieve symbol timing synchronization with the received signal as quickly as possible.
Once all of the data has been transferred from the Data Block Buffer, the modem will set the FREE and IRQ bits of the Status Register to *1', (causing the chip {AG output to go low if the IRENE bit of the Mode Register has been set to “1') to tek the pC that it may write new data and the next task to the modem.
MX919B Modem Tasks: Receive Mode Transmit Mode NULL NULL SSH Search for FS + Header T248 Transmit 24 symbols RHB Head Header Block THB Transmit Header Block 0 1 1 [RUB Read Intermediate or Last Block | TIE Transmit Intermediate Block Search for Frame Sync TLB Transmit Last Block R4S Read 4 symbols T48 Transmit 4 symbols NULL NULL RESET Cancel any current action RESET Cancel any current action 4.5.2.
4.52.12 RAS: Read 4 Symbols This task causes the modem fo read the next 4 symbols and translate them directly (without DE-interleaving or FEC) to an 8-bit byte which is placed into the Data Block Buffer. The FREE and IRQ bits of the Status Register are then set to “10 “indicate that the pC may read the data byte from the Data Block Buffer and write the next task to the Command Register. This task is intended for special tests and channel monitoring ~ perhaps preceded by a SFS task.
4.52.16 TLB: Transmit Last Block This task takes 8 bytes of data from the Data Block Buffer, updates and appends the 4-byte CHIC checksum, translates the resulting 12 bytes to 4-level symbols (with FECES, interleaves the symbols, and transmits the result as a formatted ‘Last’ “Sock. Once the modem has read the data bytes from the Data Block Buffer, the FREE and IRQ bits of the Status Register will be settle's. 4.5.2.
Data to Data Block Buffer = 3 Task to Command Register Riel a] —t EMPTY Bit FREE Bit ely meme ftp tty Symbols to RRC Filter L multitask tom Task? | Rem Tesla | Modem Tx Output —— ead Figure 11: Transmit Task Timing Diagram Modem Rx Input
453 Control Register This 8-bit write-only register controls the modem’s symbol rate, the response times of the receive clock extraction, signal _ level measurement circuits, and the Frame Sync patter recognition tolerance to inexact matches. Control Register NYY NY CK DIV STOL LEVERS PL LBW 4.5.3.1 Control Register B7, B6: CK DIV Clock Division Ratio These bits control a frequency divider driven from the clock signal present at the ITAL pin, therefore determining the nominal symbol rate.
1 0 | Mossy Peak Detect 1 1 | Slow Peak Detect 1 normal use the LEVERS bits should be set to '0 1' (Level Track). The other modes are intended for special purposes, 10r device testing, or are invoked automatically during an LEVEE sequence. in 'Slow Peak Detect’ modes, the positive and negative excursions of the received signal (after frittering) are measured by peak rectifiers driving the DOGCART and DOC? capacitors to establish the amplitude of the signal and any DC offset with regards to Vag.
Mode Register IRENE INVEST Tusk RX EYE PAVE Set to 000" 45.41 Mode Register B7: IRENE TRO Output Enable When this bit is set to '1', the TRQ chip output pin is pulled low (Vss) given the IRQ bit of the Status Register is a 1 454.2 Mode Register B6: INVEST Invert Symbols This bit controls the polarity of the transmitted and received symbol voltages.
Figure 14: Ideal ‘RX EYE' Signal 454.5 Mode Register B3: PAVE Powers ave When this bit is a 1", the modem will be in a ‘power save’ mode in which the internal filters, the Rx Symbol and Clock extraction circuits, and the Tx output buffer will be disabled. The TOUT pin will be connected ta Vp as through a high value internal resistance. The Ital clock oscillator, Rx input amplifier and the uC interface logic will continue to operate. Setting the PAVE bit to ‘0 restores power to all of the chip circuitry.
4552 Status Register B6: FREE Data Block Buffer Free This bit reflects the availability of the Data Block Buffer and is cleared to '0" when a task other than NULL or RESET is written to the Command Register. n transmit mode, the FREE bit will be set fo '1’ (also setting the Status Register IRQ bit to '1'} by the modem when the mode is ready for the pC to write new data to the Data Block Buffer and the next task lo the Command Register.
250 150 100 (noise in 2 x symbol-rate bandwidth) Figure 15: Typical Data Quality Reading vs S/N The Data Quality readings are only valid when the modem has successfully acquired signal level and timing lock for at least 64 symbol times. it is invalid when an MASC or LEVEE sequence is being performed or when the LEVERS setting is "Mossy Peak Detect’. A low reading will be obtained i the PL LBW bits are set to 'Wide' or if the received signal waveform is distorted in any significant way. Section 5.
4.7 Transmitted Symbol Shape Bit 4 of the Command Register (TIMPANI) selects the transmit base band signal and the receive signal equalization as follows: the TIMPANI bit is '0", then the transmit base band signal is generated by feeding full-symbol-time-wicith 4-level symbols into the RRC low pass filter. The receive signal equalization is optimized for this type of signal. With this setting, the MX9198B is compatible with the MX919A devices, another member of the MX818 device family.
Figure 18: Tx Signal Eye TIMPANI = 1 Note: Setting TIMPANI to 1’ affects the Tx output signal level as shown in Section 6.1.3 and the table below. TIMPANI =0 | TIMPANI =1 Nominal Voltage difference between continuous "+3" and 0.157Vpp 0.157Vpp continuous '-3' symbol outputs. Nominal VP for continuous ‘+3 +3 -3 symbol patter. | 0.20Vpp 0.
§ Application 5.1 Transmit Frame Example ‘he operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences, and one each Header, Intermediate and Last blocks are provided below: Ensure that the Control Register has been loaded with a suitable CK DIV value, that the IRENE and TX/BX bits of the Mode Register are '1', the RX EYE and PAVE bits are '0', and the INVEST bit is set appropriately.
START Ensure that the Control Register has been loaded with Set uC variable BLOCKS' a suitable CK DIV value 10 the lumberer of intermediate blocks 1 to be transmitted Ensure that the Mods Register ' 1RQEN, PAVE and RX EYE bits ate ‘0, Set pC variable ‘STATE to 0 the TX bits and the INVEST bit is set appropriately J Set the Mode Register IRENE BitTorrent' Write a RESET task to the Command Register v 1 Enable Cu's MX919B Tx Interrupt Service Routine Read the Status Register ¥ Write 6 bytes of Symbol Sync patt
Value oC variable STATE anyone bo FQ rote and corresponding MX9 o Echo te bog pre be nn E1308 ta Frame Vd patter ‘being transmitted. goad Header Look bytes and THB task. 2: Header or Intermediate Block being transmitted. load Intermediate or Last Block bytes & TIS of TLE task. 3: Last book being transmitted, 4 Waiting Soto ot raps mission, finish on interrupt with EMPTY bit set. EMPTY btw 1 7 Writs 6 bite Frame Sync.
5.2 Receive Frame Example The operations needed to revive a single Frame consisting of Symbol and Frame Sync sequences and one each Header, Intermediate and Last blocks are shown below; ~~ moh en Noo Ensure that the Control Register has been loaded with suitable CK DIV, STOL, LEVERS and PL LBW values, and that the IRENE bit of the Mode Register is '1', the TX/RX PAVE, and RX EYE bits are '0', and the INVEST bit is set appropriately.
Ensure that the Control Register ‘has been loaded with suitable CK DIV, STOL, LEVERS and PL LBW values 7} ~ Wait until the received carrier has been present Ensure that the Soda Ry CIRCE, for at slats 8 symbol times PAVE, RX EYE and bits are 0’, and the INVEST bit is set appropriately iy 1 Sat 4C variable STATE to 0 ‘Write a RESET task to the Command Register y J Sot the Mode Register IR GEN bit fo 1’ Fed the Status Register 1 Enable C's MX3198 Rx Interrupt Service Routine v Write a SSH task to the Command
Value of pC variable STATE" on entry to IRQ routine and corresponding MX919B's actions: ©: Frame Sync has boon recognized ‘and Header block received, read out data and kad RIB task. 1 : Intermediate black has been received, read out date and load RIB task. RETURN 2 : Last block has been received, { Not MX6198 IRQ) read out data and finish.
5.3 Clock Extraction and Level Measurement Systems 5.3.1 Supported Types of Systems The MX919B is intended for use in systems where: I. The Symbol Sync patter is transmitted immediately on start-up of the transmitter, before the first Frame Sync patter (see Figure 23). 2. A terminal may remain powered up indefinitely, transmitting concatenated Frames with or without intervening Symbol Synge patters (each Frame having a Frame Sync patter and symbol timing being maintained from one Frame to the next). 3.
5.3.4 Automatic Acquisition Functions Setting the MASC and LEVEE bits to 1" triggers the modem's automatic Symbol Clock Extraction and Level Measurement acquisition sequences, which are designed to measure the received symbol timing, amplitude, and DC offset as quickly as “= possible before switching to accurate but slower measurement modes.
2. Any ac coupling at the receive input will transform any step in the voltage at the discriminator output to a slowly decaying pulse which can confuse the modem’s level measuring circuits. As illustrated in Figure 25 below, the time for this step to decay to 37% of its original value is 'RC' where: 1 RC= 2n(3dB cut off frequency of the RC network) which is 32ms, or 153 symbol times at 4800 symbols/sec {9600bps) for a 5Hz network.
> Rx FREQUENCY Tx FREQUENCY DISCRIMINATOR MODULATOR SIGNAL LEVEL — Z" ADJUSTMENT PA SIGNAL AND ADJUSTMENT DC LEVEL REIN ¥ DROPOUT ADJUSTMENT pC 4 Tx TOUT ~> CIRCUS CIRCUITS D3 D7 20Al ——pd g xg MX9198 MODEM i 35393 Figure 26: Typical Connections between Radio and MX919B
5.6 Received Signal Quality Monitor In applications where the modem has to monitor a long transmission containing a number of concatenated Frames, it is _ recommended that the controlling software include a function which regularly checks that the modem is still receiving a “od data signal and triggers a re-acquisition and possibly changes to another channel if a problem is encountered.
6 Performance Specification 64 Electrical Performance 11 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. General Min. Max. Units Supply (Von Vss) 03 70 v Voltage on any pinto Vss -0.3 Vpp + 0.3 v Current Vpn -30 30 mA Vss -30 30 mA Any other pin Package Min, Max. Units Total Allowable Power Dissipation at Tau = 25°C 800 mw Aerating above 25°C 13 mW C above °C Storage Temperature -55 125 °C Operating Temperature Package Min. Max.
8.1.3 Operating Characteristics For the following conditions unless otherwise specified: Ital Frequency = 4.9152MHz, Symbol Rate = 4800 symbols/sec, louse Bandwidth = 0 to 9800HzZ, Vpp = 5.0V @ Tag = 25°C Notes | Min. | Typ. | Max. Units DC Parameters ipo 1 4.0 10.0 mA fpp (Vop = 3.3V) ipp (Powers ave Mode) (Powers ave Mode, Vpp = 3.3V) Parameters Tx Output TOUT Impedance Signal Level TIMPANI Vep TIMPANI = 1 3 0.88 11 1.32 VP Output DC Offset with respect to Vpp /2 4 -0.25 0.
6.1.4 Operating Characteristics Notes: 1. Not including any current drawn from the modem pins by external circuitry other than the Ital oscillator. 2. Small signal impedance. 3. Measured after the textual RC fitter (R4/C5) for symbol sequence, (Tx output level is proportional to Vpo)4. Measured at the TOUT pin with the modem in the Tx idle mode. 5. For optimum performance, measured at DROPOUT pin, fora +3 -3 symbol sequence, TXIMP=0ori, The optimum level and DC offset values are proportional to Vpp. 6.
‘WRITE CYCLE (DATA TO MODEM) tart 1 L | ADDRESS | rd pd ADDRESS VALID face =p! fos Hb», loss § frm hme lows ton I 1 DATA DATA Dora D7 (1 byte) VALID READ CYCLE (DATA FROM MODEM) tar ADDRESS ! OAL > ADDRESS VALID EON 1! ty ! Lea + twos, tax torn DATA Biro — Figure 28: pC Parallel Interface Timings
6.1.6 Typical Bit Error Rate 1-1 —— BER with FEC 1-2 = = BERBER without FEC 1-3 BER 1E4 1-5 1-6 185 18 SIN dB (Noise in 2 x Symbol Rate Bandwidth) Figure 29: Typical Bit Error Rate With and Without FEC Measured under nominal working conditions, LEVERS bits set to ‘Level Track’ or "Slow Peak Detect’ and PL LBW bits set to Medium’ or "Nam row’ Bandwidth, Command Register TIMPANI bit set (same for Tx and Rx devices), with pseud-random data.
8.2 Packaging A Zz chaparral 1 2 ALTERNATIVE Tel, JET J SL Package Tolerances DIM. MIN. TYP. MAX. A 0.613 (15.57) B 02860726) 0.299 (7.59) C 003236) 0.905 (2.67) E 0.390 (9.90) 0.418 (10.64) H 0.003008) 0.020 0.51) J 0013(039) 0.020 (0.51) K 00080091) 0.046 {1.17) Lo 0016041) 0.050 (1.27) P 0.050 (1.27) T 0x92) 0.0125 (0.32) NOTE : A dimensions in inches {mm.} Angles are in degrees Figure 30: 24-pin SPIC Mechanical Outline: Order as part no. MX919BDOW Le As] 1R818E0048 PIN Package Tolerances DIM. MIN.
—] g Package Tolerances ML DIM. MIN. TYR MAX. A 0380961) 0.409 (10.40) B 0380(061) 0.408 (10.40) C 0128(325) 0.146 (370) D 0417 (1060) 0.435 (11.05) E 047(08) 0450305 F 0.250 (6.35) a 0.250 (6.35) H 0.023 (0.58) J 0018045) 0.022 (0.55) K 0047119) 0.048 (1.22) FP 0.051 (1.30) T 9.009 (0.22) wo ss Y NOTE : All dimensions in inches {mm.) Angles are in degrees Package Tolerances DIM, MIN. TYR MAX. A 1.270 (32.28) B os00(1270) 0.555 {14.04} C 0151384) 0.220 (5.59) E 0800{1524) 0.670 {17.02} Ef 0.625 (15.