| mmmzewamaas=e | [VLA CLXIV INL. Mixed Signal ICS DATA BULLETIN mmm MX91 9B 4-L elev FSK Modem Data Pump PRELIMINARY INFORMATION Features Applications + 4-Level Root Raised Cosine FSK Modulation + Wireless Data Terminals « Half Duplex, 4800 to 19.
CONTENTS Section Page 1 Block Diagram eemereseanansan eeaereentarenrenerarsisetesttaLeaia tt nat attar ere tinted Art nea chats east es ears chant ars 6 2 Signal List transferred misrepresentation inns arrears retbisiesierarasearersar rent amen areas res Ea hbo “7 3 External pertussis renter snr rarer es bones Nome as genera incarnadine — 4 General Description restrteaaietesonnn rsa ar arms es nonappearance roorsssnssanensrane 4.1 Description of Blocks. 9 4.1.1 Data Bus Buffers 8 4.1.
5218 TIB: Transmit Intermediate BOCK... cocoons chess chess ss 18 452.16 TLB: Transmit Last Block. 45217 T4S: Transmit 4 Symbols. 4.52.18 RESET: Stop any current action 452.19 Task Timing... 4.5220 RRC Filter Delay 453 Control Register... i 453.1 Control Register B7, B6: CK DIV Clock Division Ratio 4532 Control Register BS, B4: STOL Frame Sync Tolerance fo Inexact Matches 4.53.3 Control Register B3, B2: LEVERS Level Measurement Modes. 453.
.6 Received Signal Quality Monitor ., 6 Performance Specification 6.1 Electrical Performance 6.1.1 Absolute Maximum Ratings 6.1.2 Operating Limits 6.1.3 Operating Characteristics . 6.1.4 Operating Characteristics Notes: 6.1.5 Timing... Renee 6.1.6 Typical Bit Error Hate. . 6.2 PACKAGING. ov sass seas mass ear se A344 4A VY 40aL EASE AAA 488 Shs Seder ASAP era eternal nee M-COM, Inc.
Figures Figure figure 1: Block Diagram Figure 2. Recommended External Components. Figure 3: Typical Modem uC connections Figure 4: Translation of Binary Data to Filtered 4-Level Symbols in Tx Midi tree cee nears Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5, Figure 7: Ever-AIN SIGNALIZATION.
1 Block Diagram DATA STATUS IRQ = REGISTER REE COMMAND MODE CONTROL « los DATA REGISTER REGISTER REGISTER Ti BUS Joy D4 BUFFERS 2 | os DATA Sui Ds — BUFFER GENERATOR/ CHECKER Ja — ENCODER RO ADDRESS ENCODER! AND cs RAW 1 Ao DECODE A1 INTERLEAVE/ FRAME Yoo DE-INTERLEAVE | | SYNC DETECT Voo Vivas Rx Symbols Vss | DROPOUT i.
2 Signal List Pin No. Signal Type Description 1 BQ output | A ‘wire-Rabies' output for connection to the host PC's Interrupt Request input. When active, this output has a low impedance pull down to Vgg. It has a high impedance when inactive. 2 D7 BUS 3 D6 BUS 4 D5 BUS 5 D4 BUS Pins 2-9 (D7-D0) are 8-bit, bi-directional, 3-state 6 D3 BUS uC interface data fines 7 D2 BUS 8 D1 BUS 9 Do BUS 10 RD input | Read. An active low logic level input used to control the reading of data from the modem into the host uC.
3 External Components Von Veo | F 1 From Rx FM D7 {2 al Dropout Discriminator oy «3 AXON Frauen: SE Ds oq | Sous o Tx Frequency fr TOUT [i Modulator MX919B [noc Dpe———7 15] BOCK 5 CLOCKWORK Wop «>is 17 je DAL vam c7 |cs Jos YEE g 7 Val Mee | | | O'clock cal ITAL Figure 2: Recommended External Components Component | Notes | Value | Tolerance Component | Notes | Value | Tolerance 100k +20% R4 100k 5% C7 5 £20% jal 0.1 pF 320% 0.1yF 420% | C3 3 120% Recommended External Component Notes: 1. See Section 4.1.10.
4 General Description 4.1 Description of Blocks 1.1.1 Data Bus Buffers Eight bi-directional 3-state logic level buffers between the modem's internal registers and the host Cu's data bus lines. 4.1.2 Address and B/W Decode This block controls the transfer of data bytes between the pC and the modem’s internal registers according to the state of the Write and Read Enable inputs (WR and RD ), the Chip Select input {TS ), and the Register Address inputs AD and At. The Data Bus Rulers, Address.
4.1.10 Bx Input Amp This amplifier allows the received signal input to the modem to be set to the optimum level by suitable selection of the external components R1 and R2. The value of R1 should be calculated to give 0.2 x PGP voluptuous at the DROPOUT pin far received sequence. A capacitor may be placed in series with R1 if ac coupling of the received signal is desired (see Section 5.
Frequency / Bit Rate ur Figure 5: RRC Filter Frequency Response vs. Bit Rate (including the external RC filter R4/C5) Frequency / Symbol Rate Figure 6: RRC Filter Frequency Response vs. Symbol Rate (including the external RC filter R4/C5) 4.1.12 Tx Output Buffer This is a unity gain amplifier used in the transmit mode to buffer the output of the Tx low pass filter.
4.1.13 Rx Level/Clock Extraction These circuits, which operate only in receive mode, derive a symbol rate clack from the received signal and measure the received signal amplitude and DC offset. This information is then used to extract the received 4-level symbols and also to provide an input to the received Data Quality measuring circuit. The textual capacitors C6 and C7 form part of the deceived signal level measuring circuit.
Accordingly, 1 byte = 4 symbols = 8 bits, and one byte translates to four symbols for the T4S and R4S tasks and six bytes translates to twenty-four symbols for the T248 task described in Section 4.5.2 MSB LSB Bits: Symbols: sent first sent last 2. FEC way: {more complicated) essentially translates groups of 3 binary bits to pairs of 4-level symbols using a Forward Error Correcting coding scheme for the block oriented tasks THB, TIB, TLB, RHB, and RIB described in Section 452.
4.4 Frame Structure Figure 7 shows how an over-air message frame may be constructed from a sequence of: a Symbol Sync pattern (preamble), a Frame Sync patter, and one or more ‘Header’, *Intermediate’ or ‘Last’ blocks. i \ Header Block Intermediate Block Last Block \ , Byte 1716151413(21110 7.6151 413121110; 73615 413121410) 31C binary data stored 3 171 Data Bytes [1 Data Bytes [1] 1] Data Bytes [| in MX919E data block memory configured header, intermediate, of 6 \ ast block by MX9198 7 7 task being executed
received correctly can be identified as such, and do not need to be re-transmitted. These, and some other possible frame structures, are shown in Figure 8. A | symbol | FRAME "HEADER BLOCKS SYNC SYNC B . SYMBOL | FRAME ) . LAST . SYNC SYNC INTERMEDIATE! BLOCKS BLOCK _Symbolic Frame SUNG SYNC INTERMEDIATE BLOCKS Figure 8: Alternative Frame Structures The MX919B performs the entire block formatting and DE-formatting required to convert data between uC binary form and Over-Air as shown in Figure 7. 4.
and extract symbols from the received signal, supplying them to the DE-interleave buffer, otherwise these received symbols are ignored. 4.521 Command Register B7: SCAG Acquire Symbol Clack “his bit has no effect in transmit mode. In receive mode, when a byte with the MASC bit set to ‘1’ is written to the Command Register, and TASK is not set to RESET, it initiates an automatic sequence designed to achieve symbol timing synchronization with the received signal as quickly as possible.
Once all of the data has been transferred from the Data Block Buffer, the modem will set the FREE and IRQ bits of the Status Register to '1', (causing the chip {RO output to go low if the IRENE bit of the Mode Register has been set to "1% to tell the pC that it may write new data and the next task to the modem. This lets the pC write the next task and its associated data to the modem while the modem is still transmitting the data from its previous task.
MX919B Modem Tasks: Bz | B11B0 Receive Mode Transmit Mode NULL NULL 0 0 1 SSH Search for FS + Header T248 Transmit 24 symbols RHB Read Header Block THB Transmit Header Block RLB Read Intermediate or Last Block | 718 Transmit Intermediate Block SF8 Search for Frame Sync TLB Transmit Last Block R48 Read 4 symbols T48 Transmit 4 symbols NULL NULL BESET Cancel any cement action RESET Cancel any current action 4.5.2.
4.5.2.12 R48: Read 4 Symbols This task causes the modem to read the next 4 symbols and translate them directly (without DE-interleaving or FEC) to an 8-bit byte which is placed into the Data Block Buffer. The FREE and IRQ bits of the Status Register are then set to ‘1 to ‘indicate that the uC may read the data byte from the Data Block Buffer and write the next task to the Command Register. This task is intended for special tests and channel monitoring perhaps preceded by a SFS task.
4.5.2.16 TLB: Transmit Last Block This task takes 8 bytes of data from the Data Block Buffer, updates and appends the 4-byte CR checksum, translates the resulting 12 bytes to 4-level symbols {with FECES. interleaves the symbols, and transmits the result as a formatted ‘Last’ lock. Inc the modem has read the data bytes from the Data Block Buffer, the FREE and IRQ bits of the Status Register will be sett '1'. 4.52.
Data to Data Block Buffer Task to Command Register EMPTY Bit FREE Bit rep pre F yy pity Symbols to RRC Fitter From Task ¥ 1 fom Task | From Tasks Modem Tx Output em Figure 11: Transmit Task Timing Diagram Modem Rx Input << > Symbols to DE-interleave foretaste | foretaste | foretaste — Circuit Psst lr see tae | Data from Data Block Buffer Task to Command Register tpt ile ile eit ee FREE Bit Figure 12: Receive Task Timing Diagram 4.5.2.
4.5.3 Control Register This 8-bit write-only register controls the modem's symbol rate, the response times of the receive clock extraction, signal level measurement circuits, and the Frame Sync patter recognition tolerance to inexact matches. Control Register NY YY CK DIV STOL LEVERS PL LBW 4.5.3.1 Control Register B7, B6: CK DIV Clock Division Ratio These bits control a frequency divider driven from the clock signal presenter at the ITAL pin, therefore determining the nominal symbol rate.
1 0 | Mossy Peak Detect 1 1 | Slow Peak Detect 1 normal use the LEVERS bits should be set to '0 1' {Level Track). The other modes are intended for special purposes, 101 device testing, or are invoked automatically during an LEVEE sequence. In 'Slow Peak Detect’ modes, the positive and negative excursions of the received signal (after filtering) are measured by peak rectifiers driving the DOC and DOC capacitors to establish the amplitude of the signal and any DC offset with regards to Viagra.
Mode Register TI {GEN INVEST TWX RX EYE PAVE Set to 000° 454.1 Mode Register B7: IRENE [HG Output Enable When this bit is set to the RQ chip output pin is pulled low (Vgg) given the IRQ bit of the Status Register is a "1". 4.5.4.2 Mode Register B6: INVEST Invert Symbols This bit controls the polarity of the transmitted and received symbol voltages.
Figure 14: Ideal 'RX EYE’ Signal 454.5 Mode Register B3: PAVE Powers ave When this bit is a ‘1°, the modem will be in a ‘power save’ mode in which the internal filters, the Rx Symbol and Clock extraction circuits, and the Tx output buffer will be disabled. The TOUT pin will be connected to Piaget through a high value internal resistance. The Ital clock oscillator, Rx input amplifier and the uC interface logic will continue to operate. Setting the PAVE bit to 0" restores power to all of the chip circuitry.
45.52 Status Register B6: FREE Data Block Buffer Free This bit reflects the availability of the Data Block Buffer and is cleared to '0' when a task other than NULL or RESET is written to the Command Register. n transmit mode, the FREE bit will be set to '1' (also setting the Status Register IRQ bit to 1") by the modem when the modem is ready for the LC to write new data to the Data Brock Buffer and the next task to the Command Register.
250 200 150 100 (noise in 2 x symbol-rate bandwidth) Figure 15; Typical Data Quality Reading vs S/IN The Data Quality readings are ably valid when the modem has successfully acquired signal level and timing lock for at least 64 symbol times. It is invalid when an MASC or LEVEE sequence is being performed or when the LEVERS setting is ‘Mossy Peak Detect’. A low reading will be obtained if the PL LBW bits are set to ‘Wide’ or if the received signal waveform is distorted in any significant way. Section 5.
4.7 Transmitted Symbol Shape Bit 4 of the Command Register (TIMPANI) selects the transmit base band signal and the receive signal equalization as follows: the TIMPANI bit is '0", then the transmit base band signal is generated by feeding full-symbol-time-width 4-elev! symbols into the RRC low pass filter. The receive signal equalization is optimized for this type of signal. With this setting, the MX2198 is compatible with the MX919A devices, another member of the MX918 device family.
Figure 18: Tx Signal Eye TIMPANI = 1 Note: Setting TIMPANI to affects the Tx output signal level as shown in Section 6.1.3 and the table below. TIMPANI =0 | TIMPANI = 1 Nominal Voltage difference between continuous +3’ and 0.157Vpp 0.157Vpp | continuous '-3' symbol outputs. ! Nominal Veep for continuous *+8 +3 -3 symbol pattern. 0.20Vpp 0.
5 Application 5.1 Transmit Frame Example The operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences, and one each Header, Intermediate and Last blocks are provided below: 1. Ensure that the Control Register has been loaded with a suitable CK DIV value, that ihe IRENE and TX/FRX bits of the Mode Register are '1’, the RX EYE and PAVE bits are '0', and the INVEST bit is set appropriately. 2.
START Ensure that the Contention Register has been loaded with Set uC variable BLOCKS' a suitable CK DIV value 10 the number of Intermediate blocks to be transmitted Ensure that the Mode Register ' {RENE, PAVE and RX EYE bits are '0', Set uC variable ‘STATE to © the TX/RX bits 't", and the INVEST bit is set appropriately v Set the Mode Register (RENE ditto ‘1 Write a RESET task to the Command Register 1 v Enable C's MX9168 Tx Interrupt Service Routing Read the Status Register v Witt 6 bytes of Symbol Sync p
Value of uC variable 'STATE' on gantry lo IRQ routine and compounding MX3188's actions: 0. Symbol Sync pattern being transmitted, toad Frame Sync patter & 1245 task. +: Frame Sync pane being transmitted. load Header Block bytes and THB task. 2 Header or Intermediate Block being transmitted, goad Intermediate or Last Brock bytes & TIB or TLB task. 2: Last block being transmitted, ignore this interrupt. 4 Salting for end of transmission, finish on interrupt with EMPTY bit set.
5.2 Receive Frame Example The operations needed to receive a single Frame consisting of Symbol and Frame Sync sequences and one each Header, Intermediate and Last blocks are shown below; 4 ose Ensure that the Control Register has been loaded with suitable CK DIV, STOL, LEVERS and PL LBW values, and that the IRENE bit of the Mode Register is 1", the TX/BX PAVE, and RX EYE bits are '0’, and the INVEST bit is set appropriately.
START Ensure that the Control Register has been loaded with suitable CR DIV, STOL.
Value of 4.
5.3 Clock Extraction and Level Measurement Systems 5.3.1 Supported Types of Systems The MX919B is intended for use in systems where: {. The Symbol Sync pattern is transmitted immediately on start-up of the transmitter, before the first Frame Sync pattern {see Figure 23). 2. A terminal may remain powered up indefinitely, transmitting concatenated Frames with or without intervening Cymbal ee patterns {each Frame having a Frame Sync pattern and symbol timing being maintained from one Frame to the next). 3.
5.34 Automatic Acquisition Functions Setting the MASC and LEVEE bits to '1' triggers the modem's automatic Symbol Clock Extraction and Level Measurement acquisition sequences, which are designed to measure the received symbol timing, amplitude, and DC offset as quickly as Possible before switching to accurate but slower measurement modes.
2. Any ac coupling at the receive input will transform any step in the voltage at the discriminator output 1o a slowly decaying pulse which can confuse the modem's level measuring circuits. As illustrated in Figure 25 below, the time for this step to decay to 37% of its original value is ‘RC" where: 1 RC= 2r{3dB cut off frequency of the RC network) which is 32ms, or 153 symbol times at 4800 symbols/sec (3600bps) for a 5Hz network.
Rx FREQUENCY Tx FREQUENCY — DISCRIMINATOR MODULATOR SIGNAL LEVEL 3 ‘ADJUSTMENT DC LEVEL ) ADJUSTMENT SIGNAL Ao REIN EXAMPLE ADJUSTMENT uc Fox ™ TOUT 1 7 CIRCUITS CIRCUITS Who-o 00-7 gpd D0-D7 TE—» MX9198 MODEM TC Figure 26: Typical Connections between Radio and MX919B
5.6 Received Signal Quality Monitor In applications where the modem has to monitor a long transmission containing a number of concatenated Frames, it is recommended that the controlling software include a function which regularly checks that the modem is still receiving a ‘aod data signal and triggers a re-acquisition and possibly changes to another channel if a problem is encountered.
6 Performance Specification 6.1 Electrical Performance 511 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage ta the device. General Min, Max. Units Supply (Voo Vss) -0.3 7.0 Vv Voltage on any pinto Vgg -0.3 Vpp + 0.3 Vv Current Vop Any other pin Package Min. Max. Units Total Allowable Power Dissipation at App = 25°C 800 mw Aerating above 25°C 13 MW above °C Storage Temperature -55 125 °C Operating Temperature Package Min. Max.
6.1.3 Operating Characteristics For the following conditions unless otherwise specified: Ital Frequency = 4.9152MHz, Symbol Rate = 4800 symbols/sec, louse Bandwidth = 0 to 9600Hz, Vpp =5.0V @ Tap = 25°C Notes | Min. | Typ. | Max. Units DC Parameters loo 1 40 10.0 mA lop (Vop = 3.3V) Ipp (Powers ave Mode) 1 1.5 mA fpp (Powers ave Mode, Vg = 3.3V) Parameters Tx Output TOUT Impedance Signal Level TIMPANI VP TIMPANI = 1 3 0.88 11 1.32 Veg Output DC Offset with respect to Vpp /2 4 -0.25 0.
6.1.4 Operating Characteristics Notes: 1. Not including any current drawn from the modem pins by external circuitry other than the Ital oscillator. 2. Small signal impedance. 1. Measured after the external RC filter (R4/C5) for symbol sequence, (Tx output level is proportional fo Vpo)4. Measured at the TOUT pin with the modem in the Tx idle mode. 5. For optimum performance, measured at DROPOUT pin, for a +3 -3 symbol sequence, TIMPANI =O or 1, The optimum level and DC offset values are proportional to Vp.
WRITE CYCLE (DATA TO MODEM) tan H— | Cu oss Xe ADDRESS VALID lavs Wed Tog HEI SEE fossa 1 1 : tow DATA DATA Dotard (1 byte) VALID 1 ‘ READ CYCLE (DATA FROM MODEM) Lan Het 3 I ADDRESS ADDRESS VALID taser rm oan tors; ple sam tax opp DATA oto D7 (1 byte ! — CATS VALID Ds EEE.
6.1.6 Typical Bit Error Rate 1-1 ——e BER with FEC 18-2 = = BERBER without FEC 1-3 BER 1-4 1-5 1-6 (Noise in 2 x Symbol Rate Bandwidth) Figure 29: Typical Bit Error Rate With and Without FEC Measured under nominal working conditions, LEVERS bits set to "Level Track’ or ‘Slow Peak Detect’ and PLEBE bits set to ‘Medium’ or ‘Narrow’ Bandwidth, Command Register TIMPANI bit set (same for Tx and Rx devices), with suede-random data.
6.2 Packaging Package Tolerances DIM. MIN. TYR MAX. A 0597 (15.16) 0618 (15,57) B 0286 (726) 0.299 (7.59) C 0.105 (2.67) E 0.390 (9.90 0.419 (10.64) H 0.003 (0.08) 0.020 (0.51) J 0.020 (0.51) K 0.006091) 0.046 {1.17 L 0.016 (041) 0.050 (1.27) p 0.050 (1.27) T 0.0125 (0.32) ROTE : All dimensions in inches {mm.) Angles are in degrees Figure 30: 24-pin SPIC Mechanical Outline: Order as part no. MX9198DW A Package Tolerances fe rt] UNREGENERATE DIM. MIN TYP MAX ~ A 0318807) 0.328 8.
0.380 (9.61) 0.380 (961) 0.128 (3.25) 0417 (10.60) 0.417 (10.50) Package Tolerances MIN. TYP. MAX. 0.409 (10.40) 0.409 (10.40) 0.146 (370) 0.435 (11.05) 0.435 (11.05) 0.250 (6.35) 0.028 (0.58) 0.018 (045) 0.047 (1.19) 0.040 (1.24) 0.006 (0.152) 30° Angles are 0.250 (6.35) 0.022 (0.55) 0.048 (1.22) 0.051 (1.30) 0.008 (0.22) a5 go NOTE : All dimensions in inches (mm) degrade Figure 32: 24-pin PL CC Mechanical Quinine : Order as part no. MX919BLH A ALAS ALAS j TATTY TV YY PIN | B 1 Package Tolerances DiM. MIN.