inter iAPX 432 Interface Processor Architecture Reference Manual 171863-001
INTEL iAPX 432 INTERFACE P~OR Manual Orner Number 171863-001 Release 1.
Additional oopies of this manual or other Intel literature may be obtained from: Literature Department Intel Corporation 3065 BCMers Avenue Santa Clara, CA 95051 The information in this document is subject to change without notice. Intel Corporation makes no warranty of any kind with regard to this material, including, but not limited to, the inplied warranties of merchantability and fitness for a particular p..1rpose.
PREFACE Understanding any complex comp.lting system, such as the Intel iAPX 432, requires the assimilation of a great deal of technical information. Before reading this manual on the architecture of the 432 Interface Processor, the reader should have conmand of the general 432 concepts. Intel offers three documents which provide these prerequisites. o The INTEL 432 System Summary, Order Number 171867, provides the broad picture of the 432. It should be read as a first introduction to the 432 system.
TABLE OF CCNl'ENI'S TITLE 1. PAGE KE'Y' 1-1. 1-2. 1-3. 1-4. 1-5. crncEP'l'S ...•.....•.•..•....••.....•••.•••••••••...•..•..
3. ~ ••••••••••••••••••••••••••••••••••••••••••••••••••••• 3-1. WindCM AttribJtes Wioo~ Status ••••••••••••••.••••••••••••••••••••••••••• Subrange Base Address arrl Subrange Size Object Reference Direction ............................................ . Transfer Status ••••••••••••••••••••••••••••••••••••••• Transfer Mode ......................................... O\Terlay ••••••••••••••••••••••••••••••••••••••••••••••• 3-2. 3-3. 3-4. 3-5.
APPENDICES Page APPENDICES A. SYS'm1 ~ S~ A-I. Context Objects A-2. A-3. S~Y FA~T S~y C-l. C-2. C-3. C-4. A-I A-3 .......................................... . A-7 ........................................ Process Objects Processor Objects B. FUNCTICN c. ••••••••••••••••••••••••••••••••••••••• A-l ............................................ B-1 C-l .......................................... C-l C-l •••••••••••••••••••••••••••••••"••••••• e.
TABLES TITLE 1-1. 2-1. 2-2. 2-3. 3-1. B-1. B-2. B-3. D-l. E-l.
FIGURES PAGE TITLE 1-1. 1-2. 1-3. 1-4. 1-5. 1-6. 1-7. 1-8. 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. 4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 6-1. 0-1. E-l. F-l. F-2. F-3. F-4. F-5.
CHAPTER 1 KEY CCNCEPTS This chapter introduces the iAPX 432 Interface Processor (IP). The first four sections cover the IP as it is used normally in connection with inIXlt/output operations. Section 1-1 distinguishes Peripheral Subsystems (PS), which are responsible for the bulk of I/O operations, fran the 432 data processing system, and shows how Interface Processors link these together. The second section reviews the 432' s basic model of inp.
iAPX 432 Interface Processor Architecture Reference Manual 432 Memory 432 System/Peripheral Subsystem Boundary Figure 1-1 432 System and Peripheral SljbSystems 1-2
KEY CCHE?TS In a 432-based system, the bulk of processing required to support inplt/out];Xlt operations is delegated to Peripheral Subsystems; this includes device control, timing, interrupt handling and buffer ing • A Peripheral Subsystem is an autonomous computer system with its own memory, I/O devices am controllers, at least one processor, and software.
iAPX 432 Interface Processor Architecture Reference Manual It is ~rtant to note that both the window and function facilities utilize and strictly enforce the standard 432 addressing and protection systems. Thus, a window provides protected access to an object, and a function provides a E.rotected way for Peripheral Subsystem software to interact with the 432 system. 1-2.
KEY CONCEP'IS 432 System Peripheral Subayatem ------------------- Service Order Messaqe o Device Task Procesa (:;'\ -V Service Reply Message O. 1. 2. Process running on GDP needs I/O service Process formulates message describing service, sends it to device task Device task receives service order, interprets it 3. 4. 5.
iAPX 432 Interface Processor Architecture Reference Manual 432 System - - - - - - - P e r i p h e r a l Subsystem - - - - - - - - - - - - Device Task Figure 1-3 Peripheral Subsystem Interface 1-6 f
1-3. PERIPHERAL SUBSYS'lm INTERFACE A Peripheral Subsystem interface is a collection of hardware and software that acts as an ad.aptor which enables message-based oammunication between a process in the 432 system and a device task in a Peripheral Subsystem. Viewed from the 432 side, the Peripheral Subsystem interface appears to be a set of processes. The Peripheral Subsystem interface may be designed to present any desired appearance to a device task. For example, it may look like a collection of tasks.
iAPX 432 Interface Processor Architecture Reference Manual 432 System --------.~ ~~~--------- Peripheral Subsystem Optional DMA ontrolle "tt H o (1 en UI UI oH I 432 3: (1) :I o H Memory '< H ::s rt en H (1 o ::s ::s (1) n "tt co t1 ~. :J" ~---- ..... ---. (1) t1 -, :) J Logical I» I-' ~ ~Attached ~ ~Iprocessor rt' (1) EJ '-------01 to I-----~--' ; ..... - ......... -...
KEY COOCEPTS Continuing the notion of the logical I/O processor, the Attached Processor fetches instructions, provides the instructions needed to alter the flow of execution, and performs arithmetic, logic and data transfer operations within the Peripheral Subsystem. INTERFACE P~SSOR The IP completes the logical I/O processor by providing data paths between the Peripheral Subsystem and the 432 system.
iAPx 432 Interface Processor Architecture Reference Manual To sunmar ize, the Attached Processor and the Interface Processor interact with each other by means of address references generated by the AP and interrupts generated by the IP. Since the Interface Processor respoms to memory references, other active Peripheral Subsystem agents (bus masters), such as ~ controllers, may obtain access to 432 system memory via the IP's windows.
KEY CXNCEP'IS The Interface Processor provides a process addressing environment within the 432 system which supports the operation of the I/O controller in the 432 system. This environment is embodied as a set of system objects that ·"are used and manipulated by the IP. At any t~e, the I/O controller is represented in 432 memory by IP process obj ects am associated context obj ects. Like a GOP, the IP itself is represented by a processor object.
iAPX 432 Interface Processor Architecture Reference Manual -f-Peripheral Subsystem Memory space---"I ~ 432 System Memory Space --. Local Memory Addresses Interface Processor ( .....----... - IP window maps a subrange of peripheral subsystem addresses onto an object in 432 memory --- I Object Subrange 0,I windowed Memory Reference"~"~....mm=-"ED"~~ ~ .................. ~ .....----+ - - - - ......._--_....
KEY CCNCEPTS Since a windCM is referenced like memory, any individual transfer may be between an obj ect and PS memory, an object and a PS processor register, or an object and an I/O device. The latter may be appealing from the standpoint of "efficiency," rut it should be used with caution. Using a windCM to directly "connect" an I/O device and an object in 432 memory has the undesirable effect of propagating the real-time constraints imposed by the device beyond the subsystem boundary into the 432 system.
iAPX 432 Interface Processor Architecture Reference Manual The IP's function set permits the I/O controller to: o alter windows; o exchange messages with GOP processes via the standard 432 interprocess communication facility; o manitulate objects. These functions may be viewed as extensions to the Attached Processor's instruction set, which permit the I/O controller to operate in the 432 system.
KEY CONCEPTS _ 8tem_l_ Peripheral Sub8Y --lI-1 < Peripheral Subsystem Interface 432 0+- System - . Port Object> (1) I I Input - - -......~. 0 Message ~.~-----output 0 ~____ J~--"··~_B_u_~_~_e_r_~··IIf-----1·"O""4:l------I"·1(M~~~:~!)I""-----I··O Action _____C_o_p.Y__ D_a_ta____11 ....___C_O_p_Y_D_a_t_a_ _....11 Data Location &.S.I/0 ~~~~~!in9 ::::;n9 spac~ Device (P.S.
iAPx 432 Interface Processor Architecture Reference Manual I/O EXAMPLE To illustrate the operation of the 432 I/O model more specifically, this section provides a simple example which shows how line printer output might be implemented. Of course, the example describes only one of many possible awroaches that might be taken. Furthermore, the example does not show all the detail of a typical implementation, with the Peripheral Subsystem supporting transfers to and from a number of devices concurrently.
KEY CONCEPTS 432 Memory Peripheral subayatem Memory 432 ' S y a t _ - - - - - - -_ _ _ _ .eripheral Subayatelll I n t e r t a c e - - - - - I _ .eripheral .
iAPX 432 Interface Processor Architecture Reference Manual .Table 1-1 Pr inter Example Legend Item Description Object (message) descr ibing pr int operation fram requesting process's point of view (see figure 1-8). 432 communications port assigned convention to queue print objects. by 432 communicat ions port where GOP process waits for result of operation. SEND,/R:ErnIVE 432 operators (GOP instructions, IP functi.ons) provided for interprocess cxmnunication.
KEY
iAPX 432 Interface Processor Architecture Reference Manual Text~ CI Print Data Object References".,.
KEY CONCEPTS Printer Server Task Perspective The printer server task may be viewed as a "front end" to the pr inter task which is responsible for translating the message sent by the GOP process into the form expected by the printer task. The printer server loops through the following steps: 1. RECEIVE a message from the print_request-POrt. 2. When the message (a print object) is received, obtain an object selector for the message text. 3. Using the object selector, open a windoo onto the message text. 4.
iAPX 432 Interface Processor Architecture Reference Manual 1-5. SUPPLEMENTARY INTERFACE ProcESSOR FACILITIES The preceding sections have described the Interface Processor as it is used most of the time. The IP provides two additional capabilities which are typically used less frequently, often only in exceptional circumstances. These are physical reference nnde and interconnect access. PHYSICAL REFERENCE r-DDE An IP oormally operates in logical reference nnde.
KEY CONCEPTS The IP (like a GOP) requires two register locations in the interconnect space to be defined for any system: the processor ID register (interconnect address 0) o o the interprocessor communication (IPC) register (interconnect address 2) The remainder of the interconnect address space may be used to store or acquire other infoonation such as configuration parameters, error logging registers, and other application-specific quantities.
rnAPTER 2 CBJOCTS AND OPERA'lORS This chapter describes the 432 environment as it appears to the I/O controller software. It :r;x:>ints out what the I/O controller can, and cannot, do in the 432 system. The first section broadly compares the facilities provided by the Interface Processor to those available on the General Data Processor. The remaining sections describe Interface Processor facilities provided for: o addressing and protection; o objects for program environments; o .
iAPX 432 Interface Processor Architecture Reference Manual To permit the I/O controller to function in the 432 system as well as in the Peripheral Subsystem, the IP provides an environment, and operators that it executes within this environment.· The environment is embodied in the system objects that the Interface Processor recognizes and manipulates, while the operators take the form of function requests issued by the IP controller and executed by the IP.
CI3JECrS AND OPERATORS Table 2-1 IP/GOP System Object Comparison Object IP Implementation- Processor Object Process Obj ect Context Object Operand Stack Instruction Segment Object Table IkInain Port Carrier Storage Resource Type Definition Communication Segment Descriptor Controller Refinement Controller similar similar similar none none identical identical identical identical none identical identical identical identical Legend: identical similar none IP and GOP ~lementations are identical While conce
iAPX 432 Interface Processor Architecture Refer.ence Manual Through its windows, an IP provides the basic ability to read and wr i te the contents of objects composed of data segments. However, using its function request facility an IP can manipulate an access descriptor which references an object. The IP can examine a complex (multi-segment) object, gaining access to its (X)fT1pOnent segments.
CBJECrS AND OPERATORS Table 2-2 IP/GDP Operator Comparison (Part 1 of 2) Implementation Qe.
iAPX 432 Interface Processor Architecture Reference Manual Table 2-2 continued IP/GOP Operator Canparison (Part 2 of 2) ProcESS Cl:H1UNICATICN OPERA'IORS Send Receive Conditional Send Conditional Receive Surrogate Send Surrogate Receive Delay Read Process Clock fII PR)CESSOR (X)[\MJNICATIGl OPERATORS Send to Processor Broadcast to Processors Read Processor Status and Clock MOve to Interconnect MJve fran Interconnect BRANCH OPERA'IDRS CHARAcrER OPERATORS SHORI' ORDINAL OPERATOR) SIDRr INT.
CBJECl'S AND OPERATORS 2-2. CBJECl' ADDRESSING AND GLCBAL SIDRAGE MANAGEMENT Object addressing on the IP follows the same three level sequence as on a GOP. The steps taken to address an object are: 1. Given an access descriptor, a processor uses the directory index field to index the object table directory and gain a storage descr iptor for the o~ect table which contains an object reference for the desir object. 2.
iAPX 432 Interface Processor Architecture Reference Manual 2-4. FACILITIES FUR ASYNCHRCNOUS CDMJNlCATICN The IP offers the same set of operators for asynchronous interprocess communication as does a GOP, with the excey;>tion that the DEIAY operator ls not implemented. The DEIAY operator, used in scheduling to delay a process from being dispatched (on a GOP), is not required by an IP where process scheduling and dispatching is per formed by the I/O oontroller. 2-5.
0BJECrS AND OPERATORS Contained in each obj ect ' s storage descr iptor is an I/O lock which is applied by the IP when a window is opened on the object. This lock serves 'bNo purposes: first it guarantees that only one IP window can be opened on a particular 432 object at a time; second it prevents IIDvement of the object (e.g. by a memory compaction process) while it is mapped through a window. The transfer of data between the PS and the 432 system is a three step process.
iAPX 432 Interface Processor Architecture Reference Manual Direct vs. Indirect Accessibility If a copy of an access descriptor for an object is in one of t.he four entry access segments, the object it references is dir.ectly accessible.
CEJECrS AND OPERATORS Table 2-3 Direct/lndirect Accessibility Viewpoint of IP/GDP in 432 System . Directly Accessible 432 Infor.mation o access descriptors o data All access descriptors in the four Entry Access Segments. All objects of type data segment referenced b¥ access descriptors in the four Entry Access Segments. Indirectly Accessible 432 InfoLmation o Information, data or access, which can be reached via access path manipllation (i.e.
iAPx 432 Interface Processor Architecture Reference Manual Object Selectors An object selector identifies an object by specifying an access descriptor contained in one of the four entry access segments. The object selector oonsists of a double byte quantity composed of two fields: 1.
The Interface Processor windCM mechanism provides the Per ipheral Subsystem with protected access to the contents of objects located in the 432 system. There are five windows, labeled 0-4. Each windCM can be used to access one (single segment) object. To prevent the possible manipulation of access descriptors as ordinary data and corruption of the protection mechanisms, the windCMed object must be of base type data segment. Access descr.
iAPX 432 Interface Processor Architecture Reference Manual 3-1. WINJX)W ATl'RIBUl'ES Each window has a set of attributes which define its state at a given rnanent; these are sumnarized in table 3-1. The IP sets the attributes of all five windows when it performs processor qualification. The attributes of the control windcw are obtained from values recorded in the processor object. Processor qualification closes windows 0-3.
Table 3-1 Window Attribute Summary Attribute Description Window Status Window is open/closed/faulted Subr ange Base Address Start of windowed subr ange in the PS Subrange Size Length of windowed subrange in the PS Obj ect Reference Obj ect Selector for windowed 432 obj ect Base Displacement Displacement in bytes into windowed 432 object Direction Read/write permission for windowed object. When the window is being opened this attribute is the perm1ss1on requested by the I/O controller.
iAPX 432 Interface Processor. Architecture Reference Manual SUBRANGE BASE AIDRESS AND SUBRANGE SIZE A windCM's subrange is defined by a subrange base address and a subrange size, in bytes. The subra~ is the contiguous set of Peripheral SUbsystem memory addresses that are mapped by the windCM. A Per ipheral Subsystem bus master that references an addr.ess in a subrange accesses the corresponding object in the" 432 system. A PS subrange is defined in terms of powers of 2.
WINOOWS
iAPX 432 Interface Processor Architecture Reference Manual DIRECl'ICN The direction attribute specifies whether the windowed object may be read, written, both read and written, or neither read nor written. When the window is opened the IP checks the requested direction attribute with the access rights granted by the object reference. The access rights requested in the direction attribute must be equal to, or logically less than, the rights granted by the object reference.
00 meaning for windows 2-4, which suWOrt random transfers to 432 system memory only; the random transfer mode is described in section 3-2. Attempting to set the transfer mode of windows 2-4 will cause a fault. OVERIAY Sane Peripheral Subsystems (e.g., those based on processors with limi ted address spaces) may not be able to dedicate a block of memory space for exclusive use as IP window subranges. Such systems may elect to co-Iocate all or part of the IP' s range with real PS memory.
iAPX 432 Interface Processor Architecture Reference Manual -64K-:!::: I\~\~\! ,::" -36K- )}js';ilirange of windo,:" opened wl.th overlay attrl.bute set iiiiii!i!! :-:-:-:.:.
WINOOWS 3- 2. W1NIXM OPERATI(l\J This section descr ibes the IP' s response to an address reference that falls into the windowed subrange of an open windGl. The discussion covers random mode transfers to and from ordinary memory-based objects; the special cases of block mode, interconnect objects and function requests are covered in subsequent sections. ADDRESS RECDGNITI(l\J The Interface Processor m:mitors all Peripheral Subsystem address references that fall into its range.
iAPX 432 Interface Processor Architecture Reference Manual PS ADDRESS SPACE , -r- %P ~ 432 ADDRESS SPACE --.-.----- 64K Byte Range Adjusted Object Lenqth SOBRANGE .. Access p- I LENGTH Transfer Displacement 1 1 _.... _---- Initial Computations o Adjusted Object Length = Object Length - Base Displacement o Visible Object Length = Minimum (Adjusted Object Length, Byte Count) for block mode operation. o Visible Object Length = Minimum (Adjusted Subrange Size) for randan mode operation.
IP WINDOW MAPPED 432 OBJECT ----0 0 --------· / / 0 -------LJ ----c/// O ---- ", ----0 LJ ........
LAPX 432 Interface Processor Architecture Reference Manual 3-3. RANOOM mOE DATA TRANSFER Given that an IP address reference has passed the consistency checks, the IP finishes the Peripheral Subsystem bus cycle just as a menory oomponent would, accepting data from the bus in a wr i te operation, and placing data on the bus in a read operation.
Byte -.., 41 03 ... ...... - - disP1acement~ --- (7) I 3 (6) (5) (4 ) .... ( 3) 1 (2) (1) 2 4096 Windot'-1ed Subrange --- -- - - - (0) Windowed Object Legend Reference Sequence: Subrange Address Referenced: Reference Operation: Object Byte Accessed (disp.
iAPX 432 Interface Processor Architecture Reference Manual 3-4. BIOCK MJDE MTA TRANSFER Window 0 can be opened in random m::Xie or in block mode. Block mode allows the Peripheral Subsystem to take advantage of software instructions (e.g. iAPx 86 str:i.ng operations) and devices such as ~ controllers, which are capable of generating consecutive address references at high speed. Block mode also oermits the transfer of a large anount of data through a small PS address subrange.
WINOOWS BLOCK MODE CCNSIS'lENCY CHEr!K Since the byte count and base displacement effectively predefine the transfer from the perspective of the 432 object, the IP can perform most of the required consistency checks when the window is opened. The only checks made during a transfer are direction and byte count. BI.
iAPX 432 Interface Processor Architecture Reference Manual Canpleting a block node write transfer which is shorter than the byte count is a two-step process. First, the AP must issue an ALTER MAP AND SELECl' DATA SEGmNI' function with the entry state operand to "force termination" on window o. This causes the IP to empty its FIFO to 432 menory. Then, the AP must issue an additional ALTER MAP AND SELECI' DATA SEG1EN.I' FUNcrICN with an entry state operand to set window 0 invalid (close the window).
WINOOWS BLOCK MODE ADDRESS ING mentioned earlier, in a block mode transfer the IP determines the displacement of a transf€r inbo the windowed object b¥ means of its on-chip displacement counter. Unlike random mode, then, the object displacement is independent of the subrange displacement. This gives rise to two addressing techniques that may be used by the Peripheral Subsystem in block mode: swept and source/sink.
iAPx 432 Interface Processor Architecture Reference Manual Byte ----------- 41 03 diSPlacement~ (7) (6) (5) (4) (3) 3 2 1 (2) 4 096 Windowed Subrange ------ (1) (0) Windowed Object T3 ! (Base Displacement) - Legend G) G) Reference Sequence: Subrange Address Referenced: 4,99 4100 4101 Write Byte write Byte write Byte Reference Operation: 3 4 5 Object Byte Accessed (disp.
Byte displacement, .....----,," ,,'- " " ,, (7)~ ,,,, (6) (5) (4) 4096 ( 3) Windowed Subrange (2) ""'- (1) Tf;Base ""'- ,~---~ (,) 1 Displacement) Windowed Object Legend Reference Sequence: Sub range Address Referenced: Reference Operation: Object Byte Accessed (disp.
iAPx 432 Interface Processor Architecture Reference Manual 3-5. INTE~ TRANSFERS Window 1 may be opened onto either the 432 memory space or the 432 processor-memory interconnect space. The address space is selected by the transfer JlDde attribute when window 1 is opened; it may be changed at any time ~ closing the window and re~pening it with the transfer mode set differently.
OiAPTER 4 FONcrIOOS This chapter describes the common facility that supports the execution of all Interface Processor functions. The first section shows hCM windCM 4 is used to provide access to the facility. The next section explains how a function is requested by writing operands and an o~""Ode through the windCM. The last two sections describe how the IP executes a requested function and returns status infonmation upon campletion of the operation. 4-1.
iAPX 432 Interface Processor Architecture Reference Manual Operands 9 (reserved) Opcode 8 Function State 7 Process Selection Index Processor Data Segment Figure 4-1 Function Request Area 4-2 6
FUNCTICNS IP WINDOWS 432 SYSTEM 0--------0 0 ---------0 0 ------0 -_ ---0 --- ---0 0 IP WINDOWS 432 SYSTEM --_~ IP _ _......... PROCESSOR DATA SEGMENT ---- DATA SEGMENTS .... ...
iAPX 432 Interface Processor Architecture Reference Manual 4-2. FUNCrICN REC.UFSTS The performance of a function may be considered fram the AP point of view as a sequence of three phases, as shown in figure 4-3. The IP controller, running on the AP, performs the first phase, requesting the execution of a function. The IP executes functions serially; requesting execution of ~ second function before ~ prior function has been completed produces an undefined result.
FUNCl'ICNS ••• Read function state Request Phase Write operands Write opcode I \ " Perform \ \ other \ \ processing,' - - - - - - - - - .I Interrupt • from IP ~ -I \ _ _ _ _ _ __ ~ Execution Phase I ,.-_-_-_~_ _...
iAPX 432 Interface Processor Architecture Reference Manual FUNCl'IOO OPERANDS Interface Processor function may require fran zero to seven
FONcrICNS 15 I ~~ , -J'I Short Ordinal ________ _______ ~y l~-------------(16-bit unsigned integer) 15 , I, : : : i : : : :v,------I : ::: ! : :] Bit Field l,------(Subfields defined by function) 15 l 21! ..
~ 432 Interface Processor Architecture Reference Manual 15 , p0000000000001Il~ \\ \\ Object Selector Operand d ° fO -Entere - - - -Access - - - -Segment - - - -Identl. - - -,l.er \ Access Descriptor Index \ --------- - -L- - - - - - -~\ \ r---~-----"'" L 1 L o 0 \(2) o 0 (1) o 0 UI> 0 \ ~----------~ Context Access Segment L ::L o o o ~------------ Entered Access Segment 1 Entered Access Segment : __ Entered Access Segment 3 J__ , 'Object Tab1~J \ Ma J '"..:. j>p~::.g-, o.
FUNcrIONS 4-3. FUNcrICN EXOCUTICN The IP per forms the actual execution of a function independent of the IP controller. Therefore the IP controller (an Attached Processor with associated IP control software) is free do other work after it has requested execution of a function (except that it must refrain from requesting a second function). Altr~ugh the IP's execution of any given function necessarily varies, figure 4-6 shows the basic sequence of steps that is common to most functions.
iAPX 432 Interface Processor Architecture Reference Manual Qualify Selected Process Decode Opcode no Perform operation Update destinations Update Return-value Update function completion state Gener~ 1nt:~J Figure 4-6 Basic IP Function Execution Flow 4-10
FUNCl'IONS Successful execution of a function typically causes the alteration of a destination operand (that is, an actual operand~ the operands field of the function request area is never changed by function execution). In addition, or alternatively, same functions produce a return-value. For example, the READ PR:CESSOR STATUS AND CLOCK function returns the current values of the IP' s system clock and status.
• n 'it' CHAPTER 5 PHYSICAL REEKRENCE MJOE The preceding chapters of this manual have Dmplicitly described the Interface Processor's logical reference node, its mrmal nnde of oper ation. The IP also provides ptzsical reference mode. Physical reference mode is distinguished rom logical reference mode by direct 24-bit base-plus-displacement addressing and a l~ited subset of functions.
iAPX 432 Interface Processor Architecture Reference Manual 5-2. PHYSICAL REFERENCE mDE ADDRESSING In physical reference mode the object reference attribute of a Upon window is replaced b¥ a 24-bit segment base address. recognition of a subrange address reference the IP determines the transfer displacement as in logical reference node. It forms the transfer address b¥ adding the displacement to the segment base address.
CHAPTER 6 FAULTS . This chapter describes IP faults, exceptional corrlitions which can occur as the IP performs functions. In general, the IP fault philosophy follows that of the GOP: the processor detects and contains faults so they do not affect other processes or processors in the 432 system. The response to a fault, i.e. fault handling, is not predefined and may be tailored through software to the needs of the 432 system user.
iAPx 432 Interface Processor Architecture Reference Manual The IP records fault information in various areas of IP process and processor objects (refer to Appendix A for detailed description of these fault information areas). There are three categories of IP operation in which faults may be generated: physical reference node, logical reference node, and window-mapped data transfer. Each of these modes utilizes specific fault information areas to report faults.
FAULTS· Context-Level Faults Context-level faults are the least severe of the IP logical node faults. A context-level fault arises fran exceptions which can be confined to the context in which the IP is operating. The IP may fault when attempting to execute a function or during the movement of data through one of the windows. One example of a context-level fault is the condition which occurs when a request to the function facility contains an erroneous function code.
iAPX 432 Interface Processor Architecture Reference Manual The fault port is serviced by a 432 fault handling process where one of four actions may be taken: o o o o Correct the reason for the fault and OOmplete any partially perfonmed function by completing the unfinished steps. Correct the reason for the fault, rewind any partially performed function steps, and then retry the function. Decide to reflect the process-level fault to the context-level. "Crash" the system.
FAULTS ., ~~ FLT "FATAL" ~~ ,~ FLT FLT FLT processor processor processor processor ipsor.psor ipsor .psor ipsor.psor ipsor.psor .4~ 4~ FLT FLT process process i prcs. prcs . ; prcs . prcs . .. FLT ~~ ~. FLT PRO CESSOR FAU LT ., FLT ~ context . es iprcs.ctxt.
iAPX 432 Interface Processor Architecture Reference Manual 6-2. FAULT HANDLING When an IP process encounters a process-level fault, it is autanatically sent to a 432 fault port to await service. A fault handling 432 process is designated to service the faulted processes waiting at the fault port. By design, IPs and GOPs share a cormnon base architecture, so IP faults may often be handled by software similar to that used to service GOP faults.
APPENDIX A SYSTEM OBJECT STRUCTURES The object structures of Interface Processors are described belOil. The only objects structures described are for those whose form or interpretation differ fran GOP object structures. Note that the values found in the length fields in the var ious objects descr ibed belOil are encoded as "actual length minus 1" in bytes.
iAPX 432 Interface Processor Architecture Reference Manual A context object is represented by a context access segment and an associated context data segment. Context Access Segments Diagranmatically, a context access segment is structured as shown belCM.
SYSTEM OBJECI'S STRUCIURES A- 2. PROCESS int Iroves, of course, as each instruction is executed because a new instruction is autanatically specified.
iAPX 432 Interface Processor Architecture Reference Manual entry = 1----------------1 = 12 11 = refined context access segment = 1 1----------------1 1 carrier AD -1---> 1----------------1 surrogate carrier 1 carrier AD -1---> current carrier 1----------------1 port AD -1---> current port 1----------------1 AD -1---> 1----------------1 current message 1----------------1 1 port AD -1---> 1----------------1 dispatching port 1 AD -1---> reserved 1----------------1 port AD -1---> fault port 1 ca
SYSTEM 0BJECrS STRUCTURES Process Data Segments The basic structure of a process data segment is shown below.
iAPX 432 Interface Processor Architecture Reference Manual The organization of the process status field is shown below.
SYSTEM. 0BJECl'S STRUClURES A- 3. PROCF.5SOR CBJECTS 432 Interface Processor consists of two cxx:>perating processing elements: a mapping facility and a function request facility. The mapping facility translates Peripheral Subsystem addresses into 432 system addresses. The function request facility executes the operator set described in Appendix B. The mapping facility and the function request facility can run in parallel.
iAPX 432 Interface Processor Architecture Reference Manual entry = 1----------------1 1 1 = 21 20 = process selection list = 1----------------1 1- 1 11- 1 1- -1 mapped -1 data segments -1 -1 1----------------1 1 AD -1---> 1----------------1 AD -1---> 1----------------1 1 AD -1---> 1----------------1 port AD - 1---> 1----------------1 1 carrier AD -1---> 1----------------1 carrier AD -1---> 1----------------1 reserved reserved reserved normal port surrogate carrier normal carrier port AD -!
SYSTEM 0BJECrS STRUCTURES The base descriptor base type field of a rights field of a processor access segment access is interpreted in the same manner as for all objects of access segment.
iAPX 432 Interface Processor Architecture Reference Manual double byte = displacement = 1----------------1 = processor data segment control window area = 14 1----------------1 reserved 1----------------1 ! cur. prcs idx. 1 1----------------1 1 psor status 1 1----------------1 - - > ! object lock ! a 1----------------1 The processor status field is shown below.
SYSTEM 0BJECl'S STRUCl'URFS The stowed bit is interpreted as follows: o - running I - stopped The broadcast acceptance mode bit is interpreted as follows: o- broadcast interprocessor messages are not being accepted and acknowledged I - broadcast interprocessor messages are being accepted or acknowledged Note that the processor ID fields in the processor data segment and the local oorrmunication segment are filled in by the associated processor at initialization time from externally read information.
LAPX 432 Interface Processor Architecture Reference Manual double byte = = displacement 1----------------1 80 = reserved = 1----------------1! ! = processor fault information 77 = !----------------1 1----------------1 1 selected idx. 1----------------1 64 1 selected state ! 63 = mapping facility fault information 62 65 = 1 52 1----------------! 1 = mapping facility = 28 1----------------1 1 reserved 1 27 1----------------! 1 IPC fun. req.
SYSTEM 0BJECrS STRUCl'URES Peripheral Subsystem State Field The organization of the Peripheral Subsystem state field is shown belCM. 1 12 bits lxlxxlxl 1 1 1 1-- write sample delay 1--- xack delay 1------- interrupt inhibit reserved ! 1 1------------- The write sample delay field and the xack delay field program the characteristics of the IP conponent interface to the Peripheral Subsystem. See the iAPx 43203 VI..SI Interface Processor Data Sheet, Order Number 171874-001 for details.
iAPX 432 Interface Processor Architecture Reference Manual Alarm, Dispatching, and Reconfiguration State Fields The alarm, dispatching ("select process"), and reconfiguration state fields are used to indicate that the processor has responded to that type of signal and signalled the associated Peripheral Subsystem via interrupt. Each has the following organization.
SYSTEM 0BJECl'S STRt.CIURES Function State Field The function state field is used to describe the current state of the function request facility. It has the following organization.
iAPX 432 Interface Processor Architecture Reference Manual current status information. When operands are read from this subr ange or wr i tten into this subr ange, the processor data segment is accessed. Data written into the part of the subrange representing the function request facility is captured when no function is in progress. During function execution, Attached Processor software must not make further function requests.
SYSTEM OBJECTS STRUCTURES Above the block transfer information, a copy of the information contained in each of the processor-resident map entr ies (0 through 4) is represented by a data structure with the following organization. = double byte 1----------------1 displacement 1 base disp. 4 1----------------1 1 mask 1 1--------7-------1 base address 1----------------1 1 entry state 1 a 1----------------1 = = = The entry state field is used to describe the current state of the given map entry.
iAPX 432 Interface Processor Architecture Reference Manual The 2-bit transfer direction subfield indicates the types of read/write requests from the associated Peripheral Subsystem which are valid with respect to this map entry.
SYSTEM OBJECl'S STRUCTURFS The base displacement field contains the byte displacement into the 432 segment used to construct a refinement of a data segment. See Figure 3-2 for an illustration of the role of a window's base displacement in forming a refinement. Mapping Facility Fault Information Area The mapping facili ty fault information area consists of an entry fault code and fault displacement pair for each map entry. Diagranmatically, the fault information for each map entry appears as shown beiCM.
iAPX 432 Interface Processor Architecture Reference Manual The I-bit segment bound subfield indicates whether or not the associated fault was caused by a segment bounds violation. A value of zero indicates that the fault was not caused by a segment bounds violation. A value of one indicates that the fault was caused by a segment bounds violation. The I-bit menory overflaY subfield indicates whether or not the associated fault was caused by a memory overflow.
SYSTEM 0BJECrS srRUCTURES Selected Index and Selected State Fields The selected index and selected state fields are filled in by the processor fram information found in the process carrier data segment at process selection time, i. e when a "select process" IPC is received. The selected index is a process selection index used to conmunicate to Attached Processor software which process from the process selection list has just been bound to the processor.
iAPX 432 Interface Processor Architecture Reference Manual 4 - Clear broadcast acceptance mode 5 - Flush object table 6 - Suspend and fully requalify processor 7 - Suspend and requalify processor 8 - 14 - Unused 15 - Close (Invalidate) Windows and Unlock I/O Locks (on windows 0-3) 16 - Generate PS Reset 17 - Close (Invalidate) Windows and Unlock I/O Locks (on windows 0-3) and Enter Physical Mode The base rights of a corrmunication segment access descriptor are interpreted in same manner as for all segments
APPENDIX B FUNcrIOO SUMMARY Ap;>endix B sumnarizes the Interface Processor functions. Three lists are provided to assist in locating the page which contains a particular functioo description. One list, Table B-1, organizes the function set by alphabetical order. Table B-2 organizes the function set by increasing function code number and is -r;>articularly useful when debugging IP controller software.
iAPx 432 Interface Processor Architecture Reference Manual TABLE B-1 ALPHABEl'ICAL INDEX TO IP FUNcrICNS HEX FUNcrICN NAME (Logical Mode Functions) ALTER MAP AND SEI..
FUNCTIOO SUMMARY 'mBLE B-2 IP FUNcrICN SUMMARY BY FUNcrICN CODE HEX FUNCTICN CDDE FUNCrICN NAME 00 01 02 03 04 05 06 07 08 09 OA OB OC OD OE OF 10 11 12 13 14 15 16 17 18 19 (Logical Mode Functions) ALTER MAP AND SELECr DATA SEGiENI' SEND TO PKOSSOR SET PERIPHERAL SUBSYSTEM ~DE READ P~SSOR STATUS AND CLOCK CDPY ACCESS DESCRIPTOR NUIL ACCESS DESCRIPTOR ENl'ER GLCBAL ACCESS SEGiENI' EN'lER ACCESS SEG1ENI' AMPLIFY RIGHTS RESrRIcr RIGHTS RErRIENE TYPE REPRESENI'ATICN REl'RIEVE PUBLIC TYPE REPRESENTATICN RE
iAPX 432 Interface Processor Architecture Reference Manual TABLE B-3 IP FUNCl'ICN SUMMARY BY OPERATOR ID DEX::IMAL OPERATOR ID FUNcrIOO NAME 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 22 24 25 26 27 28 29 3 4 5 6 B-4 (logical Mode Functions) ALTER MAP AND SELECT DATA SEG1ENI' SEND TO PROCESSOR SRI' PERIPHERAL SUBSYSTEM MDE READ PROCESSOR STATUS AND CLOCK (Dpy AOCESS DESCRIPTOR NUIL ACCESS DESCRIPl'OR ENl'ER GLCBAL ACCESS SEG1ENI' EN'IER ACCESS SEGviENI' AMPLIFY RIGHTS RFSrRICl' RIGHTS RErRIE
FUNCl'IOO StM1ARy FUNCl'ICN 'IEMPIA'IE Operator ID: ID Contents 1------------------------1 1 reserved 1 1------------------------1 1 reserved 1------------------------1 oper and 5 1 reserved . 1 1------------------------1 operand 4 1 reserved 1------------------------1 oper and 3 1 reserved 1------------------------11 oper and 2 1 reserved 1------------------------1 operarrl I 1 reserved 1------------------------1 oper and 0 1 reserved 1------------------------1 function code 1 OXXH (FUNCl'ICN NAME) .
iAPX 432 Interface Processor Architecture Reference Manual ALTER MAP AND SELECr DATA SEGmNI' Operator ID: 3 Contents results 0 through operand operand operand operand operand Function Request Facility 9 1------------------------1 1 reserved 1 1------------------------1 6 1 BLOCK COON!' 1------------------------1 5 1 BASE DISPIACEMENI' 1------------------------1 4 1 SOURCE OBJECl' SELECTOR 1 !------------------------! 3 ! MASK 1------------------------1 2 1 BASE ADDRESS 1 operand 1 oper and 0 IP function
FUNCrlOO SUMMARY ArlIER MAP AND SELECI' PHYSICAL SEG1ENI' Operator ID: 3 Contents results 0 through oper am operam operand operarrl operam oper am oper am Function Request Facility 9 1------------------------1 1 reserved 1------------------------1 6 1 reserved 5 1------------------------1 IPHYSICAL ADDRESS (high 8) 1 1------------------------1 4 IPHYSICAL ADDRESS (low 16) 1 1------------------------1 3 1 MASK 1------------------------11 2 1 BASE ADDRESS 1------------------------1 1 1 ENrRY STATE 1-------
iAPX 432 Interface Processor Architecture Reference Manual AMPLIFY RIGHTS Operator 10: 11 Contents results 0 through 9 operarrl 6 oper arrl 5 operand 4 operand 3 operand 2 operand I operand 0 IP function code function state process selection index Function Request Facility 1------------------------1 1 reserved 1------------------------1 1 reserved 1------------------------1 1 reserved 1------------------------1 1 reserved 1------------------------1 1 reserved 1------------------------1 1 reserved 1---
FUNCl'ICN Sl:M-1ARY BroAOCAST TO POCCESSORS Operator ID: 27 Contents results I through 9 result 0 Function Request Facility 1------------------------1 1 reserved 1 1------------------------1 1 BOOLEAN Hex Byte Offset 22H-33H 20H oper and 4 1------------------------1 1 reserved 1------------------------1 1 reserved 1 1------------------------1 1 reserved lAH oper and 3 1------------------------1 1 reserved 1 ISH oper arrl 6 operarrl 5 operand 2 1------------------------1 1 reserved 1 operand I
iAPX 432 Interface Processor Architecture Reference Manual
FUNCrIOO Sm.f.
iAPX 432 Interface Processor Architecture Reference Manual DESCRIPTOR Operator 10: 7 COpy ACCESS Contents Function Request Facility results 0 through 9 oper and 6 operand 5 oper and 4 operand 3 • operand 2 1------------------------1 ! reserved ! 1------------------------1 1 reserved 1------------------------1 1 reserved 1------------------------1 1 reserved 1------------------------1 1 reserved 1------------------------1 1 reserved 1 1------------------------1 oper and 1 1 SOURCE CBJECl' SELECI'OR
ACCESS SEG1ENI' Operator ID: 10 EN'lER Contents Function~est Hex Byte Offset Facility oper and 3 1-----------------------! reserved 1-----------------------! reserved 1-----------------------1 reserved 1------------------------, 1 reserved 1-----------------------1 reserved operand 2 1 reserved results 0 through 9 operand 6 operand 5 oper and 4 operand 1 oper and 0 IP function code function state process selection index 1-~---------------------- 1-----------------------1 SOURCE ClI3J'ECI' SELEC
iAPX 432 Interface Processor Architecture Reference Manual ENrER GLOBAL AOCESS SEG1Em' Operator ID: 9 Contents Function Request Facility 9 11------------------------1 reserved 1 1------------------------1 oper am. 6 1 reserved 1 1------------------------11 oper am. 5 1 reserved 1------------------------1 oper and 4 1 reserved 1------------------------1 oper arrl 3 1 reserved 1-----------------------oper am.
FUNCTICN SUI+1ARY INDIVISIBLE ADD SHORI' ORDINAL Operator ID: 28 Contents 1------------------------1 ! reserved 1 1------------------------1 result 0 ! ORIGINAL VALUE 1------------------------1 oper and 6 1 reserved 1------------------------1 operand 5 ! reserved 1------------------------1 oper and 4 1 reserved 1------------------------1 oper and 3 1 reserved 1------------------------1 oper and 2 1 VALUE 1------------------------11 operand I 1 DISPLACEMENT 1------------------------1 oper and 0 ! SOURCE O
iAPx 432 Interface Processor Architecture Reference Manual INDIVISmLE INSERr SHORT ORDINAL Operator ID: 29 Contents 11------------------------1 reserved 1------------------------1 result 0 1 ORIGINAL VALUE 1 1------------------------1 oper am 6 ! reserved 1------------------------1 operand 5 1 reserved 1------------------------1 operand 4 1 reserved 1------------------------1 operand 3 1 MASK 1------------------------1 operand 2 1 VALUE 1 1------------------------1 operand 1 1 DISPIACEMENr 1-------------
FUNcrICN St.
iAPX 432 Interface Processor Architecture Reference Manual INSPECr AOCESS DESCRIPTOR Operator ID: 17 Contents results results Hex Byte Offset Function Request Facility 2 through 9 1------------------------1 1 reserved 1------------------------1 1 SOURCE ACCESS 0 through 1 1 DESCRIPTOR IMAGE 1------------------------1 operand 6 1 reserved 1------------------------1 operand 5 1 reserved oper and 4 operand 3 operand 2 operand I operand 0 IP function code function state process selection index 24H-3
FUNcrION SUMMARY ~K 0BJECl' Operator ID: 19 Contents results 1 through 9 result 0 operam 6 oper am 5 oper am 4 oper am 3 operam 2 operand 1 operand 0 IP function code function state process selection index Function Request Facility 1------------------------1 1 reserved 1 1------------------------1 1 BOOLEAN 1 1------------------------1 1 reserved 1 1------------------------1 ! reserved 1------------------------1 1 reserved 1 1-----------------~------1 1 reserved 1 1------------------------"! 1 reserve
iAPX 432 Interface Processor Architecture Reference Manual NULL AOCESS DESCRIPTOR Operator ID: 8 .
READ P~OR STATUS AND cra:K (IDgical and Physical Mode) Operator ID: 6 Contents Function Request Facility Hex Byte Offset IP function code 1------------------------1 1 reserved 1------------------------1 1 SYSTEM cra:K 1 . .
iAPX 432 Interface Processor Architecture Reference Manual ~IVE Operator ID: 23 Contents results 0 through 9 oper am 6 operam 5 oper and 4 operand 3 operand 2 oper and I oper and 0 IP function code function state process selection index Function Request Facility 1------------------------1 1 reserved .1------------------------1.
FUNcrION S~ RESl'RIcr RIGHTS Operator ID: 12 Hex Byte Contents results 0 through 9 Offset 1------------------------1 1 reserved 20H-33H oper and 4 1-----------------------1 reserved 1-----------------------1 reserved 1-----------------------1 reserved oper and 3 1------------------------1 1 reserved ! oper and 6 oper and 5 IP Function Request Facility 1-----------------------oper and 2 1 reserved 1-----------------------operand 1 1 DESC crRL Cl3J SELECrOR 1-----------------------operand OLDES
iAPX 432 Interface Processor Architecture Reference Manual REl'RIEVE PUBLIC TYPE REPRFSENI'ATICN Operator ID: 14 Contents results 0 through 9 oper and 6 oper am 5 oper am 4 oper am 3 Hex Byte Offset Function Request Facility 1------------------------1 1 reserved 1------------------------1 1 reserved 1------------------------1 1 reserved 1------------------------1 1 reserved 1------------------------1 1 reserved 1-----------------------1 TYPE DEF OBJ SELECI'OR 1-----------------------operand 1 1 SOURCE
FUNcrIOO St.
iAPX 432 Interface Processor Architecture Reference Manual REI'RI1WE REFINED CBJEcr Operator ID: 16 Contents 1------------------------1 ! reserved ! 1-----------------------operand 6 1 reserved 1-----------------------oper and 5 1 reserved 1-----------------------oper and 4 1 reserved 1------------------------1 oper and 3 1 reserved 1------------------------1 operand 2 1 REFIN crRL CBJ SELECrOR' 1-----------------------oper and I 1 SOURCE 0BJECl' SELECrOR 1-----------------------operand OlDEST OBJECI' S
RErRIEVE TYPE DEFINITICN Operator ID: 15 Contents results 0 through 9 Function Request Facility Hex Byte Offset 1------------------------1 1 reserved 1 20H-33H 6 1-----------------------1 reserved 1-----------------------oper am 5 1 reserved 1-----------------------oper and 4 1 reserved 1------------------------1 oper and 3 ! reserved 1------------------------! oper am 2 1 reserved !------------------------I oper and 1 ! SOURCE CBJECl' SELECrOR 1-----------------------oper and OlDEST OBJECI' SELECrOR
iAPX 432 Interface Processor Architecture Reference Manual SEND Operator ID: 21 Contents Function Request Facility 9 11------------------------1 reserved 1------------------------1 oper and 6 1 reserved 1 1------------------------1 oper am 5 1 reserved 1------------------------1 operand 4 1 reserved 1 1------------------------1 operand 3 ! MESSAGE 0BJECl' SELECI'OR! 1------------------------1 operand 2 1 reserved 1------------------------1 operand 1 1 reserved 1------------------------1 operand 0 1 POR
FONcrION Sl.
iAPX 432 Interface Processor Architecture Reference Manual SEND TO PRX:ESSOR (Physical· Mode) Operator ID: Contents results 1 through 9 result 0 oper and 6 oper and 5 oper and 4 operand 3 operand 2 operand 1 operand 0 IP function code function state process selection index 4 Hex Byte Offset Function Request Facility 1------------------------1 1 reserved 1 1------------------------1 1 BOOLEAN 1------------------------1 1 reserved 1-----------------------1 reserved 1-----------------------1 reserved 1--
FUNcrIOO SUl+1ARY SEI' PERIPHERAL MODE (logical and Physical Mode) Operator ID: 5 SUBSYSTEM Contents results 0 through 9 oper and 6 oper and 5 operand 4 operand 3 operand 2 operand I operand 0 IP function code function state process selection index Function Request Facility 1------------------------1 1 reserved 1 1------------------------1 1 reserved 1------------------------1 1 reserved 1------------------------1 1 reserved 1 1------------------------1 1 reserved 1------------------------1 1 reser
iAPx 432 Interface Processor Architecture Reference Manual StJRROGATE ROCEIVE Operator ID: 26 Contents results 0 through oper am oper am oper am operarrl Function Request Facility 9 11------------------------1 reserved 1------------------------1 6 1 reserved 1 1------------------------1 5 1 reserved 1------------------------1 4 1 reserved 1------------------------1 3 1 reserved 1------------------------1 operand 2 1 CARRIER 0I3J'ECI' SELECl'ORI Hex Byte Offset 20H-33H 1EH lCH lAH l8H l6H 1--------~
FUNcrICN S~ SURroGA'lE SEND Operator 10: 25 Contents Function Request Facility 9 11-----------------------reserved 1-----------------------oper and 6 . 1 reserved 1-----------------------oper and 5 1 reserved 1-----------------------oper and 4 1 reserved 1-----------------------operand 3 1 MESSAGE CBJECl' SELECl'OR.
iAPX 432 Interface Processor Architecture Reference Manual UNLOCK 0BJECr Operator 10: 20 Contents resul ts 0 through 9 operand 6 oper and 5 operand 4 oper and 3 oper and 2 operand I operand 0 IP function code function state process selection index Function Request Facility 1-----------------------! reserved 1-----------------------1 reserved 1-----------------------1 reserved 1-----------------------1 reserved 1-----------------------1 reserved 1-----------------------1 reserved 1----------------------
APPENDIX C FAULT SUMMARY C-l. FAULT REPORTING Both logical ana physical mode faults are reported in fault information areas as descr ibed belON. The faul t information area for oontext, process, and processor level faults has the same organization. Process objects contain fault information for context and process level faults which occur in logical node. Processor objects contain fault information for processor level faults which occur in logical node.
iAPX 432 Interface Processor Architecture Reference Manual = double = fault information area byte 1 displacement 1----------------1 1 execution statel n+12 1----------------1 1 operator id 1 1----------------1 1 system tbner 1 1----------------1 1 psor status 1----------------1 1 cxt/prcs statusl 1----------------1 1 PS status 1 1---------------fault code 1---------------1 fault os/disp 1---------------1 pelk buffer .1----------__----1.
FAULT SUMMARY The Peripheral Subsystem status, context/process status, processor status, and system timer fields contain the values of the the corresponding on-chip registers at the time of the fault. The o:perator id, which differs fran the opcode field in an instruction, specifies the operator that causes the fault. If a fault occurs during instruction decoding, the operator id is zero. The operator id value of each operator is the same as the index found in Appendix B.
iAPX 432 Interface Processor Architecture Reference Manual The W field specifies whether the fault was on a read or write access. A value of zero indicates a read access. A value of one indicates a write access. The faulted displacement is recorded in the fault displacement (in access memory, or interconnect), and in the object index field of the fault object selector (in access access segment).
FAULT SUMMARY The The TT TT and EEEE fields specifY the fault level and the fault type. bits are interpreted as follows: TT Description 00 01 10 Context Level Faults Process Level Faults (group 1) Process Level Faults (group 2) Processor Level Faults 11 There are 16 fault types within each of the 4 groups. The encoding column of the tables in the following sections contains the TT and EEEE fields if the type is FF (all other faults). C- 3.
iAPX 432 Interface Processor Architecture Reference Manual Sub-operations Faults FAULT GroUPS !TYPE! ENmDING Sbore Access Descriptor Faults => Level Fault Destination Delete Rights Fault Memory Overflow Fault Read/Write Rights Fault Faults Faults Faults Faults 01 0100 01 0011 FF FF TS TS FF FF 01 0000 01 0001 00010111 00011111 01 1011 01 0110 .
FAULT S{Mt1ARY Operator Faults OPERATOR Alter Map and Select Data Segment Interconnect Descriptor Fault I/O Lock Fault Transfer Direction Fault Length Validity Fault Window Subrange Overlap Fault lnoamplete Block Transfer Fault Operand Validity Fault Forced Termination Fault ! TYPE! ENOODING I FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 0100 0101 0110 0111 1000 1001 1010 1011 FF 01 0011 FF 01 0110 00001011 Oopy Access Descriptor => Store Access Descriptor Faults Null Access Descriptor Destina
iAPX 432 Interface Processor Architecture Reference Manual Retrieve Refined Object Refinement Control Object System Rights Fault => Object Qualification Faults (Refinement Ctl Obj) Source Object Validity Fault Type Fault => Store Access Descriptor Faults FF TS FF FF 01 0110 00001100 01 0101 01 1000 FF 01 0101 Lock Object => Object Qualification Faults (data segment) Source Object Access Rights Fault FF 01 0110 Unlock Object => Object Qualification Faults (data segment) Source Object Access Rights Fa
FAULT S'f.M.
iAPX 432 Interface Processor Architecture Reference Manual C-4. tOCN- INSTIUCTICN INTERFACE FAULTS OPERATOR Initialization => => Object Qualification Faults (processor AS) => Object Qualification Faults (object table directory) => Object Qualification Faults (processor OS) Processor Object Lock Fault => IPC Faults Base/Mask Incampatibality Fault IPC Faults => => Object Qualification Faults (Cammo Segment) Communication Segment Lock Fault Response Count Fault .
] APPENDIX D INTERRUPT HANDLING Whenever the Interface Processor detects an event that may require attention from the IP controller, it records the nature of the event in the current IP processor data segment and e.mi ts a pulse on 1. ts interrupt line. There are several different types of events which may be sources of interrupts, and their occurrence and timing is not necessar ilv predictable. In this sense IP interrupts are similar to several I/O devices that are wire-DRd to a cammqn interrupt line.
iAPX 432 Interface Processor Architecture Reference Manual Mask IP interrupt Reset latch Save interrupted environment Enable higherpriority .
INTERRlJPI' HANDLING The central logic of this approach assumes that there is a "list" of poosible interrupt sources to be scanned, and that passing through this list may uncover one (the usual case), multiple, or zero events that require responses. To illustrate the second two cases, assume that the possible events are labelled A through K, and that the interrupt handler tests for A, then B, and so on. Assume also that event B occurs follCMed quickly by event J.
iAPX 432 Interface Processor Architecture Reference Manual Table 0-1 Interrupt Sources Processor Data Segment Subfield Value Event OOOOs Function completion state subfield Function completed normally (this interrupt may be masked) Function state field OIB lOs lIB Entry state field (One Fault level subfield Context-level fault Process-level fault Processor-level fault per map entry) Transfer OIB Transfer lOs Transfer lIB Transfer state subfield terminated by byte count(l) termination forced(1,3)
APPENDIX E SYSTEM INITIALIZATICN System initialization may be considered as a sequence of activities that brings a 432-based system from an arbitrary state to a known state where execution can begin. Although the initialization sequence will vary widely among applications, this appendix outlines the basic procedure. The first section describes how the system may be reset to a krnm state.
iAPX 432 Interface Processor Architecture Reference Manual An Interface Processor responds to an INIT pulse by aborting any current operation, entering physical reference mode, configuring its windows as shown in table E-l, clear ing broadcast acceptance node, and then issuing an interrupt request to its Attached Processor.
SYSTEM INITIALIZATION ~ L .... ,... .... ..., (Processor Number n) Storage Descriptor (n) Processor Object Processor Object :: ~ ~~ (Processor Number (1) Storage Descriptor ([I) Object Table Header 1) .....
iAPX 432 Interface Processor Architecture Reference Manual Note that the term "processor obj ect" above is meant to include ccmnunication segments, am a processor carrier, in addition to processor access and data segments. Likewise, "process object" includes a domain, instruction segments, context objects, etc. This environment may be extended to include nnre processors, processes, ports and so on, as is appropriate for a given application.
SYSTEM INITIALIZATION Before any function request is made by the IP, enough 432 memory This is necessary must be initialized to allCM Ip· execution. because the IP will attempt to update the segment maWed by windCM 4 in response to the function request.
iAPX 432 Interface Processor Architecture Reference Manual Having established its identity, the processor proceeds to locate its processor object. It does this by assuming that the initial object table directory is located at physical mennry address 8 (see figure E-I). A segment header field of eight bytes precedes the initial object table directory. It further asstmles that the first storage descriptor in the directory locates an object table containing storage descriptors for processor objects.
SYSTEM INITIALIZATION Table E-l Window Configuration Following !NIT Attt"ibute WindCM 0 Window 1 WindCM 4 Window Status Open Open Open Transfer Mode Block Interconnect Random Subrange Base Address 07EOOH 08000H 07FOOH Subrange Size OOIOOH 08000H OOIOOH Segment Base 0 0 0 Segment Length 65,535 65,535 65,535 Direction Write Read/Write Read/Write Transfer State In Progress In Progress In Progress Overlay Yes Yes Yes E-7
APPENDIX F INTERPROCESS CCMruNICATICN AND DISPA'lCHIt.;x; EXAMPLE In Chapter 1, a printer example was used to demonstrate the flow of data between 432 processes and AP tasks. In this appendix, the printer example is again discussed. However, this time the view taken is that of a programmer writing an Attached Processor task to direct an IP to accomplish printer output.
iAPX 432 Interface Processor Architecture Reference Manual IP 432 OBJECTS CONTEXT IP PROCESSOR OBJECT IP DISPATCHING PORT PRINT REQUEST PORT PRINT OBJECT 432 PROCESS Figure F-l Print Example Objects F-2 AP PHYSICAL PROCESSORS
INTERPIO::FSS mHlNlCATICN AND DISPA'lCHING EXAMPLE Procedures in the utilities section demonstrate how a programmer can construct facilities to invoke IP functions. Recall from the function sunmary in Aweooix B that an AP requests an IP function by writing a process selection index, all required operands, and finally depositing a function code into the appropriate slots in the function request facility (frf). The IP begins execution of the function only after the function code has been written.
iAPX 432 Interface Processor Architecture Reference Manual Printer task: Procedure: /*****~******************************************/ /* /* /* Data Structures and Constants */ */ */ /************************************************/ /**************************************************************************************/ /* Declare the 256 byte structure for the Control Window and map it beginning at */ /* an offset of 07FOOH into the 64K byte segment which is reserved for the IP.
INTERPR:nSS C(l.MJNICATICN AND DISPATCHING EXAMPLE /**************************************************************************************/ /* Seven object selectors are required. One for the message slot in the COntext */ /* Acx:ess Segment, sioce this is where the hardware will put the Access /* Descriptor (AD) for the Print Request Message following the Receive instruction. */ */ ~ ~ for the Print Request Port am one for the Print Reply Port.
iAPX 432 Interface Processor Architecture Reference Manual Dispatch: Procedure~ /**********************************************************************************/ /* This procedure hangs the IP's processor carrier on the IP's dispatching */ /* port. This allcws blocking sends and receives to be h a n d l e d . * / 1* This example assumes that the IP processor carrier blocks at the dispacthing */ /* port. No "select process" IPC is received if the Surrogate Receive does not */ /* block.
INTERPRXESS exM-UNICATICN AND DISPA'ICHING EXAMPLE Get-print_message: Procedure: /**********************************************************************************/ /* Attempt to Receive a message fran the Print Request Port, Figure F-2 */ /**********************************************************************************/ W~ndow_4.frf-prcs_idx = process_l; Wl.rrlow_4. frf_operand (0) = requestJ'Ort_obj_sel: Window_4.frf_operator = Ol4H: /* Use process obj ect 1. /* port /* Receive function code.
iAPX 432 Interface Processor Architecture Reference Manual Clooe wirrlow: ProCedure~ /**********************************************************************************/ /* Close windCM, note only ~ operarrls are Ie<;uired. */ /**********************************************************************************/ Window_4.frf-prcs_idx Window 4. frf operand (0) Window-4.frf-operand(1} Window:4.
INTERP:rocESS CGMJNICATICN AND DISPATCHING EXAMPLE Return-print_message: Procedure; /**********************************************************************************/ /* Sem message to Print Reply Port. See Figure F-6 */ /**********************************************************************************/ W~ndow_4.frf-prcs_idx = process 1; Window 4.frf.operand(O) Window-4.frf operand(l) Window=4.frf=operator If = replY-PQrt_obj_sel; = message obj sel; = 016H; - ~imow_4.
iAPX 432 Interface Processor Architecture Reference Manual /************************************************/ ~ P /* Initialization */ /* */ /*****************************************k******/ Call Disable_Interrupts: /* Busy waiting will be used, not the interrupt mechanism /* Also assume that 00 faults will occur */ */ Call Dispatch ~ /************************************************/ P /* Print Driver Body /* ~ */ */ /************************************************/ /* loop forever */ Ca
INTERPROCESS a::MruNICATIGl AND DISPAroIING EXAMPLE IP DISPATCHI G PORT IP --EJ ~.
iAPX 432 Interface Processor Architecture Reference Manual IP DISPATCHING PORT IP C~ CARRIER - .:- "c, / ~/ -.tIo 4 IP PROCESS IP PROCESSOR OBJECT / ~~/ ~ /~
INTERP~S ~ICATIrn AND DISPATCHING EXAMPLE ;' INTERRUPT ,----, ... 1/ IP DISPATCHING PORT SELECTED STATE -- (- IP A.
iAPX 432 Interface Processor Architecture Reference Manual IP r ~ EJ ~ WINDOW "ALTER MAP AND SELECT DATA SEGMENT" function IP PROCESS - PRINT REQUEST PORT ,fA PRINT REPLY PORT CARRIE' (~ 432 PROCESS III' ~ PRINT OBJECT Figure F-S Window Manipulation F-l4
INTERPRXESS
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