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Document Number: 336464-001

8th Generation Intel

Processor

Family for S-Processor Platforms

Datasheet, Volume 1 of 2

October 2017

Revision 001

Summary of content (155 pages)

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8th Generation Intel® Processor Family for S-Processor Platforms Datasheet, Volume 1 of 2 October 2017 Revision 001 Document Number: 336464-001
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Legal Lines and Disclaimers You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.
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Contents 1 Introduction ............................................................................................................ 10 1.1 Supported Technologies ..................................................................................... 12 1.2 Power Management Support ............................................................................... 12 1.2.1 Processor Core Power Management........................................................... 12 1.2.2 System Power Management .................
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2.5 2.6 2.4.7 GT2 Graphic Frequency ...........................................................................35 Display Interfaces ..............................................................................................36 2.5.1 DDI Configuration ...................................................................................36 2.5.2 eDP* Bifurcation .....................................................................................37 2.5.3 Display Technologies ................................
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4.3 4.4 4.5 4.6 4.7 5 4.2.5 Package C-States ................................................................................... 69 4.2.6 Package C-States and Display Resolutions ................................................. 72 Integrated Memory Controller (IMC) Power Management ........................................ 72 4.3.1 Disabling Unused System Memory Outputs ................................................ 72 4.3.2 DRAM Power Management and Initialization .....................................
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5.3 S-Processor Line Thermal and Power Specifications ................................................92 5.3.1 Thermal Profile for PCG 2015D Processor ...................................................93 5.3.2 Thermal Profile for PCG 2015C Processor ...................................................94 5.3.3 Thermal Profile for PCG 2015B Processor ...................................................95 5.3.4 Thermal Metrology ..................................................................................
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2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 3-1 4-1 4-2 4-3 4-4 5-1 5-2 5-3 5-4 5-5 5-6 5-7 7-1 9-1 9-2 9-3 Interleave (IL) and Non-Interleave (NIL) Modes Mapping............................................. 24 PCI Express* Related Register Structures in the Processor ........................................... 27 Example for DMI Lane Reversal Connection ............................................................... 29 Video Analytics Common Use Cases ........................................................
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2-24 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 8-1 8-2 9-1 8 Supported Resolutions1 for HBR2 (5.4 Gbps) by Link Width.........................................45 System States........................................................................................................63 Processor IA Core / Package State Support ....................
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Revision History Revision Number 001 Description • Initial release Revision Date October 2017 §§ Datasheet, Volume 1 of 2 9
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Introduction 1 Introduction The 8th Generation Intel® Processor Family for S-Processor is built on 14-nanometer process technology. The S-Processor Line is offered in a 2-Chip Platform. See Figure 1-1. The following table describes the processor lines covered in this document. Table 1-1. Processor Lines Processor Line1 Package Base TDP S-Processor Line (DT) LGA1151 65W, 95W Processor IA Cores Graphics Configuration 6 GT2 4 GT2 Platform Type 2-Chip Notes: 1.
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Introduction Figure 1-1. S-Processor Line Platform PCI Express* 3.0 x 16 DDR Ch. A Digital Display Interface x 3 DDIx3 embedded DisplayPort* eDP* Cameras Touch Screen Fingerprint Sensor DDR4 System Memory DDR Ch. B PECI SMBus EC DMI 3.0 USB 2.0 BIOS/FW Flash SPI/ I2C/ USB2 eSPI / LPC PTT USB 2.0 USB 2.0/3.0/3.1 PCH USB 2.0/3.0/3.1 Ports SATA SSD Drive HDA/I2S HD Audio Codec PCI Express* 3.0 x20 GPIO USB 2.0 SMBus 2.
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Introduction 1.1 Supported Technologies • Intel® Virtualization Technology (Intel® VT) • Intel® Active Management Technology 11.0 (Intel® AMT 11.0) • Intel® Trusted Execution Technology (Intel® TXT) • Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) • Intel® Hyper-Threading Technology (Intel® HT Technology) • Intel® 64 Architecture • Execute Disable Bit • Intel® Turbo Boost Technology 2.
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Introduction 1.2.2 System Power Management • S0/S0ix, S3, S4, S5 Refer to Chapter 4, “Power Management” for more information. 1.2.3 Memory Controller Power Management • Disabling Unused System Memory Outputs • DRAM Power Management and Initialization • Initialization Role of CKE • Conditional Self-Refresh • Dynamic Power Down • DRAM I/O Power Management • DDR Electrical Power Gating (EPG) • Power training Refer to Section 4.3 for more information. 1.2.4 Processor Graphics Power Management 1.2.4.
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Introduction 1.3 Thermal Management Support • Digital Thermal Sensor • Intel Adaptive Thermal Monitor • THERMTRIP# and PROCHOT# support • On-Demand Mode • Memory Open and Closed Loop Throttling • Memory Thermal Throttling • External Thermal Sensor (TS-on-DIMM and TS-on-Board) • Render Thermal Throttling • Fan speed control with DTS • Intel Turbo Boost Technology 2.0 Power Control Refer to Chapter 5, “Thermal Management” for more information. 1.4 Package Support • The processor is available in A 37.
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Introduction Table 1-2.
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Introduction Table 1-2. Terminology (Sheet 3 of 3) Term PEG Description PCI Express Graphics PL1, PL2, PL3 Power Limit 1, Power Limit 2, Power Limit 3 Processor The 64-bit multi-core component (package) Processor Core The term “processor core” refers to Si die itself, which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256KB L2 cache. All execution cores share the LLC.
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Introduction Table 1-3. Related Documents (Sheet 2 of 2) Document Document Number High Definition Multimedia Interface specification revision 1.4 http://www.hdmi.org/ manufacturer/specification.aspx Embedded DisplayPort* Specification revision 1.4 http://www.vesa.org/ vesa.standards/ DisplayPort* Specification revision 1.2 http://www.vesa.org/ vesa.standards/ PCI Express* Base Specification Revision 3.0 http:// www.pcisig.
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Interfaces 2 Interfaces 2.1 System Memory Interface • Two channels of DDR4 memory with a maximum of two DIMMs per channel. DDR technologies, number of DIMMs per channel, number of ranks per channel are SKU dependent. • UDIMM, SO-DIMM, and Memory Down support (based on SKU) • Single-channel and dual-channel memory organization modes • Data burst length of eight for all memory organization modes • DDR4 I/O Voltage of 1.
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Interfaces Table 2-1. Processor DDR Memory Speed Support (Sheet 2 of 2) Processor Line DDR4 1DPC [MT/s] DDR4 2DPC [MT/s] LPDDR3 [MT/s] Notes: 1. 1DPC-refer to 1 DIMM per channel natively, means 1 DIMM Slot per channel and not refer to 1 DIMM populated at 2 DIMMs per channel. 2DPC-refer to 2DIMMs per channel, fully populated or partially populated with 1 DIMM only. 2. S-Processor SO-DIMM 2DPC is limited to 2133 MT/s due to Daisy Chain topology. 3.
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Interfaces Table 2-3. 2.1.
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Interfaces Dual-Channel Mode – Intel® Flex Memory Technology Mode The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a symmetric and asymmetric zone. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached.
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Interfaces 2.1.4 System Memory Frequency In all modes, the frequency of system memory is the lowest frequency of all memory modules placed in the system, as determined through the SPD registers on the memory modules. The system memory controller supports up to two DIMM connectors per channel. If DIMMs with different latency are populated across the channels, the BIOS will use the slower of the two latencies for both channels. For Dual-Channel modes both channels should have a DIMM connector populated.
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Interfaces 2.1.7 DDR I/O Interleaving The processor supports I/O interleaving, which has the ability to swap DDR bytes for routing considerations. BIOS configures the I/O interleaving mode before DDR training.There are 2 supported modes: • Interleave (IL) • Non-Interleave (NIL) The following table and figure describe the pin mapping between the IL and NIL modes. Table 2-5.
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Interfaces Figure 2-2. Interleave (IL) and Non-Interleave (NIL) Modes Mapping Interleave back to back Non‐Interleave side by side Ch B Ch B Ch B Ch B DQ/DQS CMD/CTRL DQ/DQS CMD/CTRL Ch A Ch B DQ/DQS DQ/DQS Ch A Ch A Ch A Ch A DQ/DQS CMD/CTRL DQ/DQS CMD/CTRL Ch A SoDIMM Ch A SoDIMM Ch B SoDIMM Ch B SoDIMM 2.1.
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Interfaces Table 2-6.
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Interfaces • Power Management Event (PME) functions • Dynamic width capability • Message Signaled Interrupt (MSI and MSI-X) messages • Lane reversal • Full Advance Error Reporting (AER) and control capabilities are supported only on Server SKUs. The following table summarizes the transfer rates and theoretical bandwidth of PCI Express* link. Table 2-7.
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Interfaces 2.2.3 PCI Express* Configuration Mechanism The PCI Express* (external graphics) link is mapped through a PCI-to-PCI bridge structure. Figure 2-3. PCI Express* Related Register Structures in the Processor PCI Express* Device PEG PCI-PCI Bridge representing root PCI Express* ports (Device 1) PCI Compatible Host Bridge Device (Device 0) DMI PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the conventional PCI specification.
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Interfaces • Full RX Equalization and acquisition for: AGC (Adaptive Gain Control), CDR (Clock and Data Recovery), adaptive DFE (decision feedback equalizer) and adaptive CTLE peaking (continuous time linear equalizer). • Full adaptive phase 3 EQ compliant with PCI Express* Gen 3 specification See the PCI Express* Base Specification 3.0 for details on PCI Express* equalization. 2.3 Direct Media Interface (DMI) Direct Media Interface (DMI) connects the processor and the PCH.
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Interfaces Figure 2-4. Example for DMI Lane Reversal Connection Without Lane Reversal With Lane Reversal CPU Package CPU Package CPU DMI CPU DMI L0 2.3.
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Interfaces 2.4 Processor Graphics The processor graphics is based on Gen 9 LP (generation 9 Low Power) graphics core architecture that enables substantial gains in performance and lower-power consumption over prior generations. The processor graphics architecture delivers high dynamic range of scaling to address segments spanning low power to high power, increased performance per watt, support for next generation of APIs.
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Interfaces 2.4.3 Media Support (Intel® QuickSync & Clear Video Technology HD) Gen 9 LP implements multiple media video codecs in hardware as well as a rich set of image processing algorithms. Note: All supported media codecs operate on 8 bpc, YCbCr 4:2:0 video profiles. 2.4.3.1 Hardware Accelerated Video Decode Gen 9 LP implements a high-performance and low-power HW acceleration for video decoding operations for multiple video codecs.
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Interfaces 2.4.3.2 Hardware Accelerated Video Encode Gen 9 LP implements a high-performance and low-power HW acceleration for video decoding operations for multiple video codecs. The HW encode is exposed by the graphics driver using the following APIs: • Intel Media SDK • MFT (Media Foundation Transform) filters Gen 9 LP supports full HW accelerated video encoding for AVC/MPEG2/HEVC/VP8/JPEG. Table 2-9.
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Interfaces 2.4.3.4 Hardware Accelerated Transcoding Transcoding is a combination of decode video processing (optional) and encode. Using the above hardware capabilities can accomplish a high-performance transcode pipeline. There is not a dedicated API for transcoding. The processor graphics supports the following transcoding features: • Low-power and low-latency AVC encoder for video conferencing and Wireless Display applications. • Lossless memory compression for media engine to reduce media power.
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Interfaces 2.4.5 Gen 9 LP Video Analytics There is HW assist for video analytics filters such as scaling, convolve 2D/1D, minmax, 1P filter, erode, dilate, centroid, motion estimation, flood fill, cross correlation, Local Binary Pattern (LBP). Figure 2-5.
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Interfaces 2.4.6 Gen 9 LP (9th Generation Low Power) Block Diagram Figure 2-6.
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Interfaces 2.5 Display Interfaces 2.5.1 DDI Configuration The processor supports single eDP* interface and 2 or 3 DDI interfaces (depends on segment). Table 2-12. DDI Ports Availability Ports Port name in VBT S-Processor Line2,3 DDI0 - eDP Port A Yes DDI1 Port B Yes DDI2 Port C Yes DDI3 Port D Yes DDI4 - eDP/VGA Port E Yes1 Notes: 1. For more information, see Section 2.5.2, “eDP* Bifurcation” 2. 3xDDC (DDPB, DDPC, DDPD) are valid for all the processor SKUs . 3.
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Interfaces 2.5.2 eDP* Bifurcation Table 2-13. VGA and Embedded DisplayPort* (eDP*) Bifurcation Summary Port S-Processor Line eDP - DDIA (eDP lower x2 lanes, [1:0]) Yes VGA - DDIE2 (DP upper x2 lanes, [3:2]) Yes1 Notes: 1. Requires a DP to VGA converter. 2. DP-to-VGA converter on the processor ports is supported using external dongle only, display driver software for VGA dongles which configures the VGA port as a DP branch device. 3.
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Interfaces Table 2-15. Display Resolutions and Link Bandwidth for Multi-Stream Transport calculations (Sheet 2 of 2) Pixels per line Lines Refresh Rate [Hz] Pixel Clock [MHz] Link Bandwidth [Gbps] 1280 720 60 74.25 2.23 1280 768 60 68.25 2.05 1360 768 60 85.5 2.57 1280 1024 60 108 3.24 1400 1050 60 101 3.03 1680 1050 60 119 3.57 1920 1080 60 148.5 4.46 1920 1200 60 154 4.62 2048 1152 60 156.75 4.70 2048 1280 60 174.25 5.23 2048 1536 60 209.25 6.
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Interfaces • For display resolutions driving capability see Table 2-17, “Maximum Display Resolution”. • DisplayPort* Aux CH supported by the processor, while DDC channel, Panel power sequencing, and HPD are supported through the PCH. Figure 2-7.
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Interfaces 2.5.4 DisplayPort* The DisplayPort* is a digital communication interface that uses differential signaling to achieve a high-bandwidth bus interface designed to support connections between PCs and monitors, projectors, and TV displays. A DisplayPort* consists of a Main Link, Auxiliary channel, and a Hot-Plug Detect signal. The Main Link is a unidirectional, high-bandwidth, and low-latency channel used for transport of isochronous data streams such as uncompressed video and audio.
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Interfaces The processor HDMI interface is designed in accordance with the High-Definition Multimedia Interface. Figure 2-9. HDMI* Overview HDMI Sink HDMI Source HDMI Tx (Processor) TMDS Data Channel 0 HDMI Rx TMDS Data Channel 1 TMDS Data Channel 2 TMDS Clock Channel Hot‐Plug Detect Display Data Channel (DDC) CEC Line (optional) 2.5.6 Digital Video Interface (DVI) The processor Digital Ports can be configured to drive DVI-D.
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Interfaces Table 2-16. Processor Supported Audio Formats over HDMI and DisplayPort* Audio Formats AC-3 Dolby* Digital HDMI* DisplayPort* Yes Yes Dolby Digital Plus Yes Yes DTS-HD* Yes Yes LPCM, 192 kHz/24 bit, 8 Channel Yes Yes Dolby TrueHD, DTS-HD Master Audio* (Lossless Blu-Ray Disc* Audio Format) Yes Yes The processor will continue to support Silent stream.
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Interfaces Table 2-17. Maximum Display Resolution (Sheet 2 of 2) Standard S-Processor Line Notes Notes: 1. Maximum resolution is based on implementation of 4 lanes with HBR2 link data rate. 2. bpp - bit per pixel. 3. S-Processor Line support up to 4 displays, but only three can be active at the same time. 4. The resolutions are assumed at max VCCSA. 5. In the case of connecting more than one active display port, the processor frequency may be lower than base frequency at thermally limited scenario. 6.
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Interfaces Table 2-19. HDCP Display supported Implications Table (Sheet 2 of 2) Topic HDCP Revision Maximum Resolution HDCP Solution2 HDR1 BPC3 Comments HDCP1.4 4K@30 No iHDCP 8 bit Legacy Integrated for HDCP1.4 HDCP2.2 4K@30 No LSPCON 8 bit LSPCON HDCP2.2 required HDCP2.2 4K@30 No iHDCP4 8 bit New Integrated for HDCP2.2 HDMI2.0 HDCP2.2 4K@60 No LSPCON 12 bit (YUV 420) LSPCON HDCP2.2 required HDMI2.0a HDCP2.2 4K@60 Yes LSPCON 12 bit (YUV 420) LSPCON HDCP2.
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Interfaces 2.5.13 Table 2-22. Display Bit Per Pixel (BPP) Support Display Bit Per Pixel (BPP) Support Technology eDP* 24,30,36 DisplayPort* 24,30,36 HDMI* 2.5.14 Table 2-23. Bit Per Pixel (bpp) 24,36 Display Resolution per Link Width Supported Resolutions1 for HBR (2.7 Gbps) by Link Width Max Link Bandwidth [Gbps] Max Pixel Clock (theoretical) [MHz] S-Processor Lines 4 lanes 10.8 360 2880x1800 @ 60 Hz, 24bpp 2 lanes 5.4 180 2048x1280 @ 60 Hz, 24bpp 1 lane 2.
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Interfaces • PECI EC Connection. Figure 2-10.
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Interfaces Figure 2-11.
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Technologies 3 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor. The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site: http://www.intel.com/technology/ 3.
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Technologies • More secure: The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system.
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Technologies translate the linear address), the resulting guest-physical address is executable under EPT only if the XS bit is set in every EPT pagingstructure entry used to translate the guest-physical address —The XU and XS bits are used only when translating linear addresses for guest code fetches.
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Technologies • DMA remapping: for supporting independent address translations for Direct Memory Accesses (DMA) from devices. • Interrupt remapping: for supporting isolation and routing of interrupts from devices and external interrupt controllers to appropriate VMs. • Reliability: for recording and reporting to system software DMA and interrupt errors that may otherwise corrupt memory or impact VM isolation.
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Technologies Intel VT-d functionality, often referred to as an Intel VT-d Engine, has typically been implemented at or near a PCI Express* host bridge component of a computer system. This might be in a chipset component or in the PCI Express functionality of a processor with integrated I/O. When one such VT-d engine receives a PCI Express transaction from a PCI Express bus, it uses the B/D/F number associated with the transaction to search for an Intel VT-d translation table.
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Technologies • Intel VT-d superpage – support of Intel VT-d superpage (2 MB, 1 GB) for default Intel VT-d engine (that covers all devices except IGD) IGD Intel VT-d engine does not support superpage and BIOS should disable superpage in default Intel VT-d engine when iGfx is enabled. Note: Intel VT-d Technology may not be available on all SKUs. 3.2 Security Technologies 3.2.
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Technologies For the above features, BIOS should test the associated capability bit before attempting to access any of the above registers. For more information, refer to the Intel® Trusted Execution Technology Measured Launched Environment Programming Guide Note: Intel TXT Technology may not be available on all SKUs. 3.2.
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Technologies 3.2.5 Execute Disable Bit The Execute Disable Bit allows memory to be marked as non executable when combined with a supporting operating system. If code attempts to run in nonexecutable memory, the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can, thus, help improve the overall security of the system.
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Technologies 3.2.9 Intel® Memory Protection Extensions (Intel® MPX) Intel® MPX provides hardware accelerated mechanism for memory testing (heap and stack) buffer boundaries in order to identify buffer overflow attacks. An Intel MPX enabled compiler inserts new instructions that tests memory boundaries prior to a buffer access. Other Intel MPX commands are used to modify a database of memory regions used by the boundary checker instructions.
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Technologies • Supported protected memory sizes: — Supports 32, 64 and 128MB. For more information, refer to the Intel® SGX website at: https://software.intel.com/en-us/sgx Intel® SGX specifications and functional descriptions are included in the Intel® 64 Architectures Software Developer’s Manual, Volume 3. Available at: http://www.intel.com/products/processor/manuals 3.2.11 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Refer to Section 3.1.2 Intel VT-d for detail. 3.
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Technologies 3.3.2.1 Intel® Turbo Boost Technology 2.0 Frequency To determine the highest performance frequency amongst active processor IA cores, the processor takes the following into consideration: • The number of processor IA cores operating in the C0 state. • The estimated processor IA core current consumption and ICCMax register settings. • The estimated package prior and present power consumption and turbo power limits. • The package temperature.
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Technologies 3.3.4 Intel® 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides key mechanisms for interrupt delivery. This extension is primarily intended to increase processor addressability.
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Technologies • The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the “x2APIC” mode. To benefit from x2APIC capabilities, a new operating system and a new BIOS are both needed, with special support for x2APIC mode. • The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendible for future Intel platform innovations. Note: Intel x2APIC Technology may not be available on all SKUs.
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Power Management 4 Power Management This chapter provides information on the following power management topics: • Advanced Configuration and Power Interface (ACPI) States • Processor IA Core Power Management • Integrated Memory Controller (IMC) Power Management • PCI Express* Power Management • Direct Media Interface (DMI) Power Management • Processor Graphics Power Management Datasheet, Volume 1 of 2 61
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Power Management Figure 4-1. Processor Power States G0 – Working S0 – Processor powered on C0 – Active mode P0 Pn C1 – Auto halt C1E – Auto halt, low frequency, low voltage C2 – Temporary state before C3 or deeper.
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Power Management Figure 4-2. Processor Package and IA Core C-States 4.1 Advanced Configuration and Power Interface (ACPI) States Supported This section describes the ACPI states supported by the processor. Table 4-1. System States State Description G0/S0 Full On G1/S3-Cold Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor). G1/S4 Suspend-to-Disk (STD). All power lost (except wake-up on PCH). G2/S5 Soft off. All power lost (except wake-up on PCH).
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Power Management Table 4-2. Processor IA Core / Package State Support State C0 Table 4-3. Description Active mode, processor executing code. C1 AutoHALT processor IA core state (package C0 state). C1E AutoHALT processor IA core state with lowest frequency and voltage operating point (package C0 state). C2 All processor IA cores in C3 or deeper. Memory path open. Temporary state before Package C3 or deeper.
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Power Management Table 4-6. 4.
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Power Management 4.2.1.2 Intel® Speed Shift Technology Intel Speed Shift Technology is an energy efficient method of frequency control by the hardware rather than relying on OS control. OS is aware of available hardware P-states and request a desired P-state or it can let Hardware determine the P-state. The OS request is based on its workload requirements and awareness of processor capabilities.
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Power Management 4.2.3 Requesting Low-Power Idle States The primary software interfaces for requesting low-power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E). However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx.
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Power Management A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel 64 and IA-32 Architectures Software Developer’s Manual for more information. While a processor IA core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E, see Section 4.2.5.
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Power Management This feature is disabled by default. BIOS should enable it in the PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by this register. 4.2.5 Package C-States The processor supports C0, C2, C3, C6, C7, and C8 package states. The following is a summary of the general rules for package C-state entry.
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Power Management Figure 4-4. Package C-State Entry and Exit Package C0 This is the normal operating state for the processor. The processor remains in the normal state when at least one of its processor IA cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low-power state. Individual processor IA cores may be in deeper power idle states while the package is in C0 state.
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Power Management • The other processor IA cores are in a C3 or deeper power state, and the processor has been granted permission by the platform. • The platform has not granted a request to a package C6/C7 state or deeper state but has allowed a package C3 state. In package C3-state, the LLC shared cache is valid. Package C6 State A processor enters the package C6 low-power state when: • At least one processor IA core is in the C6 state.
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Power Management 4.2.6 Package C-States and Display Resolutions The integrated graphics engine has the frame buffer located in system memory. When the display is updated, the graphics engine fetches display data from system memory. Different screen resolutions and refresh rates have different memory latency requirements. These requirements may limit the deepest Package C-state the processor can enter.
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Power Management When a given rank is not populated, the corresponding control signals (CLK_P/CLK_N/ CKE/ODT/CS) are not driven. At reset, all rows should be assumed to be populated, until it can be proven that they are not populated. This is due to the fact that when CKE is tri-stated with a DRAMs present, the DRAMs are not ensured to maintain data integrity. CKE tri-state should be enabled by BIOS where appropriate, since at reset all rows should be assumed to be populated. 4.3.
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Power Management Selection of power modes should be according to power-performance or thermal tradeoff of a given system: • When trying to achieve maximum performance and power or thermal consideration is not an issue: use no power-down • In a system which tries to minimize power-consumption, try using the deepest power-down mode possible – PPD/DLL-off with a low idle timer value • In high-performance systems with dense packaging (that is, tricky thermal design) the power-down mode should be considered in
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Power Management Table 4-8. Targeted Memory State Conditions (Sheet 2 of 2) State 4.3.2.3 Memory State with Processor Graphics Memory State with External Graphics S3 Self-Refresh Mode Self-Refresh Mode S4 Memory power-down (contents lost) Memory power-down (contents lost) Dynamic Power-Down Dynamic power-down of memory is employed during normal operation. Based on idle conditions, a given memory rank may be powered down.
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Power Management 4.4 PCI Express* Power Management • Active power management support using L1 state. • All inputs and outputs disabled in L2/L3 Ready state. Note: Processor PEG-PCIe interface does not support Hot-Plug. Hot Plug like* is only supported at Processor PEG-PCIe using Thunderbolt Device. * Turning Thunderbolt™ power on and Off electrically RTD3 Like Table 4-9.
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Power Management Intel S2DDT is most effective with: • Display images well suited to compression, such as text windows, slide shows, and so on. Poor examples are 3D games. • Static screens such as screens with significant portions of the background showing 2D applications, processor benchmarks, and so on, or conditions when the processor is idle. Poor examples are full-screen 3D games and benchmarks that flip the display image at or near display refresh rates. 4.6.2 Display Power Savings Technologies 4.
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Power Management 2. Intel DPST subsystem applies an image-specific enhancement to increase image contrast, brightness, and other attributes. 3. A corresponding decrease to the backlight brightness is applied simultaneously to produce an image with similar user-perceived quality (such as brightness) as the original image. Intel DPST 6.
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Power Management 4.6.3.3 Dynamic FPS (DFPS) Dynamic FPS (DFPS) or dynamic frame-rate control is a runtime feature for improving power-efficiency for 3D workloads. Its purpose is to limit the frame-rate of full screen 3D applications without compromising on user experience. By limiting the frame rate, the load on the graphics engine is reduced, giving an opportunity to run the Processor Graphics at lower speeds, resulting in power savings. This feature works in both AC/DC modes. 4.
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Thermal Management 5 Thermal Management 5.1 Processor Thermal Management The thermal solution provides both component-level and system-level thermal management. To allow optimal operation and long-term reliability of Intel processorbased systems, the system/processor thermal solution should be designed so that the processor: • Bare Die Parts: Remains below the maximum junction temperature (TjMAX) specification at the maximum thermal design power (TDP).
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Thermal Management • The processor may exceed the TDP for short durations to utilize any available thermal capacitance within the thermal solution. The duration and time of such operation can be limited by platform runtime configurable registers within the processor. • Graphics peak frequency operation is based on the assumption of only one of the graphics domains (GT) being active.
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Thermal Management Note: Implementation of Intel Turbo Boost Technology 2.0 only requires configuring PL1, PL1 Tau, and PL2. Note: PL3 and PL4 are disabled by default. Figure 5-1. Package Power Control 5.1.3.2 Platform Power Control The processor supports Psys (Platform Power) to enhance processor power management. The Psys signal needs to be sourced from a compatible charger circuit and routed to the IMVP8 (voltage regulator).
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Thermal Management • The Psys signal and associated power limits / Tau are optional for the system designer and disabled by default. • The Psys data will not include power consumption for charging. 5.1.3.3 Turbo Time Parameter (Tau) Turbo Time Parameter (Tau) is a mathematical parameter (units of seconds) that controls the Intel Turbo Boost Technology 2.0 algorithm. During a maximum power turbo event, the processor could sustain PL2 for a duration longer than the Turbo Time Parameter.
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Thermal Management Table 5-1. Configurable TDP Modes (Sheet 2 of 2) Mode Description TDP-Up The SKU-specific processor IA core frequency where manufacturing confirms logical functionality within the set of operating condition limits specified for the SKU segment and Configurable TDP-Up configuration in Table 5-2. The Configurable TDP-Up Frequency and corresponding TDP is higher than the processor IA core Base Frequency and SKU Segment Base TDP.
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Thermal Management several thermal management features exist to reduce package power consumption and thereby temperature in order to remain within normal operating limits. Furthermore, the processor supports several methods to reduce memory power. 5.1.5.1 Adaptive Thermal Monitor The purpose of the Adaptive Thermal Monitor is to reduce processor IA core power consumption and temperature until it operates below its maximum operating temperature.
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Thermal Management If enabled, the offset should be set lower than any other passive protection such as ACPI _PSV trip points TCC Activation Offset with Tau To manage the processor with the EWMA (Exponential Weighted Moving Average) of temperature, an offset (degrees Celsius) is written to the TEMPERATURE_TARGET (0x1A2) MSR, bits [29:24], and the time window (Tau) is written to the TEMPERATURE_TARGET (0x1A2) MSR [6:0].
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Thermal Management 5.1.5.1.3 Clock Modulation If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor event, the Adaptive Thermal Monitor will utilize clock modulation. Clock modulation is done by alternately turning the clocks off and on at a duty cycle (ratio between clock “on” time and total time) specific to the processor. The duty cycle is factory configured to 25% on and 75% off and cannot be modified.
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Thermal Management frequency, voltage, or both. Changes to the temperature can be detected using two programmable thresholds located in the processor thermal MSRs. These thresholds have the capability of generating interrupts using the processor IA core's local APIC. 5.1.5.2.1 Digital Thermal Sensor Accuracy (Taccuracy) The error associated with DTS measurements will not exceed ±5 °C within the entire operating range. 5.1.5.2.
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Thermal Management cores. Systems should still provide proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. Overall, the system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP. 5.1.5.
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Thermal Management Mode can be accomplished using processor MSR or chipset I/O emulation. On-Demand Mode may be used in conjunction with the Adaptive Thermal Monitor. However, if the system software tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode.
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Thermal Management 5.2 All-Processor Line Thermal and Power Specifications The following notes apply only to Table 5-2, Table 5-3 and Table 5-4.
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Thermal Management 5.3 S-Processor Line Thermal and Power Specifications Table 5-2. TDP Specifications (S-Processor Line) Segment and Package Processor IA Cores, Graphics Configuration and TDP Hexa Core GT2 95W SProcessor Line LGA Quad Core GT2 95W Hexa Core GT2 65W Quad Core GT2 65W Table 5-3. Processor IA Core Frequency Graphics core Frequency Thermal Design Power (TDP) [w] Base 3.2 GHz to 3.7 GHz 1.0 GHz to 1.2 GHz 95 LPM 0.8 GHz 0.35 GHz N/A Configuration Base 4.0 GHz 1.
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Thermal Management Table 5-4. TCONTROL Offset Configuration (S-Processor Line - Client) (Sheet 2 of 2) Segment Hexa Core GT2 Quad Core GT2 Notes: 1. Digital Thermal Sensor (DTS) based fan speed control is recommended to achieve optimal thermal performance. 2. Intel recommends full cooling capability at approximately the DTS value of -1, to minimize TCC activation risk. 3. For example, if TCONTROL = 20 ºC, Fan acceleration operation will start at 80 ºC (100 ºC - 20 ºC). 5.3.
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Thermal Management Table 5-5. Thermal Test Vehicle Thermal Profile for PCG 2015D Processor (Sheet 2 of 2) Power (W) TCASE_MAX (C) Power (W) TCASE_MAX (C) 32 50.7 78 60.9 34 51.2 80 61.3 36 51.6 82 61.7 38 52.1 84 62.2 40 52.5 86 62.6 42 52.9 88 63.1 44 53.4 90 63.5 46 53.8 92 63.9 5.3.2 Thermal Profile for PCG 2015C Processor Figure 5-3. Thermal Test Vehicle Thermal Profile for PCG 2015C Processor Notes: 1.
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Thermal Management Table 5-6. Thermal Test Vehicle Thermal Profile for PCG 2015C Processor (Sheet 2 of 2) Power (W) TCASE_MAX (C) Power (W) TCASE_MAX (C) 20 51.7 53 65.2 22 52.5 54 65.6 24 53.3 56 66.5 26 54.2 58 67.3 28 55.0 60 68.1 30 55.8 62 68.9 32 56.6 64 69.7 34 57.4 65 70.2 5.3.3 Thermal Profile for PCG 2015B Processor Figure 5-4. Thermal Test Vehicle Thermal Profile for PCG 2015B Processor Notes: 1.
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Thermal Management Table 5-7. 96 Thermal Test Vehicle Thermal Profile for PCG 2015B Processor (Sheet 2 of 2) Power (W) TCASE_MAX (C) Power (W) TCASE_MAX (C) 14 55.3 34 65.5 16 56.4 35 66.1 18 57.
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Thermal Management 5.3.4 Thermal Metrology The maximum TTV case temperatures (TCASE-MAX) can be derived from the data in the appropriate TTV thermal profile earlier in this chapter. The TTV TCASE is measured at the geometric top center of the TTV integrated heat spreader (IHS). Figure 5-5 illustrates the location where TCASE temperature measurements should be made. Figure 5-5. Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location 37.
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Thermal Management Similarly for a system with a design target of 45 °C ambient, the ΨCA at DTS = -1 needed will be 0.21 °C/W. The second point defines the thermal solution performance (ΨCA) at TCONTROL. The following table lists the required ΨCA for the various TDP processors. These two points define the operational limits for the processor for DTS 1.1 implementation.
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Thermal Management 5.3.6 Fan Speed Control Scheme with Digital Thermal Sensor (DTS) 2.0 To simplify processor thermal specification compliance, the processor calculates the DTS Thermal Profile from TCONTROL Offset, TCC Activation Temperature, TDP, and the Thermal Margin Slope provided in the following table. Note: TCC Activation Offset is 0 for the processors.
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Signal Description 6 Signal Description This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The notations in the following table are used to describe the signal type. The signal description also includes the type of buffer used for the particular signal (see the following table). Table 6-1.
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Signal Description Table 6-2. DDR4 Memory Interface (Sheet 2 of 2) Signal Name Description Dir. Buffer Type Link Type Availability DDR0_CKE[3:0] DDR1_CKE[3:0] Clock Enable: (1 per rank). These signals are used to: • Initialize the SDRAMs during power-up. • Power-down SDRAM ranks. • Place all SDRAM ranks into and out of selfrefresh during STR (Suspend to RAM). O DDR4 SE [1:0] applicable for All Processor Lines. [3:2] applicable only in S Processor Line .
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Signal Description Table 6-3. System Memory Reference and Compensation Signals Signal Name DDR_VTT_CNTL Description Dir. Buffer Type Link Type System Memory Power Gate Control: When signal is high – platform memory VTT regulator is enable, output high. When signal is low - Disables the platform memory VTT regulator in C8 and deeper and S3. O CMOS SE 6.2 PCI Express* Graphics (PEG) Signals Table 6-4.
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Signal Description 6.4 Reset and Miscellaneous Signals Table 6-6. Reset and Miscellaneous Signals Signal Name Description Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. Intel recommends placing test points on the board for CFG pins. • CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted: — 1 = (Default) Normal Operation; No stall. — 0 = Stall. • CFG[1]: Reserved configuration lane.
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Signal Description Table 6-7. embedded DisplayPort* Signals (Sheet 2 of 2) Signal Name Description DISP_UTILS embedded DisplayPort Utility: Output control signal used for brightness correction of embedded LCD displays with backlight modulation. This pin will co-exist with functionality similar to existing BKLTCTL pin on PCH DISP_RCOMP DDI IO Compensation resistor, supporting DP*, eDP* and HDMI* channels. Dir.
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Signal Description 6.8 Testability Signals Table 6-10. Testability Signals Description Dir. Buffer Type Link Type BPM#[3:0] Breakpoint and Performance Monitor Signals: Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. I/O GTL SE All Processor Lines PROC_PRDY# Probe Mode Ready: PROC_PRDY# is a processor output used by debug tools to determine processor debug readiness.
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Signal Description Table 6-11. Error and Thermal Protection Signals (Sheet 2 of 2) Signal Name THERMTRIP# 6.10 Description Dir. Buffer Type Link Type Thermal Trip: The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all executions when the junction temperature exceeds approximately 130 °C.
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Signal Description 6.11 Processor Power Rails Table 6-13. Processor Power Rails Signals Signal Name Description Dir. Buffer Type Link Type Availability Vcc Processor IA cores power rail I Power — All Processor Lines VccGT Processor Graphics power rail I Power — All Processor Lines VDDQ System Memory power rail I Power — All Processor Lines VccSA Processor System Agent power rail I Power — All Processor Lines VccIO Processor I/O power rail. Consists of VCCIO and VccIO_DDR.
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Signal Description 6.
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Electrical Specifications 7 Electrical Specifications 7.1 Processor Power Rails Table 7-1.
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Electrical Specifications 7.2 DC Specifications The processor DC specifications in this section are defined at the processor signal pins, unless noted otherwise. • The DC specifications for the DDR4 signals are listed in the Voltage and Current Specifications section. • The Voltage and Current Specifications section lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages.
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Electrical Specifications Table 7-2. Processor IA core (Vcc) Active and Idle Mode DC Voltage and Current Specifications (Sheet 2 of 2) Symbol Parameter Segment Min Typ Max Note1 Unit Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2.
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Electrical Specifications Table 7-3. Symbol Processor Graphics (VccGT) Supply DC Voltage and Current Specifications (Sheet 2 of 2) Parameter Segment DC_LL AC_LL (SProcessors) AC Loadline T_OVS_MAX Max Overshoot time — V_OVS_MAX Max Overshoot — Unit Note1 3.1 3.1 m 7, 9, 10 — Same as Max DC_LL (up to 400 KHz) m 7, 9, 10 — — 10 s — — 70 mV Typ — — — — — S-Quad Core GT2 S-Hexa Core GT2 VccGT Loadline slope Max Min S-Processor Line Notes: 1.
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Electrical Specifications 7.2.1.4 VccSA DC Specifications Table 7-5. System Agent (VccSA) Supply DC Voltage and Current Specifications Symbol Parameter Segment Min Typ Max Unit Note1,2 — 1.05 — V 3,5 ±5(DC+AC+ripple) % 8 11.1 11.
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Electrical Specifications Table 7-6. Symbol Processor I/O (VccIO) Supply DC Voltage and Current Specifications (Sheet 2 of 2) Parameter Segment Min Typ Max Unit Note1,2 Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits. 3.
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Electrical Specifications Table 7-9. Symbol Processor PLL_OC (VccPLL_OC) Supply DC Voltage and Current Specifications Parameter Segment VccPLL_OC PLL_OC supply voltage (DC + AC specification) All TOBCCPLL_OC VccPLL_OC Tolerance All IccMAX_VCCPLL_OC Max Current for VccPLL_OC Rail S-Processor Line - Quad Core GT2 S-Processor Line - Hexa Core GT2 Min Typ Max Un it Notes1,2 — VDDQ — V 3 % 3,4 AC+DC:± 5 — 130 130 — mA Notes: 1.
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Electrical Specifications Table 7-10. DDR4 Signal Group DC Specifications (Sheet 2 of 2) US-Processor Line Symbol Parameter Min DDR_RCOMP[0] Typ ODT resistance compensation DDR_RCOMP[1] Data resistance compensation DDR_RCOMP[2] Command resistance compensation Units Notes1  6 Max RCOMP values are memory topology dependent.  6  6 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2.
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Electrical Specifications Table 7-12. Digital Display Interface Group DC Specifications (DP/HDMI) (Sheet 2 of 2) Symbol Parameter Min Typ Max Units Notes1 Notes: 1. VccIO depends on segment. 2. VOL and VOH levels depends on the level chosen by the Platform. 7.2.2.4 embedded DisplayPort* (eDP*) DC Specification Table 7-13. embedded DisplayPort* (eDP*) Group DC Specifications Symbol Parameter Min Typ Max Units VOL eDP_DISP_UTIL Output Low Voltage — — 0.
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Electrical Specifications Table 7-15. GTL Signal Group and Open Drain Signal Group DC Specifications (Sheet 2 of 2) Symbol Parameter Min Max Units Notes1 VIL Input Low Voltage (PROC_TCK,PROC_TRST#) — Vcc * 0.3 V 2, 5, 6 VIH Input High Voltage (PROC_TCK,PROC_TRST#) Vcc * 0.3 — V 2, 4, 5, 6 VHYSTERESIS Hysteresis Voltage Vcc * 0.2 — V - RON Buffer on Resistance (TDO) 7 17  - VIL Input Low Voltage (other GTL) — Vcc * 0.
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Electrical Specifications Input Device Hysteresis The input buffers in both client and host models should use a Schmitt-triggered input design for improved noise immunity. Use the following figure as a guide for input buffer design. Figure 7-1.
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Package Mechanical Specifications 8 Package Mechanical Specifications 8.1 Package Mechanical Attributes The S-Processor Line uses a Flip Chip technology available in Land Grid Array (LGA). The following table provides an overview of the mechanical attributes of the package. Table 8-1.
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Package Mechanical Specifications Table 8-2. Package Storage Specifications (Sheet 2 of 2) Parameter Description RHSUSTAINED STORAGE The maximum device storage relative humidity for the sustained period of time as specified below in Intel Original sealed moisture barrier bag. TIMESUSTAINED STORAGE A prolonged or extended period of time: associated with customer shelf life in Intel Original sealed moisture barrier bag. Min Max 60% @ 24 °C 0 months 6 months Notes 1, 2, 3 1, 2, 3 Notes: 1.
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Processor Ball Information 9 Processor Ball Information The processor is available in the LGA package (LGA1151). This chapter provides the top view of the Ball map. Table 9-1 provides the Ball Listing. 9.1 Ball Map Figure 9-1.
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Processor Ball Information Figure 9-2.
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Processor Ball Information Figure 9-3.
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Processor Ball Information 9.2 Ball Listing Table 9-1. Ball Listing (Sheet 1 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) V3 PROC_AUDIO_CLK I 16002 -2286 V2 PROC_AUDIO_SDI I 16916.4 -2286 U1 PROC_AUDIO_SDO O 17830.8 -3200.4 W4 BCLKN I 15087.6 -1371.6 W5 BCLKP I 14173.2 -1371.6 D13 CATERR# O 6858 -15087.6 J9 CLK24N I 10515.6 -10515.6 K9 CLK24P I 10515.6 -9601.2 G8 VSS GND 11430 -12344.4 AY3 VSS GND 16002 17830.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 2 of 31) Ball# 126 Ball Name Default X Location (µm) Y Location (µm) C19 DDI2_TXP[2] O 1371.6 -16002 D20 DDI2_TXP[3] O 457.2 -15087.6 C11 DDI3_AUXN O 8686.8 -16002 B11 DDI3_AUXP O 8686.8 -16916.4 A14 DDI3_TXN[0] O 5943.6 -17830.8 B15 DDI3_TXN[1] O 5029.2 -16916.4 A16 DDI3_TXN[2] O 4114.8 -17830.8 B17 DDI3_TXN[3] O 3200.4 -16916.4 B14 DDI3_TXP[0] O 5943.6 -16916.4 C15 DDI3_TXP[1] O 5029.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 3 of 31) Ball# Ball Name F9 EDP_TXP[3] H8 RSVD K10 RSVD L10 RSVD K12 RSVD L12 Default Y Location (µm) 10515.6 -13258.8 N/A 11430 -11430 N/A 9601.2 -9601.2 N/A 9601.2 -8686.8 N/A 7772.4 -9601.2 RSVD N/A 7772.4 -8686.8 J13 RSVD N/A 6858 -10515.6 K13 RSVD N/A 6858 -9601.2 J11 RSVD N/A 8686.8 -10515.6 D16 BPM#[0] I/O 4114.8 -15087.6 D17 BPM#[1] I/O 3200.4 -15087.6 G14 BPM#[2] I/O 5943.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 4 of 31) Ball# 128 Ball Name Default X Location (µm) Y Location (µm) C6 PEG_RXN[1] M5 PEG_RXN[10] I 14173.2 -7772.4 N4 PEG_RXN[11] I 15087.6 -6858 P5 PEG_RXN[12] I 14173.2 -5943.6 R4 PEG_RXN[13] I 15087.6 -5029.2 T5 PEG_RXN[14] I 14173.2 -4114.8 U4 PEG_RXN[15] I 15087.6 -3200.4 D5 PEG_RXN[2] I 14173.2 -15087.6 E4 PEG_RXN[3] I 15087.6 -14173.2 F5 PEG_RXN[4] I 14173.2 -13258.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 5 of 31) Ball# Ball Name C4 PEG_TXN[2] D3 PEG_TXN[3] E2 PEG_TXN[4] F3 PEG_TXN[5] G2 PEG_TXN[6] H3 PEG_TXN[7] J2 K3 Default Y Location (µm) 15087.6 -16002 O 16002 -15087.6 O 16916.4 -14173.2 O 16002 -13258.8 O 16916.4 -12344.4 O 16002 -11430 PEG_TXN[8] O 16916.4 -10515.6 PEG_TXN[9] O 16002 -9601.2 A5 PEG_TXP[0] O 14173.2 -17830.8 B4 PEG_TXP[1] O 15087.6 -16916.4 L1 PEG_TXP[10] O 17830.8 -8686.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 6 of 31) Ball# 130 Ball Name Default X Location (µm) Y Location (µm) D15 RSVD K11 RSVD N/A 8686.8 -9601.2 AB36 PROC_SELECT# N/A -14173.2 1371.6 AC38 SKTOCC# N/A -16002 2286 J15 RSVD N/A 5029.2 -10515.6 AU9 RSVD N/A 10515.6 15087.6 J14 RSVD N/A 5943.6 -10515.6 AU10 RSVD N/A 9601.2 15087.6 D11 THERMTRIP# O 8686.8 -15087.6 A25 VCC PWR -4114.8 -17830.8 A26 VCC PWR -5029.2 -17830.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 7 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) B35 VCC PWR -13258.8 -16916.4 B36 VCC PWR -14173.2 -16916.4 B37 VCC PWR -15087.6 -16916.4 C25 VCC PWR -4114.8 -16002 C26 VCC PWR -5029.2 -16002 C27 VCC PWR -5943.6 -16002 C28 VCC PWR -6858 -16002 C29 VCC PWR -7772.4 -16002 C30 VCC PWR -8686.8 -16002 C32 VCC PWR -10515.6 -16002 C34 VCC PWR -12344.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 8 of 31) Ball# 132 Ball Name Default X Location (µm) Y Location (µm) F34 VCC PWR -12344.4 -13258.8 F35 VCC PWR -13258.8 -13258.8 F37 VCC PWR -15087.6 -13258.8 G23 VCC PWR -2286 -12344.4 G24 VCC PWR -3200.4 -12344.4 G25 VCC PWR -4114.8 -12344.4 G26 VCC PWR -5029.2 -12344.4 G27 VCC PWR -5943.6 -12344.4 G28 VCC PWR -6858 -12344.4 G29 VCC PWR -7772.4 -12344.4 G30 VCC PWR -8686.8 -12344.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 9 of 31) Ball# Ball Name K21 VCC K23 VCC K25 VCC K27 VCC K29 VCC K31 Default Y Location (µm) -457.2 -9601.2 PWR -2286 -9601.2 PWR -4114.8 -9601.2 PWR -5943.6 -9601.2 PWR -7772.4 -9601.2 VCC PWR -9601.2 -9601.2 K32 VCC PWR -10515.6 -9601.2 K34 VCC PWR -12344.4 -9601.2 L14 VCC PWR 5943.6 -8686.8 L15 VCC PWR 5029.2 -8686.8 L16 VCC PWR 4114.8 -8686.8 L17 VCC PWR 3200.4 -8686.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 10 of 31) Ball# 134 Ball Name Default X Location (µm) Y Location (µm) J17 RSVD N/A 3200.4 -10515.6 B39 RSVD N/A -16916.4 -16916.4 C40 RSVD N/A -17830.8 -16002 J19 RSVD N/A 1371.6 -10515.6 AT18 VDDQ PWR 2286 14173.2 AT21 VDDQ PWR -457.2 14173.2 AU13 VDDQ PWR 6858 15087.6 AU15 VDDQ PWR 5029.2 15087.6 AU19 VDDQ PWR 1371.6 15087.6 AU23 VDDQ PWR -2286 15087.6 AV11 VDDQ PWR 8686.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 11 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) J39 VCCGT PWR -16916.4 -10515.6 J40 VCCGT PWR -17830.8 -10515.6 K36 VCCGT PWR -14173.2 -9601.2 K38 VCCGT PWR -16002 -9601.2 K40 VCCGT PWR -17830.8 -9601.2 L34 VCCGT PWR -12344.4 -8686.8 L35 VCCGT PWR -13258.8 -8686.8 L36 VCCGT PWR -14173.2 -8686.8 L37 VCCGT PWR -15087.6 -8686.8 L38 VCCGT PWR -16002 -8686.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 12 of 31) Ball# 136 Ball Name Default X Location (µm) Y Location (µm) T38 VCCGT PWR -16002 -4114.8 T40 VCCGT PWR -17830.8 -4114.8 U34 VCCGT PWR -12344.4 -3200.4 U35 VCCGT PWR -13258.8 -3200.4 U36 VCCGT PWR -14173.2 -3200.4 U37 VCCGT PWR -15087.6 -3200.4 U38 VCCGT PWR -16002 -3200.4 U39 VCCGT PWR -16916.4 -3200.4 U40 VCCGT PWR -17830.8 -3200.4 V33 VCCGT PWR -11430 -2286 V34 VCCGT PWR -12344.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 13 of 31) Ball# Ball Name AC7 VCCSA AC8 VCCSA N7 VCCSA P7 VCCSA R7 VCCSA T7 Default Y Location (µm) 12344.4 2286 PWR 11430 2286 PWR 12344.4 -6858 PWR 12344.4 -5943.6 PWR 12344.4 -5029.2 VCCSA PWR 12344.4 -4114.8 U7 VCCSA PWR 12344.4 -3200.4 V7 VCCSA PWR 12344.4 -2286 W7 VCCSA PWR 12344.4 -1371.6 Y6 VCCSA PWR 13258.8 -457.2 Y7 VCCSA PWR 12344.4 -457.2 Y8 VCCSA PWR 11430 -457.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 14 of 31) Ball# 138 Ball Name Default X Location (µm) Y Location (µm) AD37 VSS GND -15087.6 AD38 VSS GND -16002 3200.4 AD39 VSS GND -16916.4 3200.4 AD4 VSS GND 15087.6 3200.4 AD40 VSS GND -17830.8 3200.4 AD6 VSS GND 13258.8 3200.4 AD7 VSS GND 12344.4 3200.4 AD8 VSS GND 11430 3200.4 AE3 VSS GND 16002 4114.8 AE33 VSS GND -11430 4114.8 AE36 VSS GND -14173.2 4114.8 AE5 VSS GND 14173.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 15 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) AJ31 VSS GND -9601.2 AJ32 VSS GND -10515.6 7772.4 AJ33 VSS GND -11430 7772.4 AJ34 VSS GND -12344.4 7772.4 AJ35 VSS GND -13258.8 7772.4 AJ36 VSS GND -14173.2 7772.4 AJ4 VSS GND 15087.6 7772.4 AJ5 VSS GND 14173.2 7772.4 AJ8 VSS GND 11430 7772.4 AK10 VSS GND 9601.2 8686.8 AK12 VSS GND 7772.4 8686.8 AK13 VSS GND 6858 8686.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 16 of 31) Ball# 140 Ball Name AL24 VSS AL27 VSS AL3 VSS AL30 VSS AL36 VSS AL4 Default GND X Location (µm) Y Location (µm) -3200.4 9601.2 GND -5943.6 9601.2 GND 16002 9601.2 GND -8686.8 9601.2 GND -14173.2 9601.2 VSS GND 15087.6 9601.2 AL5 VSS GND 14173.2 9601.2 AM11 VSS GND 8686.8 10515.6 AM14 VSS GND 5943.6 10515.6 AM17 VSS GND 3200.4 10515.6 AM19 VSS GND 1371.6 10515.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 17 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) AN6 VSS GND 13258.8 AN7 VSS GND 12344.4 11430 AN8 VSS GND 11430 11430 AN9 VSS GND 10515.6 11430 AP11 VSS GND 8686.8 12344.4 AP14 VSS GND 5943.6 12344.4 AP24 VSS GND -3200.4 12344.4 AP27 VSS GND -5943.6 12344.4 AP30 VSS GND -8686.8 12344.4 AP36 VSS GND -14173.2 12344.4 AP37 VSS GND -15087.6 12344.4 AP40 VSS GND -17830.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 18 of 31) Ball# 142 Ball Name Default X Location (µm) Y Location (µm) AT12 VSS GND 7772.4 AT13 VSS GND 6858 14173.2 AT14 VSS GND 5943.6 14173.2 AT15 VSS GND 5029.2 14173.2 AT17 VSS GND 3200.4 14173.2 AT24 VSS GND -3200.4 14173.2 AT25 VSS GND -4114.8 14173.2 AT26 VSS GND -5029.2 14173.2 AT27 VSS GND -5943.6 14173.2 AT28 VSS GND -6858 14173.2 AT29 VSS GND -7772.4 14173.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 19 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) AV5 VSS GND 14173.2 AV9 VSS GND 10515.6 16002 AW3 VSS GND 16002 16916.4 AW30 VSS GND -8686.8 16916.4 AW32 VSS GND -10515.6 16916.4 AW34 VSS GND -12344.4 16916.4 AW36 VSS GND -14173.2 16916.4 AW5 VSS GND 14173.2 16916.4 AW9 VSS GND 10515.6 16916.4 AY27 VSS GND -5943.6 17830.8 AY30 VSS GND -8686.8 17830.8 AY5 VSS GND 14173.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 20 of 31) Ball# 144 Ball Name Default X Location (µm) Y Location (µm) D4 VSS GND 15087.6 D7 VSS GND 12344.4 -15087.6 E11 VSS GND 8686.8 -14173.2 E13 VSS GND 6858 -14173.2 E15 VSS GND 5029.2 -14173.2 E17 VSS GND 3200.4 -14173.2 E19 VSS GND 1371.6 -14173.2 E21 VSS GND -457.2 -14173.2 E23 VSS GND -2286 -14173.2 E3 VSS GND 16002 -14173.2 E31 VSS GND -9601.2 -14173.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 21 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) H21 VSS GND -457.2 -11430 H24 VSS GND -3200.4 -11430 H26 VSS GND -5029.2 -11430 H28 VSS GND -6858 -11430 H30 VSS GND -8686.8 -11430 H35 VSS GND -13258.8 -11430 H37 VSS GND -15087.6 -11430 H39 VSS GND -16916.4 -11430 H4 VSS GND 15087.6 -11430 H7 VSS GND 12344.4 -11430 H9 VSS GND 10515.6 -11430 J10 VSS GND 9601.2 -10515.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 22 of 31) Ball# 146 Ball Name Default X Location (µm) Y Location (µm) L32 VSS GND -10515.6 -8686.8 L6 VSS GND 13258.8 -8686.8 L9 VSS GND 10515.6 -8686.8 M1 VSS GND 17830.8 -7772.4 M10 VSS GND 9601.2 -7772.4 M12 VSS GND 7772.4 -7772.4 M15 VSS GND 5029.2 -7772.4 M17 VSS GND 3200.4 -7772.4 M19 VSS GND 1371.6 -7772.4 M21 VSS GND -457.2 -7772.4 M23 VSS GND -2286 -7772.4 M25 VSS GND -4114.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 23 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) U6 VSS GND 13258.8 V1 VSS GND 17830.8 -2286 V35 VSS GND -13258.8 -2286 V37 VSS GND -15087.6 -2286 V39 VSS GND -16916.4 -2286 V8 VSS GND 11430 -2286 W3 VSS GND 16002 -1371.6 W33 VSS GND -11430 -1371.6 W6 VSS GND 13258.8 -1371.6 Y35 VSS GND -13258.8 -457.2 Y37 VSS GND -15087.6 -457.2 Y5 VSS GND 14173.2 -457.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 24 of 31) Ball# 148 Ball Name Default X Location (µm) Y Location (µm) AL40 DDR0_DQ[15] / DDR0_DQ[15] I/O -17830.8 AN38 DDR0_DQ[16] / DDR0_DQ[32] I/O -16002 11430 AN40 DDR0_DQ[17] / DDR0_DQ[33] I/O -17830.8 11430 AR38 DDR0_DQ[18] / DDR0_DQ[34] I/O -16002 13258.8 AR37 DDR0_DQ[19] / DDR0_DQ[35] I/O -15087.6 13258.8 AN39 DDR0_DQ[20] / DDR0_DQ[36] I/O -16916.4 11430 AN37 DDR0_DQ[21] / DDR0_DQ[37] I/O -15087.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 25 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) AP1 DDR0_DQ[54] / DDR1_DQ[38] I/O 17830.8 AM1 DDR0_DQ[55] / DDR1_DQ[39] I/O 17830.8 10515.6 AK3 DDR0_DQ[56] / DDR1_DQ[40] I/O 16002 8686.8 AH1 DDR0_DQ[57] / DDR1_DQ[41] I/O 17830.8 6858 AK4 DDR0_DQ[58] / DDR1_DQ[42] I/O 15087.6 8686.8 AH2 DDR0_DQ[59] / DDR1_DQ[43] I/O 16916.4 6858 AH4 DDR0_DQ[60] / DDR1_DQ[44] I/O 15087.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 26 of 31) Ball# 150 Ball Name Default X Location (µm) Y Location (µm) AL28 DDR1_DQ[29] / DDR0_DQ[61] I/O -6858 9601.2 AR28 DDR1_DQ[30] / DDR0_DQ[62] I/O -6858 13258.8 AP28 DDR1_DQ[31] / DDR0_DQ[63] I/O -6858 12344.4 AR12 DDR1_DQ[32] / DDR1_DQ[16] I/O 7772.4 13258.8 AP12 DDR1_DQ[33] / DDR1_DQ[17] I/O 7772.4 12344.4 AM13 DDR1_DQ[34] / DDR1_DQ[18] I/O 6858 10515.6 AL13 DDR1_DQ[35] / DDR1_DQ[19] I/O 6858 9601.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 27 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) AP39 DDR0_DQSN[2] / DDR0_DQSN[4] I/O -16916.4 12344.4 AU36 DDR0_DQSN[3] / DDR0_DQSN[5] I/O -14173.2 15087.6 AW7 DDR0_DQSN[4] / DDR1_DQSN[0] I/O 12344.4 16916.4 AU3 DDR0_DQSN[5] / DDR1_DQSN[1] I/O 16002 15087.6 AN3 DDR0_DQSN[6] / DDR1_DQSN[4] I/O 16002 11430 AJ3 DDR0_DQSN[7] / DDR1_DQSN[5] I/O 16002 7772.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 28 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) AN12 DDR1_DQSP[4] / DDR1_DQSP[2] I/O 7772.4 11430 AP8 DDR1_DQSP[5] / DDR1_DQSP[3] I/O 11430 12344.4 AL8 DDR1_DQSP[6] / DDR1_DQSP[6] I/O 11430 9601.2 AG7 DDR1_DQSP[7] / DDR1_DQSP[7] I/O 12344.4 5943.6 AU32 DDR0_DQSN[8] / DDR0_DQSN[8] I/O -10515.6 15087.6 AV32 DDR0_DQSP[8] / DDR0_DQSP[8] I/O -10515.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 29 of 31) Ball# Ball Name Default X Location (µm) Y Location (µm) AV29 DDR1_CKE[1] O -7772.4 16002 AW29 DDR1_CKE[2] O -7772.4 16916.4 AU29 DDR1_CKE[3] O -7772.4 15087.6 AW11 DDR0_ODT[0] O 8686.8 16916.4 AU14 DDR0_ODT[1] O 5943.6 15087.6 AU12 DDR0_ODT[2] O 7772.4 15087.6 AY10 DDR0_ODT[3] O 9601.2 17830.8 AM16 DDR1_ODT[0] O 4114.8 10515.6 AL16 DDR1_ODT[1] O 4114.8 9601.2 AP15 DDR1_ODT[2] O 5029.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 30 of 31) Ball# 154 Ball Name Default X Location (µm) Y Location (µm) AW23 DDR0_BG[0] O -2286 AV23 DDR0_BG[1] O -2286 16002 AL19 DDR1_MA[0] O 1371.6 9601.2 AL22 DDR1_MA[1] O -1371.6 9601.2 AM22 DDR1_MA[2] O -1371.6 10515.6 AM23 DDR1_MA[3] O -2286 10515.6 AP23 DDR1_MA[4] O -2286 12344.4 AL23 DDR1_MA[5] O -2286 9601.2 AW26 DDR1_MA[6] O -5029.2 16916.4 AY26 DDR1_MA[7] O -5029.2 17830.
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Processor Ball Information Table 9-1. Ball Listing (Sheet 31 of 31) Ball# AL26 Ball Name DDR1_ECC[7] Default X Location (µm) Y Location (µm) I/O -5029.2 9601.2 O -17830.8 2286 DDR VREF AC40 DDR0_VREF_DQ AC39 DDR1_VREF_DQ O -16916.4 2286 AB40 DDR_VREF_CA O -17830.8 1371.6 AC36 DDR_VTT_CNTL O -14173.2 2286 AV1 RSVD N/A 17830.8 16002 AW2 RSVD N/A 16916.4 16916.