PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache Datasheet Product Features § § § § Binary compatible with applications running on previous members of the Intel microprocessor family Optimized for 32-bit applications running on advanced 32-bit operating systems Dynamic Independent Bus architecture: separate dedicated external 133 MHz System Bus and dedicated internal cache bus operating at full processor core speed § Power Management capabilities § System Management mode § Multiple low
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache TABLE OF CONTENTS PRODUCT F EATURES .................................................................................................................................................... I 1. INTRODUCTION.....................................................................................................................................................6 2. TERMINOLOGY............................................................................
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache 6.2.3 MEASUREMENTS FOR THERMAL SPECIFICATIONS............................................................57 7. MECHANICAL SPECIFICATIONS ................................................................................................................58 7.1 W EIGHT ................................................................................................................................................................. 62 7.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache 10.1.35 PICCLK (I) ................................................................................................................................................94 10.1.36 PICD[1:0] (I/O) .......................................................................................................................................95 10.1.37 PRDY# (O)..................................................................................................
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache 1. INTRODUCTION The Pentium® III Xeon™ processor at 600 MHz+, like the Pentium® Pro, Pentium® II, Pentium® III, Pentium® II Xeon™ and Pentium® III Xeon™ processor’s, implements a Dynamic Execution micro-architecture, a unique combination of multiple branch prediction, data flow analysis, and speculative execution. The Pentium III Xeon processor at 600 MHz+ is available in a 256K cache size.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache TERMINOLOGY 2. TERMINOLOGY In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a signal is in the active state (based on the name of the signal) when driven to a low level. For example, when FLUSH# is low, a flush has been requested. When NMI is high, a non-maskable interrupt has occurred.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache TERMINOLOGY • • • SC 330 processor — refers to the Pentium II Xeon processor, Pentium III Xeon processor, or 600+ MHz Pentium III Xeon processor. SC330.1 — refers to the 600+ MHz Pentium III Xeon processor’s added cartridge pin functionality. The SC 330.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS 3. ELECTRICAL SPECIFICATIONS 3.1 System Bus and VREF The Pentium III Xeon processor at 600MHz+ signals uses a variation of the Pentium Pro processor GTL+ signaling technology. The Pentium III Xeon processor at 600 MHz+ differs from the Pentium II processor and Pentium Pro processor in its output buffer implementation.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS 3.3 Decoupling Guidelines Due to the large number of transistors and high internal clock speeds, the Pentium® III Xeon™ processor at 600 MHz+ is capable of generating large average current swings between low and full power states. This causes voltages on power planes to sag below their nominal values if bulk decoupling is not adequate.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS NOTE: The frequency multipliers supported are shown in Table 1; other combinations will not be validated nor supported by Intel. Also, each multiplier is only valid for use on the product of the frequency indicated in Table 1. Clock multiplying within the processor is provided by the internal PLL, requiring a constant frequency BCLK input.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS 2.5 V 2.5 V 1K Ω Mux A20M# 1-4 Processors IGNNE# LINT1/NMI LINT0/INTR Set Ratio: CRESET# 2 000809 Figure 2. Logical1 Schematic for Clock Ratio Pin Sharing NOTES: 1. Signal Integrity issues may require this circuit to be modified. 2. Current Intel 840 chipsets do not implement the CRESET# signal. 3.4.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS recommended range of values to support for the processor core. A ‘1’ in this table refers to an open pin and ‘0’ refers to a short to ground. The definition provided below is a superset of the definition previously defined for the Pentium Pro processor (VID4 was not used by the Pentium Pro processor) and is common to the Pentium® III Xeon™ processor at 600 MHz+ (for VCC_ CORE only).
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS 3.6 System Bus Unused Pins and Test Pins Unless otherwise specified, All RESERVED_XXX pins must remain unconnected. Note that pins that are newly marked as RESERVED in this document may be tied to a power rail in existing baseboards.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Table 3.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS A Debug Port is described in Chapter 8. The Debug Port must be placed at the start and end of the TAP chain with TDI to the first component coming from the Debug Port and TDO from the last component going to the Debug Port. In an MP system, be cautious when including an empty SC330 connector in the scan chain.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS voltage clamp, with the exception of BCLK, PICCLK and PWRGOOD. The DC specifications for these pins are listed in Table 8 and Table 9. NOTE Unless otherwise noted, each specification applies to all Pentium® III Xeon™ processors at 600 MHz+. Specifications are only valid while meeting specifications for case temperature, clock frequency and input voltages.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Table 6. Current Specifications 1,10 Symbol Parameter Icc_core Max Unit Notes 600 MHz 8.7 A 2 667 MHz 9.4 733 MHz 10.0 800 MHz 10.9 866 MHz 12.4 933 MHz 13.1 1 GHz 14.3 600 MHz 5.3 A 2 667 MHz 5.7 733 MHz 6.0 800 MHz 6.6 866 MHz 7.5 933 MHz 7.9 1 GHz 8.7 Icc_core 600 MHz 2.2 A 2 (@ 11.4V VC_CORE) 667 MHz 2.4 733 MHz 2.5 800 MHz 2.7 866 MHz 3.2 933 MHz 3.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Table 6. Current Specifications 1,10 Symbol Parameter ICCTAP ICC for TAP power supply ICCSMBus ICC for SMBus power supply Min Typ 3 Max Unit 100 mA 22.5 mA Notes 8 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. “FMB” is a suggested design guideline for flexible motherboard design. 2.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Table 8. CMOS, TAP, Clock and APIC Signal Groups, DC Specifications at the processor edge fingers Symbol Parameter Min Max Unit Notes V IL Input Low Voltage -0.150 0.7 V 6 V IH Input High Voltage 1.7 2.625 V 2.5V + 5% maximum, 7 2.0 2.625 V 2.5V + 5% maximum, 4, 5 (PICCLK & PWRGD only) V OL Output Low Voltage 0.5 V Parameter measured at 14mA V OH Output High Voltage 2.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Table 9. SMBus Signal Group, DC Specifications at the processor edge fingers Symbol Parameter Min Max Unit V IL Input Low Voltage -0.3 0.3 x VCC_SMB V V IH Input High Voltage 0.7 x VCCSMB 3.465 V V OL Output Low Voltage 0.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Table 11 Internal Parameters for the AGTL+ Bus Symbol Parameter RTT Termination Resistor V REF Min Bus Reference Voltage 2/3 V TT 50mV Typ Max 150 2/3 V TT 2/3 V TT + 50mV Units Notes ohm 1 V 2 NOTES: 1. The Pentium III Xeon processor at 600 MHz+ contains AGTL+ termination resistors on the processor. 2. 3.12 VREF is generated on the processor substrate.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Table 12. System Bus AC Specifications (Clock) at the processor Core Pins 1, 2, 3 T# Parameter System Bus Frequency T1: BCLK Period T2: BCLK Period Stability Min Nom Max Unit 132.29 133.71 MHz 125 133.33 7.5 Notes 4 9 nS ±150 Figure 4 4, 5 pS 6, 7 T3: BCLK High Time 1.4 nS 4, 12 @>2.0V T4: BCLK Low Time 1.4 T5: BCLK Rise Time 0.75 T6: BCLK Fall Time 0.75 nS 4, 12 @<0.5V 1.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Table 13. AGTL+ Signal Group, System Bus AC Specifications at the processors Core 1 RL = 50 ohms Terminated to 1.5V T# Parameter Min Max Unit Figure Notes T7: AGTL+ Output Valid Delay -0.05 2.65 nS Figure 5 2 T8: AGTL+ Input Setup Time 1.2 nS Figure 6 3, 4, 6 T9: AGTL+ Input Hold Time 0.80 nS Figure 6 5 T10: RESET# Pulse Width 1.00 mS Figure 8 5 NOTES: 1. 2.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Table 15.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Table 17. System Bus AC Specifications (TAP Connection) at the processor Core 1 T# Parameter Min T30: TCK Frequency T31: TCK Period 60.0 nS Figure 3 T32: TCK High Time 25.0 nS Figure 3 @1.7V 2 T33: TCK Low Time 25.0 nS Figure 3 @0.7V 2 T34: TCK Rise Time 5.0 nS Figure 3 (0.7V–1.7V) 2, 3 T35: TCK Fall Time 5.0 nS Figure 3 (1.7V–0.7V) 2, 3 T36: TRST# Pulse Width 40.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Table 18. SMBus Signal Group, AC Specifications at the Edge Fingers T# Parameter Min Max Unit 100 KHz Figure T50: SMBCLK Frequency T51: SMBCLK Period 10 uS Figure 4 T52: SMBCLK High Time 4.0 uS Figure 4 T53: SMBCLK Low Time 4.7 uS Figure 4 T54: SMBCLK Rise Time 1.0 uS Figure 4 T55: SMBCLK Fall Time 0.3 uS Figure 4 T56: SMBus Output Valid Delay 1.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS Th Tr 2.97V 2.46V SCLK 0.84V 0.84V Tf Tl Tr = T54 Tf = T55 Th = T52 Tl = T53 SMBUSCLK Figure 4 . SMBCLK Clock Waveform Clock Tx Tx Signal V Valid Valid T pw Tx = T7, T29 (Valid Delay) Tpw = T14, T15 (Pulse Wdith) V = 2/3 V TT for GTL+ signal group; 1.25V for CMOS, and APIC signal groups Figure 5 .
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS BCLK Tu T t RESET# T v Ty Configuration (A20M#, IGNNE#, LINT[1:0]) Tz Tx Safe Valid Tw Configuration (A[14:5]#, BR0#, FLUSH#, INIT#) Valid Tt = T9 (GTL+ Input Hold Time) Tu = T8 (GTL+ Input Setup Time) Tv = T10 (RESET# Pulse Width) Tw = T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time) Tx = T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time) T20 (R
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache ELECTRICAL SPECIFICATIONS 1.25V TCK TDI, TMS Tv Tw Tr Ts 1.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache SIGNAL QUALITY 4. SIGNAL QUALITY Signals driven on the Pentium® III Xeon™ processor at 600 MHz+ system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long-term reliability of the component. Specifications are provided for simulation at the processor core.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache SIGNAL QUALITY 4.2.1 AGTL+ Ringback Tolerance Specifications Table 21 provides the AGTL+ signal quality specifications for Pentium III Xeon processors at 600 MHz+ for use in simulating signal quality at the processor core pads. Figure 12 describes the signal quality waveform for AGTL+ signals at the processor core pads. For more information on the AGTL+ interface, see the Pentium II processor Developer's Manual (Order Number 243341).
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache SIGNAL QUALITY 4.2.2.1 Overshoot/Undershoot Magnitude Overshoot magnitude describes the maximum potential difference between a signal and its reference voltage level, Vss. Undershoot Magnitude describes the maximum potential difference between a signal and VTT (undershoot). While overshoot can be measured relative to VSS using one probe (probe on signal and ground lead on VSS), Undershoot must be measured relative to VTT .
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache SIGNAL QUALITY • If multiple overshoots and/or multiple undershoots occur, measure the worst-case pulse duration for each magnitude and compare the results against the AF = 1 specifications (note: multiple overshoot/undershoot events within one clock cycle must have their pulse durations summed together to determine the total pulse duration).
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache SIGNAL QUALITY Figure 13. Maximum Acceptable Overshoot/Undershoot Waveform1,2,3,4,5,6,7,8 NOTES: 1. Overshoot Magnitude and Undershoot Magnitude are absolute values and should never exceed 2.3V under any circumstances. 2. Overshoot is measured relative to VSS. 3. Undershoot is measured relative to VTT. 4. Overshoot/Undershoot Pulse Duration is measured relative to 1.635V. 5.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache SIGNAL QUALITY Overshoot Settling Limit V =H I V CC 2.5 Rising-Edge Ringback Falling-Edge Ringback Voltage Settling Limit V LO V SS Time Undershoot RINGBACK Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback 4.3.1 2.5V Signal Overshoot/Undershoot Guidelines The Overshoot/Undershoot guideline limits transitions beyond V CC or V SS due to fast signal edge rates.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache SIGNAL QUALITY Intel recommends that platforms meet the Absolute Maximum Specifications for Overshoot and Undershoot on BCLK. This ensures that the BCLK I/O Buffer will meet specifications regardless of Overshoot or Undershoot Pulse Duration within a Clock cycle with 50% Duty Cycle. For all Pentium III Xeon processors at 600 MHz+ , the maximum Overshoot level is 3.3V. The Absolute maximum Undershoot is –0.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache SIGNAL QUALITY 4.3.5 2.5V TOLERANT BUFFER SETTLING LIMIT GUIDELINE Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition. The amount allowed is 10% of the total signal swing (V HI – VLO) above and below its final value. A signal should be within the settling limits of its final value, when either in its high state or low state, before it transitions again.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES 5. PROCESSOR FEATURES 5.1 Low Power States and Clock Control The Pentium® III Xeon™ processor at 600 MHz+ allows the use of Auto HALT, Stop-Grant, and Sleep states to reduce power consumption by stopping the clock to specific internal sections of the processor, depending on each particular state. There is no Deep Sleep state on the Pentium III Xeon processor at 600 MHz+.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES HALT Instruction and HALT Bus Cycle Generated 2. Auto HALT Power Down State BCLK running. Snoops and interrupts allowed. 1. INIT#, BINIT#, INTR, NMI, STP Snoop Snoop Event Event Occurs 4. STP CLK Serviced HALT/Grant Snoop State # De -ass erte CLK # As s erte d STPCLK# STPCLK# Asserted De-asserted d Snoop Event Occurs 3. Stop Grant State BCLK running. BCLK running. Service snoops to caches.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES 5.1.5 SLEEP STATE — STATE 5 The Sleep state is a very low power state in which the processor maintains its context, maintains the PLL, and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES R 10K 1/16W R 10K 1/16W 5% OEM INTEL EEPROM A Stby ALERT# 5% R 10K 1/16W 5% Vcc Vcc A0 WP A0 WP A1 SC A1 SC A2 SD A2 SD Core C EEPROM Vcc R 10K 1/16W 5% A2D R 10K 5% 1/16W A0 SC A1 SD R 10K 1/16W 5% R 10K 1/16W 5% R 10K 1/16W 5% SA1 R 10K 1/16W 5% SDA SCL WP R 10K 1/16W 5% SA0 SMB_V CC SA2 SMBALERT Figure 16. Logical1 Schematic of SMBus Circuitry NOTES: 1.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES Systems implementing analog sensing should read the PIROM first, then compare that value with the measured VIN_SENSE rather than assuming any specific value. The value of AN_CORE_VSENSE is implementation dependent and cannot be assumed to be any particular value. Systems may derive benefit by monitoring its stability, but should not make assumptions about its value.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES Table 26.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES CARTRIDGE: 32h PART NUMBERS: 38h THERMAL REF.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES 5.2.2 SCRATCH EEPROM Also available on the SMBus is an EEPROM that may be used for other data at the system or processor vendor’s discretion. This device has a pull-down on the WP control pin through a 10K Ω resistor, as implemented on all previous Pentium® II Xeon™ and Pentium III Xeon processors. This will allow the OEM EEPROM to be programmed in systems with no manipulation of this signal.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES Table 28. Receive Byte SMBus Packet S Device Address R/ W* A* Data A* P 1 7 bits 1 0 8 bits 1 1 Table 28 diagrams the Receive Byte packet that performs as a current address read. The start condition is followed by a device select address field and a read flag. The device decodes its address and drives acknowledge low.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES uniquely determined for each unit. The procedure causes each unit to dissipate its maximum power (which can vary from unit to unit) while at the same time maintaining the thermal plate at its maximum specified operating temperature. Correctly used, this feature permits an efficient thermal solution while preserving data integrity.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES 1. This is an 8-bit field. The device that sent the alert will respond to the ARA Packet with its address in the seven most significant bits. The least significant bit is undefined and may return as a ‘1’ or ‘0’. See Section 5.2.5 for details on the Thermal Sensor Device addressing. Table 36.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES 5.2.6.3 Status Register The status register shown in Table 37 indicates which (if any) thermal value thresholds have been exceeded. It also indicates if a conversion is in progress or if an open circuit has been detected in the processor core thermal diode connection. A status register read is required to clear any alarm bits that are set.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES Table 38. Thermal Sensor Configuration Register Bit Name Reset State Function 7 (MSB) RESERVED 0 Reserved for future use. 6 RUN/STOP 0 Standby mode control bit. If high, the device immediately stops converting, and enters standby mode. If low, the device converts in either one-shot mode or automatically updates on a timed basis.. 5-0 RESERVED 0 Reserved for future use. 5.2.6.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache PROCESSOR FEATURES The thermal sensor latches the SA1 and SA2 signals at power up. System designers should ensure that these signals are at valid input levels before the thermal sensor powers up. This should be done by pulling the pins to V CCSMB or V SS via a 1K-ohm or smaller resistor. Additionally, SA2 may be left unconnected to achieve the tri-state or “Z” state.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache THERMAL SPECIFICATIONS 6. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS The Pentium® III Xeon™ processor at 600 MHz+ will use a thermal plate for heat sink attachment. The thermal plate interface is intended to provide for multiple types of thermal solutions. This chapter will provide the necessary data for a thermal solution to be developed. See Figure 17 for thermal plate location. Figure 17. Thermal Plate View 6.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache THERMAL SPECIFICATIONS Table 42 Power Dissipation 1 Frequency Core Power 2 (W) 2.8V OCVR Power (W) 5/12V OCVR Power (W) 2.8V Cartridge Power 3 (W) 5/12V Cartridge Power 3 (W) 2.8V Thermal Power 4 ,7 (W) 5/12V Thermal Power 4 ,7 (W) Power 5 Min Tplate °C Max Tplate °C 600 MHz 16.9 3.9 4.8 20.8 21.6 18.8 19.2 2 0 55 667 MHz 18.6 4.4 5.3 23.0 23.9 20.8 21.3 2 0 55 733 MHz 20.4 4.8 5.8 25.2 26.2 22.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache THERMAL SPECIFICATIONS 6.1.2 PLATE FLATNESS SPECIFICATION The thermal plate flatness for the Pentium® III Xeon™ processor at 600 MHz+ is specified to 0.010” across the entire thermal plate surface, with no more than a 0.003” step anywhere on the surface of the plate, as shown in Figure 18. Figure 18. Plate Flatness Reference 6.2 Processor Thermal Analysis 6.2.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache THERMAL SPECIFICATIONS between the thermal plate and heat sink. The other controllable factor (thetaθ heat sink to air ) is determined by the design of the heat sink and airflow around the heat sink. General Information on thermal interfaces and heat sink design constraints can be found in AP-586, Pentium II Processor Thermal Design Guidelines (Order Number 243331). 6.2.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache THERMAL SPECIFICATIONS 6.2.3 MEASUREMENTS FOR THERMAL SPECIFICATIONS 6.2.3.1 Plate Temperature Measurement To ensure functional and reliable processor operation, the processor's thermal plate temperature (TPLATE) must be maintained at or below the maximum TPLATE and at or above the minimum TPLATE specified in Table 42.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS 7. MECHANICAL SPECIFICATIONS Pentium® III Xeon™ processor at 600 MHz+ uses S.E.C. cartridge package technology. The S.E.C. cartridge contains the processor core, OCVR and other components. The S.E.C. cartridge package connects to the baseboard through an edge connector. Mechanical specifications for the processor are given in this section. See Section 1.1.1 for a complete terminology listing.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Figure 23. S.E.C.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Figure 24. S.E.C.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Figure 25. SEC Cartridge Retention Enabling Details 1. Maximum protrusions of the mechanical heat sink attach media into cartridge during assembly or in an installed condition not to exceed 0.160” from external face of thermal plate. 2. Specified cover retention indent dimension is at the external end of the indent. Indent walls have 1.0degree draft, with the wider section on the external end. 3.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS 7.1 Weight The maximum weight of a Pentium® III Xeon™ processor at 600 MHz+ and thermal solution is approximately 500 grams. 7.2 Cartridge to Connector Mating Details The staggered edge connector layout of the Pentium III Xeon processor at 600 MHz+ makes the processor susceptible to damage from cartridge insertion while power is applied to the connector.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Figure 28. Front View of Connector Mating Details NOTES: Retention devices for this cartridge must accommodate this cartridge “Float” relative to connector, without preload to the edge contacts in “X” and “Y” axes.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS 7.3 Substrate Edge Finger Signal Listing Table 44 is the Pentium® III Xeon™ processor at 600 MHz+ substrate edge finger listing in order by pin number. Table 45 is the Pentium III Xeon processor at 600 MHz+ substrate edge connector listing in order by pin name. These tables reflect the new SC330.1 pin definition, new or changed pins definitions are shown in bold. Table 44.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Table 44. Signal Listing in Order by Pin Number Pin No. A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 Pin Name DEP#[3] VSS DEP#[5] DEP#[6] VSS D#[61] D#[55] VSS D#[60] D#[53] VSS D#[57] D#[46] VSS D#[49] D#[51] VSS VIN_SENSE VSS D#[42] D#[45] VSS D#[39] TEST_2.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Table 44. Signal Listing in Order by Pin Number Pin No.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Table 44. Signal Listing in Order by Pin Number Pin No.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Table 45. Signal Listing in Order by Pin Name Pin No.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Pin No.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Pin No.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Pin No. A9 A7 B18 A151 B160 B161 B12 B15 B16 A18 A20 A23 A62 B27 A98 B4 A82 A24 B19 A130 B21 B100 B103 B11 B14 B17 B2 B20 B23 B26 B29 B32 B35 B38 B41 B44 B47 B5 B50 B53 B56 B58 B61 B64 B67 B70 B73 B76 B79 B8 B82 B85 B88 B91 B94 B97 B106 B109 B112 B115 Pin Name SELFSB0 SELFSB1 SLP# SMBALERT# SMBCLK SMBDAT SMI# STPCLK# TCK TDI TDO TEST_2.5_A23 TEST_2.5_A62 TEST_2.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Pin No.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache MECHANICAL SPECIFICATIONS Pin No.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache INTEGRATION TOOLS 8. INTEGRATION TOOLS The integration tool set for Pentium® III Xeon™ processor at 600 MHz+ system designs will include an InTarget Probe (ITP) for program execution control, register/memory/IO access, and breakpoint control. This tool provides functionality commonly associated with debuggers and emulators.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache INTEGRATION TOOLS The ITP will connect to the system through the debug port. Recommended connectors, to mate the ITP cable with the debug port on the board, are available in either a vertical or right angle configuration. Both configurations fit into the same board footprint. The connectors are manufactured by AMP Incorporated and are in the AMPMODU System 50 line.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache INTEGRATION TOOLS 8.1.5 DEBUG PORT SIGNAL DESCRIPTIONS Table 46 describes the debug port signals and provides the pin assignment. Table 46. Debug Port Pinout Description and Requirements 1 Name RESET# Pin 1 Description Reset signal from MP cluster to ITP. Specification Requirement Terminate2 signal properly at the debug port. Debug port must be at the end of the signal trace. DBRESET# 3 Allows ITP to reset entire target system.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache INTEGRATION TOOLS Table 46. Debug Port Pinout Description and Requirements 1 Name Pin Description Specification Requirement Notes TDO 10 Test data output signal from last component in boundary scan chain of MP cluster to ITP; test output is read serially. Add 150-ohm pull-up resistor (to VCC_TAP). Operates synchronously with TCK. Each Pentium® III Xeon™ processor at 600 MHz+ has a 25 ohm driver.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache INTEGRATION TOOLS Table 46. Debug Port Pinout Description and Requirements 1 Name Pin Description Specification Requirement Notes Pentium® III Xeon™ processor at 600 MHz+ . GND 2, 4, 6, 13, 15, 17, 19, 21, 23, 25, 27 Signal ground. Connect all pins to signal ground. NOTES: 1. Resistor values with “~” preceding them can vary from the specified value; use resistor as close as possible to the value specified. 2. 3.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache INTEGRATION TOOLS The DBRESET# output signal from the ITP is an open drain with about 5 ohms of RDS. The usual implementation is to connect it to the PWROK open drain signal on the PCIset components as an OR input to initiate a system reset. In order for the DBRESET# signal to work properly, it must actually reset the entire target system.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache INTEGRATION TOOLS processor #1 processor #2 2.5V Buffers 74LVQ244 Type 100 nH 2.5V Pull up Resistor 100 nH 56 pF 56 pF TCK 100 nH 56 pF To each device, other JTAG ... Figure 31. TCK with individual buffering scheme The ITP buffer board drives the TCK signal through the debug port, to the buffered device(s). NOTE The buffer rise and fall edge rates should NOT be FASTER than 3nS.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache INTEGRATION TOOLS V CC TAP TDI TDO SC 330.1 Processor TDI TDO TDI SC 330.1 Processor TDO TDI TDO Debug Port (ITP) PCIset Component Note: See previous table for recommended pull-up resistor values. 000799c 000799c Figure 32. System Preferred Debug Port Layout 8.2 Logic Analyzer Interconnect (LAI) and Trace Capture Tool Considerations 8.2.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache BOXED PROCESSOR SPECIFICATIONS 9. BOXED PROCESSOR SPECIFICATIONS 9.1 Introduction The Pentium® III Xeon™ processor at 600 MHz+ is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and off-the-shelf components. The boxed Pentium III Xeon processor at 600 MHz+ is supplied with an attached passive heat sink.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache BOXED PROCESSOR SPECIFICATIONS A C D B Figure 34.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache BOXED PROCESSOR SPECIFICATIONS F E Figure 35. Front View Space Requirements for the Boxed Processor 9.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS Table 47. Boxed Processor Heat sink Dimensions Fig. Ref. Label Dimensions (Inches) Min Typ A Heat sink Depth (off heat sink attach point) B Heat sink Height (above baseboard) C Heat sink Base Thickness D Heat sink Total Height at Fins 4.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache BOXED PROCESSOR SPECIFICATIONS 9.3 Thermal Specifications This section describes the cooling requirements of the heat sink solution utilized by the boxed processor. 9.3.1 Boxed Processor Cooling Requirements The boxed processor passive heat sink requires airflow horizontally across the heat sink to cool the processor.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache BOXED PROCESSOR SPECIFICATIONS perform with very little local airflow. Therefore, θPA is virtually constant and independent of the speed and direction of airflow across the heat sink. 9.3.2 Optional auxiliary fan attachment The boxed processor’s passive heat sink includes features that allow for attachment of a standard auxiliary fan to improve airflow over the passive heat sink. A standard 40mm, 50mm, or 60mm fan can be attached.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache BOXED PROCESSOR SPECIFICATIONS 4.24 1.5 Figure 38. Side View Space Recommendation for the Auxiliary Fan Figure 39. Front View Space Recommendation for the Auxiliary Fan 9.3.2.2 Fan power recommendations for auxiliary fan To facilitate power to the auxiliary fan and provide fan monitoring, a fan-sense capable power header may be provided on the baseboard near every processor that may need an auxiliary fan.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache BOXED PROCESSOR SPECIFICATIONS also recommended that the power header be consistent with the power header for other boxed processors that feature a fan-sense capable fan heat sink. Figure 40 shows the boxed processor’s standard fan/heat sink power cable connector. Table 48 shows the boxed processor’s standard fan power cable connector requirements. The actual requirements for the auxiliary fan power may vary.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX 10. APPENDIX This appendix provides an alphabetical listing of all Pentium® III Xeon™ processor at 600 MHz+ signals and tables that summarize the signals by direction: output, input, and I/O. 10.1 Alphabetical Signals Reference This section provides an alphabetical listing of all Pentium III Xeon processor at 600 MHz+ signals. 10.1.1 A[35:03]# (I/O) The A[35:3]# (Address) signals define a 236-byte physical memory address space.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache 10.1.6 BCLK (I) APPENDIX The BCLK (Bus Clock) is a 2.5V tolerant signal that determines the bus frequency. All Pentium® III Xeon™ processor at 600 MHz+ system bus agents must receive this signal to drive their outputs and latch their inputs on the BCLK rising edge. All external timing parameters are specified with respect to the BCLK signal. 10.1.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX The BR[3:1]# (Bus Request) pins drive the BREQ[3:0]# signals on the system. The BR[3:0]# pins are interconnected in a rotating manner to other processors’ BR[3:0]# pins. Table 49 gives the interconnect between the processor and bus signals for a 2-way system. Table 49.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX Table 51. BR[3] and BR[1:0]# Signals Rotating Interconnect, 2-Way System Bus Signal Agent 0 Pins Agent 1 Pins BREQ0# BR0# BR3# BREQ1# BR1# BR0# BREQ2# N/C N/C BREQ3# N/C N/C During power-up configuration, the central agent must assert its BR0# signal. All symmetric agents sample their BR[3:0]# pins on active-to-inactive transition of RESET#.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache 10.1.21 FERR# (O) APPENDIX The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel387™ coprocessor, and is included for compatibility with systems using DOStype floating-point error reporting. 10.1.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache 10.1.28 INTR - see LINT[0] APPENDIX 10.1.29 LINT[1:0] (I) The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all APIC Bus agents, including all processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a non-maskable interrupt.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache 10.1.36 PICD[1:0] (I/O) APPENDIX The PICD[1:0] (APIC Data) signals are used for bi-directional serial message passing on the APIC bus, and must connect the appropriate pins of all processors and core logic or I/O APIC components on the APIC bus. 10.1.37 PRDY# (O) The PRDY (Probe Ready) signal is a processor output used by debug tools to determine processor debug readiness. 10.1.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX 1 3 mS RESET# VRM_PWRGD 0.5 mS (max) OCVR_ O K 1 mS CPU_PWR_GD 2.8/5/12V 90% of Vin Nominal Vin (OCVR) VCC_CPU Vout (OCVR) Figure 41. PWRGD Relationship at Power-On NOTES: 1. VCC_CORE must be applied to the OCVR input before OCVR_OK can become valid (even though it could be pulled high if the VCC_SMB supply is turned on, see figure 41. 2. 3. The OCVR_OK signal is not guaranteed to be valid until 0.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX Pull-up for Pentium® III Xeon™ Processor 3V->5V buffer (7408) 3.3V 5V Vcc_smb(3.3V) +5V VRM OCVR OCVR_EN OUTEN PWRGD OCVR_OK 3.3V 5V Other PS’s, VRMs, OCVRs with open-drain PWR_GDs OCVR_EN PWR_GD_PS OCVR_OK CPU_PWR_GD CPU_PWRGD CPU_RESET# Delay Logic Processor Core Reset Logic Figure 42. PWRGD Implementation 10.1.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all Pentium® III Xeon™ processor at 600 MHz+ system bus agents. 10.1.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX Processor Pentium® III Xeon™ processor at 600 MHz+ Pin Location Pin Name Functionality A7 SELFSB1 Output, Frequency Detect A9 SELFSB0 Input, Frequency Selection. SELFSB1: Output, (Frequency Detect). 133Mhz = N/C SELFSB0: Pentium III Xeon processor at 600 MHz+ : Input; (Frequency Select). 133MHz = Pull up to 2.5V Table 52. Description of SELFSB pins 10.1.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low power Stop Grant state. The processor issues a Stop Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop Grant state.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX pins. The power supply must supply the voltage that is requested by these pins, or disable itself. See section 3.9 for the maximum rating for these signals. 10.1.63 VIN_SENSE VIN_SENSE (formerly called CPU_SENSE) is routed from edge-connector pin A56 to the VCC_ CORE power plane. VIN_SENSE provides remote sensing capabilities for the voltage seen at the input of the OCVR.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX Table 54.
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache APPENDIX Table 55. I/O Signals (Single Driver) Name Active Level Clock Signal Group Qualified RP# Low BCLK AGTL+ I/O ADS#, ADS#+1 SMBDAT High SMBCLK SMBus I/O Table 56.