Datasheet

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Intel

Pentium

III Processor for the

SC242 at 450 MHz to 1.0 GHz

Datasheet

Product Features

The Intel

Pentium

III processor is designed for high-performance desktops and for

workstations and servers. It is binary compatible with previous Intel Architecture processors.

The Pentium III processor provides great performance for applications running on advanced

operating systems such as Microsoft Windows* 98, Windows NT* and UNIX*. This is achieved

by integrating the best attributes of Intel processors—the dynamic execution, Dual Independent

Bus architecture plus Intel

MMX™ technology and Internet Streaming SIMD Extensions—

bringing a new level of performance for systems buyers. ThePentium III processor is scaleable to

two processors in a multiprocessor system and extends the power of the Intel

Pentium

processor with performance headroom for business media, communication and internet

capabilities. Systems based on Pentium III processors also include the latest features to simplify

system management and lower the cost of ownership for large and small business environments.

The Pentium III processor offers great performance for today’s and tomorrow’s applications.

■ Available in 1.0B GHz, 933, 866, 800EB,

733, 667, 600B, 600EB, 533B, and 533EB

MHz speeds support a 133 MHz system

bus (‘B’ denotes support for a 133 MHz

system bus where a processor is available

at the same specific core frequency in

seperate 100 MHz and 133 MHz Front Side

Bus versions; ‘E’ denotes support for

Advanced Transfer Cache and Advanced

System Buffering)

■ Available in 1.0 GHz, 850, 800, 750, 700,

650, 600E, 600, 550E, 550, 500, and

450 MHz speeds support a 100 MHz

system bus (‘E’ denotes support for

Advanced Transfer Cache and Advanced

System Buffering)

■ Available in versions that incorporate

256-KB Advanced Transfer Cache (on-die,

full speed Level 2 (L2) cache with Error

Correcting Code (ECC)) or versions that

incorporate a discrete, half-speed, 512-KB

in-package L2 cache with ECC

■ Dual Independent Bus (DIB) architecture

increases bandwidth and performance over

single-bus processors

■ Internet Streaming SIMD Extensions for

enhanced video, sound and 3D

performance

■ Binary compatible with applications

running on previous members of the Intel

microprocessor line

■ Dynamic execution micro architecture

■ Power Management capabilities

—System Management mode

—Multiple low-power states

■ Intel Processor Serial Number

■ Optimized for 32-bit applications running

on advanced 32-bit operating systems

■ Single Edge Contact Cartridge (S.E.C.C.)

and S.E.C.C.2 packaging technology; the

S.E.C. cartridges deliver high performance

with improved handling protection and

socketability

■ Integrated high performance 16 KB

instruction and 16-KB data, nonblocking,

level one cache

■ Enables systems which are scaleable up to

two processors

■ Error-correcting code for System Bus data

Document Number: 244452-009

July 2002

SC242 / SECC2 Package

Summary of content (101 pages)

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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Datasheet Product Features ■ ■ ■ ■ Available in 1.0B GHz, 933, 866, 800EB, 733, 667, 600B, 600EB, 533B, and 533EB MHz speeds support a 133 MHz system bus (‘B’ denotes support for a 133 MHz system bus where a processor is available at the same specific core frequency in seperate 100 MHz and 133 MHz Front Side Bus versions; ‘E’ denotes support for Advanced Transfer Cache and Advanced System Buffering) Available in 1.
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT.
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Contents 1.0 Introduction......................................................................................................................... 9 1.1 1.2 2.0 Electrical Specifications....................................................................................................13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 3.0 Processor System Bus and VREF ........................................................................13 Clock Control and Low Power States.................
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.0 Thermal Specifications and Design Considerations......................................................... 49 4.1 5.0 S.E.C.C. and S.E.C.C.2 Mechanical Specifications......................................................... 54 5.1 5.2 5.3 5.4 5.5 5.6 6.0 6.3 6.4 Introduction ......................................................................................................... 88 Fan Heatsink Mechanical Specifications............................................................. 88 6.2.
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Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 28 30 31 32 33 34 35 36 37 38 Datasheet Second Level (L2) Cache Implementation ........................................................... 9 AGTL+ Bus Topology ..........................................................................................14 Stop Clock State Machine ...................................................................................
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39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact Dimensions (Detail A) ......................................................................................... 64 S.E.C.C.2 Packaged Processor Substrate (CPUID=067xh) — Keep-In Zones..................................................................................................... 65 S.E.C.C.2 Packaged Processor Substrate (CPUID=068xh) — Keep-In Zones...........................................
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18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Datasheet System Bus AC Specifications (TAP Connection) at the Processor Core Pins.............................................................................................................36 BCLK, PICCLK, and PWRGOOD Signal Quality Specifications at the Processor Core ...................................................................................................
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Revision History Revision -009 8 Description • Removed 1.13 GHz processor frequency. Minor edits for clarity.
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Introduction 1.0 Introduction The Intel® Pentium® III processor is the next member of the P6 family, in the Intel® IA-32 processor line. Like the Intel® Pentium® II processor, the Pentium III processor implements the Dynamic Execution microarchitecture - a unique combination of multiple branch prediction, data flow analysis, and speculative execution.
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Introduction 1.1 Terminology In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a signal is in the active state (based on the name of the signal) when driven to a low level. For example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable interrupt has occurred.
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Introduction 1.1.2 Processor Naming Convention A letter(s) is added to certain processors (e.g., 600B MHz) when the core frequency alone may not uniquely identify the processor. Below is a summary what the letter means as well as a table listing all Pentium III processors currently available. • “B” — 133 MHz System Bus Frequency • “E” — Processor with “Advanced Transfer Cache” (CPUID=068xh) Table 1.
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Introduction 1.2 Related Documents The reader of this specification should also be familiar with material and concepts in the documents listed in Table 2. These documents, and a complete list of Pentium III processor reference material, can be found on the Intel Developers’ Insight web site located at http://developer.intel.com. Table 2.
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Electrical Specifications 2.0 Electrical Specifications 2.1 Processor System Bus and VREF Most Pentium III processor signals use a variation of the low voltage Gunning Transceiver Logic (GTL) signaling technology. The Pentium Pro processor system bus specification is similar to the GTL specification, but was enhanced to provide larger noise margins and reduced ringing. The improvements are accomplished by increasing the termination voltage level and controlling the edge rates.
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Electrical Specifications Figure 2. AGTL+ Bus Topology Pentium III Processor 2.2 ASIC Pentium III Processor Clock Control and Low Power States Pentium III processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. See Figure 3 for a visual representation of the Pentium III processor low power states. Figure 3.
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Electrical Specifications For the processor to fully realize the low current consumption of the Stop-Grant, Sleep, and Deep Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02Ah (Hex), bit 26 must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks during these modes. For more information, see the Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide (Document Number 243192).
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Electrical Specifications 2.2.4 HALT/Grant Snoop State—State 4 The processor will respond to snoop transactions on the Pentium III processor system bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the Pentium III processor system bus has been serviced (whether by the processor or another agent on the Pentium III processor system bus).
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Electrical Specifications 2.2.7 Clock Control The processor provides the clock signal to the L2 cache. During AutoHALT Power Down and Stop-Grant states, the processor will process a system bus snoop. The processor will not stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into the Halt/ Grant Snoop state will allow the L2 cache to be snooped, similar to the Normal state.
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Electrical Specifications 2.4.1 Processor VCCCORE Decoupling Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep an interconnect resistance from the regulator (or VRM pins) to the SC242 connector of less than 0.3 mΩ. This can be accomplished by keeping a maximum distance of 1.0 inches between the regulator output and SC242 connector. The recommended VCCCORE interconnect is a 2.0 inch wide by 1.
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Electrical Specifications Table 3. Voltage Identification Definition Processor Pins Notes1,2 VID4 VID3 VID2 VID1 VID0 VccCORE 0 1 1 1 1 1.30 0 1 1 1 0 1.35 0 1 1 0 1 1.40 0 1 1 0 0 1.45 0 1 0 1 1 1.50 0 1 0 1 0 1.55 0 1 0 0 1 1.60 3 0 1 0 0 0 1.65 3 0 0 1 1 1 1.70 3 0 0 1 1 0 1.75 3 0 0 1 0 1 1.80 3 0 0 1 0 0 1.85 3 0 0 0 1 1 1.90 3 0 0 0 1 0 1.95 3 0 0 0 0 1 2.00 3 0 0 0 0 0 2.
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Electrical Specifications voltage regulator is stable. This will prevent the possibility of the processor supply going above the specified VCCCORE in the event of a failure in the supply for the VID lines. In the case of a DC-toDC converter, this can be accomplished by using the input voltage to the converter for the VID line pull-ups. A resistor of greater than or equal to 10 kΩ may be used to connect the VID signals to the converter input. 2.
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Electrical Specifications Table 4.
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Electrical Specifications 2.8.2 System Bus Frequency Select Signal (BSEL0) The BSEL[1:0] signals (BSEL0 is also known as 100/66#) are used to select the system bus frequency for the Pentium III processor(s). Table 5 defines the possible combinations of the signals and the frequency associated with each combination. The frequency is determined by the processor(s), and frequency synthesizer.
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Electrical Specifications Figure 5. BSEL[1:0] Example for a 100/133 MHz Capable System (100 MHz Processor Installed) 3.3V CK133 220 Ω Intel® Pentium ® III Processor 133/100# 0Ω 3.3V BSEL1 220 Ω System Shutdown Logic 0Ω GND S C 2 4 2 Processor Core 1 ΚΩ 3.3 ΚΩ GND BSEL0 Figure 6. BSEL[1:0] Example for a 100/133 MHz Capable System (133 MHz Processor Installed) 3.3V 220 Ω CK133 Intel ® Pentium ® III Processor 133/100# 1 ΚΩ 3.
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Electrical Specifications 2.10 Maximum Ratings Table 6 contains Pentium III processor stress ratings only. Functional operation at the absolute maximum and minimum is not implied nor guaranteed. The processor should not receive a clock while subjected to these conditions. Functional operating conditions are given in the AC and DC tables in Section 2.11 and Section 2.13. Extended exposure to the maximum ratings may affect device reliability.
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Electrical Specifications Table 7. Absolute Maximum Ratings (CPUID=068xh) Symbol Parameter Min Max Unit Notes TSTORAGE Processor storage temperature –40 85 °C VCCCORE and VTT Processor core voltage and Termination supply voltage with respect to VSS -0.5 2.1 V VCCL2/VCC3.3 VCC3.3 with respect to VSS –0.5 5.0 V 1 Vin1.5 1.5 V buffer input voltage VTT – 2.3 VSS + 2.3 V 2, 3, 5 Vin2.5 2.5 V buffer input voltage –0.7 3.
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Electrical Specifications Table 8. Voltage and Current Specifications (Sheet 1 of 4) Processor Symbol Parameter Min Core Freq 450 MHz 500 MHz 533 MHz 533EB MHz 550 MHz 550E MHz 600 MHz 600B MHz 600E MHz VccCORE Vcc for Processor Core 600EB MHz 650 MHz 667 MHz 700 MHz 733 MHz 750 MHz 800 MHz 26 Typ Max Unit Notes1 CPUID 0672h 2.00 2,3,4,5 0673h 2.00 2,3,4,5 0672h 2.00 2,3,4,5 0673h 2.00 2,3,4,5 0672h 2.00 2,3,4,5 0673h 2.00 2,3,4,5 0681h 1.65 2,3,4,5 0683h 1.
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Electrical Specifications Table 8. Voltage and Current Specifications (Sheet 2 of 4) Processor Symbol Parameter Min Core Freq 800EB MHz 850 MHz VccCORE Vcc for Processor Core 866 MHz 933 MHz 1.0 GHz 1.0B GHz Typ Max Unit Notes1 CPUID 0681h 1.65 2,3,4,5 0683h 1.65 2,3,4,5 0686h 1.70 2,3,4,5 0681h 1.65 2,3,4,5 0683h 1.65 2,3,4,5 0686h 1.70 2,3,4,5 0681h 1.65 0683h 1.65 0686h 1.70 2,3,4,5 0683h 1.70 2,3,4,5 0686h 1.70 2,3,4,5 0683h 1.70 2,3,4,5 0686h 1.
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Electrical Specifications Table 8.
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Electrical Specifications Table 8. Voltage and Current Specifications (Sheet 4 of 4) Processor Symbol Parameter Min Core Freq 450 MHz 500 MHz 533B MHz 533EB MHz 550 MHz 550E MHz 600 MHz 600B MHz 600E MHz 600EB MHz 650 MHz 667 MHz 700 MHz 733 MHz 750 MHz 800 MHz 800EB MHz 850 MHz 866 MHz 933 MHz 1.0 GHz 1.0B GHz Typ Max Notes1 Unit CPUID 0.80 0.90 1.00 2.50 1.00 2.50 1.00 1.00 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.50 2.
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Electrical Specifications 9. VCCL2/VCC3.3 and ICCL2/ICC3.3 supply the second level cache (“Discrete” cache type only). Unless otherwise noted, this specification applies to all Pentium III processor cache sizes. Systems should be designed for these specifications, even if a smaller cache size is used. 10.Max ICC measurements are measured at VCC max voltage, maximum temperature, under maximum signal loading conditions.
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Electrical Specifications Table 9. AGTL+ Signal Groups DC Specifications Symbol Parameter Min Max Unit Notes 1, 4, 5 VIL Input Low Voltage –0.30 –0.15 0.82 VREF – 0.20 V V 12 13 VIH Input High Voltage 1.22 VREF + 0.20 VTT VTT V 2, 3, 12 2, 3, 13 Ron Buffer On Resistance 16.67 Ω 9 Leakage Current ±100 ±100 µA µA 6, 7, 8, 12 6, 10, 11, 13 IL NOTES: 1. Unless otherwise noted, all specifications in this table apply to Pentium III processor frequencies. 2.
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Electrical Specifications 2.12 AGTL+ System Bus Specifications It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination resistors to VTT at each end of the signal trace. These termination resistors are placed electrically between the ends of the signal traces and the VTT voltage supply and generally are chosen to approximate the substrate impedance. The valid high and low levels are determined by the input buffers using a reference voltage called VREF.
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Electrical Specifications The timings specified in this section should be used in conjunction with the I/O buffer models provided by Intel. These I/O buffer models, which include package information, are available for the Pentium III processor in Viewlogic XTK model format (formerly known as QUAD format) as the Intel® Pentium® III Processor I/O Buffer Models on Intel’s Developer’s Website (http://developer.intel.com.
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Electrical Specifications Table 13. Valid System Bus, Core Frequency, and Cache Bus Frequencies Processor Core Frequency (MHz) BCLK Frequency (MHz) Frequency Multiplier L2 Cache (MHz) 450 450 100 9/2 225 500 500 100 5 250 533B 533 133 4 267 533EB 533 133 4 533 550 550 100 11/2 275 550E 550 100 11/2 550 600 600 100 6 300 600B 600 133 9/2 300 600E 600 100 6 600 600EB 600 133 9/2 600 650 650 100 13/2 650 667 666.67 133 5 666.
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Electrical Specifications Table 14. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins T# Parameter Notes1, 2, 3 Min Max Unit Figure T7: AGTL+ Output Valid Delay -0.20 -0.14 -0.10 3.15 2.20 2.70 ns ns ns 8 8 8 4, 10, 13 5, 11, 13 5, 11, 12, 14 T8: AGTL+ Input Setup Time 1.90 1.20 1.20 ns ns ns 9 9 9 6, 7, 8, 11, 13 6, 7, 8, 12, 13 6, 7, 8, 11, 12, 14 T9: AGTL+ Input Hold Time 0.85 0.58 0.
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Electrical Specifications . Table 17. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core Pins T# Parameter Min Max Unit Figure T21: PICCLK Frequency 2.0 33.3 MHz T22: PICCLK Period 30.0 500.0 ns 7 Notes 1, 2, 3 T23: PICCLK High Time 12.0 ns 7 T24: PICCLK Low Time 12.0 ns 7 T25: PICCLK Rise Time 0.25 3.0 ns 7 T26: PICCLK Fall Time 0.25 3.0 ns 7 T27: PICD[1:0] Setup Time 8.0 5.0 ns ns 9 9 4, 7 4, 8 T28: PICD[1:0] Hold Time 2.
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Electrical Specifications Table 18. System Bus AC Specifications (TAP Connection) at the Processor Core Pins T# Parameter Min Max Unit Figure Notes T43: All Non-Test Inputs Setup Time 5.0 ns 12 5, 8, 9 T44: All Non-Test Inputs Hold Time 13.0 ns 12 5, 8, 9 1, 2, 3 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies. 2. All AC timings for the TAP signals are referenced to the TCK rising edge at 1.25 V (CPUID=067xh) or 0.
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Electrical Specifications Figure 8. System Bus Valid Delay Timings CLK Tx Tx Valid V Signal Valid Tpw Tx = T7, T29, T29a, T29b (Valid Delay) Tpw = T14, T15 (Pulse Width) V = 1.0V for AGTL+ signal group; 1.25V (CPUID 067xh) or 0.75V (CPUID 068xh) for APIC and TAP signal groups 762 Figure 9. System Bus Setup and Hold Timings CLK Ts Signal V Th Valid Ts = T8, T27 (Setup Time) Th = T9, T28 (Hold Time) V = 1.0V for AGTL+ signal group; 1.25V (CPUID 067xh) or 0.
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Electrical Specifications Figure 11. Power-On Reset and Configuration Timings BCLK Vccp, Vcc, VREF PWRGOOD VIL, max Ta VIH, min Tb RESET# Ta Tb = T15 (PWRGOOD Inactive Pulse) = T10 (RESET# Pulse Width) Figure 12.
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Signal Quality Specifications 3.0 Signal Quality Specifications Signals driven on the Pentium III processor system bus should meet signal quality specifications to ensure that the components read data properly and to ensure that incoming signals do not affect the long term reliability of the component. Specifications are provided for simulation and measurement at the processor core; they should not be tested at the edge fingers.
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Signal Quality Specifications 3.2 AGTL+ and Non-AGTL+ Overshoot/Undershoot Specifications and Measurement Guidelines Overshoot/Undershoot is the absolute value of the maximum voltage differential across the input buffer relative termination voltage (VTT). The overshoot/undershoot guideline limits transitions beyond VTT or VSS due to the fast signal edge rates. The processor can be damaged by repeated overshoot/undershoot events on 1.5 V or 2.5 V tolerant buffers if the charge is large enough (i.e.
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Signal Quality Specifications 3.2.2 Overshoot/Undershoot Pulse Duration Overshoot/Undershoot Pulse duration describes the total time an overshoot/undershoot event exceeds the Overshoot/Undershoot Reference Voltage (VOS_REF = 1.635 V). The total time could encompass several oscillations above the Reference Voltage. Multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total Pulse Duration.
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Signal Quality Specifications 3.2.4 Reading Overshoot/Undershoot Specification Tables The overshoot/undershoot specification for the Pentium III processor is not a simple single value. Instead, many factors are needed to determine what the over/undershoot specification is. In addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot (as measured above 1.635 V) and the Activity Factor (AF).
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Signal Quality Specifications 3.2.5 Determining If a System Meets the Overshoot/Undershoot Specifications The overshoot/undershoot specifications (Table 20 through Table 22) specify the allowable overshoot/undershoot for a single overshoot/undershoot event. However, most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (magnitude, duration, and AF).
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Signal Quality Specifications Table 21. 133 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance Overshoot/Undershoot Magnitude Maximum Pulse Duration Unit Figure 0.19 ns 15 3.7 0.37 ns 15 15 6.8 0.68 ns 15 2.15 V 15 12.5 1.25 ns 15 2.1 V 15 15 2.28 ns 15 2.05 V 15 15 4.1 ns 15 2.0 V 15 15 7.5 ns 15 AF = 0.01 AF = 0.1 AF = 1 2.3 V 15 1.9 2.25 V 15 2.2 V Notes1, 2, 3, 4, 5 NOTES: 1. BCLK period is 7.5 ns. 2.
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Signal Quality Specifications Figure 15. Maximum Acceptable AGTL+ and Non-AGTL+ Overshoot/Undershoot Waveform Time Dependent Overshoot 2.3V 2.2V 2.1V 2.0V 1.635V VTT Converted Undershoot Waveform Max Overshoot Magnitude Undershoot Magnitude Vss Overshoot = Signal - Vss Magnitude Undershoot = VTT - Signal Magnitude 3.3 Time Dependent Undershoot AGTL+ and Non-AGTL+ Ringback Specifications and Measurement Guidelines Ringback refers to the amount of reflection seen after a signal has switched.
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Signal Quality Specifications Table 23. Signal Ringback Specifications for Signal Simulation Transition Maximum Ringback (with Input Diodes Present) Unit Figure 0→1 VREF + 0.200 V 16 AGTL+ 1→0 VREF – 0.200 V 16 Non-AGTL+ Signals 0→1 1.7 V 16 2 Non-AGTL+ Signals 1→0 0.7 V 16 2 PWRGOOD 0→1 2.00 V 16 Input Signal Group AGTL+ Notes1 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies and cache sizes. 2.
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Signal Quality Specifications Figure 16. Low to High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance τ α VREF + 0.2 φ VREF ρ VREF - 0.2 δ 0.7V Clk Ref Vstart Clock Time Note: High to low case is analogous Figure 17. Signal Overshoot/Undershoot, Settling Limit, and Ringback Settling Limit Overshoot V HI Rising-Edge Ringback Falling-Edge Ringback Settling Limit VLO VSS Time Undershoot 000767 3.3.
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Thermal Specifications and Design Considerations 4.0 Thermal Specifications and Design Considerations Limited quantities of Pentium III processors utilize S.E.C.C. package technology. This technology uses an extended thermal plate for heatsink attachment. The extended thermal plate interface is intended to provide accessibility for multiple types of thermal solutions. The majority of SC242based Pentium III processors use S.E.C.C.2 packaging technology. S.E.C.C.
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Thermal Specifications and Design Considerations Figure 19. S.E.C.Cartridge 2 — Substrate View OLGA Package L2 Cache (CPUID 067xh Only Substrate View 4.1 Thermal Specifications Table 25 and Table 26 provide the thermal design power dissipation and maximum and minimum temperatures for Pentium III processors with S.E.C.C. and S.E.C.C.2 package technologies respectively.
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Thermal Specifications and Design Considerations Table 26. Thermal Specifications for S.E.C.C.2 Packaged Processors1 Proc. Core Freq. (MHz) L2 Cache Size (Kbytes) Thermal Design Power 2 (W) L2 Cache Power (W) Power Density4 (W/cm2) Up to CPUID 0683h Power Density4 (W/cm2) For CPUID 0686h6 Max TJUNCTION (°C) TJUNCTION Offset3 (°C) L2 Cache Min TCASE (°C) L2 Cache Max TCASE (°C) Min TCOVER (°C) Max TCOVER (°C) 450 512 25.3 1.26 21.65 n/a 90 4.8 5 105 5 75 500 512 28.0 1.33 23.
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Thermal Specifications and Design Considerations Figure 20. Processor Functional Die Layout (CPUID=0686h) 0.337” 0.275” Die Area = 0.90 cm2 Cache Area = 0.26 cm2 Core Area = 0.64 cm2 0.146” 0.414” Cache Area 0.04 in2 Die Area 0.14 in2 Core Area 0.10 in2 Figure 21. Processor Functional Die Layout (up to CPUID=0683h) 0.362” 0.292” Die Area = 1.05 cm2 Cache Area = 0.32 cm2 Core Area = 0.73 cm2 0.170” 0.448” Cache Area 0.05 in2 Die Area 0.16 in2 Core Area 0.11 in2 For S.E.C.C.
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Thermal Specifications and Design Considerations 4.1.1 Thermal Diode The Pentium III processor incorporates an on-die diode that may be used to monitor the die temperature (junction temperature). A thermal sensor located on the baseboard, or a stand-alone measurement kit, may monitor the die temperature of the Pentium III processor for thermal management or instrumentation purposes. Table 27 and Table 28 provide the diode parameter and interface specifications. Table 27.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications 5.0 S.E.C.C. and S.E.C.C.2 Mechanical Specifications Pentium III processors use either S.E.C.C. or S.E.C.C.2 package technology. Both package types contain the processor core, L2 cache, and other passive components. The cartridges connect to the baseboard through an edge connector. Mechanical specifications for the processor are given in this section. See Section 1.1.1 for a complete terminology listing. 5.1 S.E.C.C. Mechanical Specifications S.E.C.C.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 23. S.E.C.C. Packaged Processor — Extended Thermal Plate Side Dimensions 3.805±.020 (0.750) (1.500) 2.473±.016 2.070±.020 2X .125±.005 1.235±.020 2X .342±.005 These dimensions are from the bottom of the substrate edge fingers 2X .365±.005 1.745±.005 1.877±.020 005 Figure 24. S.E.C.C. Packaged Processor — Bottom View Dimensions 5.255±.006 Cover Thermal Plate 2.181±.015 3.243±.015 5.341±.010 5.505±.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 25. S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate Lug, and Cover Lug Dimensions 2X 0.238 2X0.103 ±0.005 2X 0.103 ± 0.005 2X 0.174 ±0.005 2X 0.647 ±0.020 2X 0.488 ±0.020 2X 0.058 ±0.005 2X 0.253 2X 0.136 ±0.005 Left 2X 0.136 ±0.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 26. S.E.C.C. Packaged Processor — Latch Arm, Extended Thermal Plate, and Cover Detail Dimensions (Reference Dimensions Only) 0.075 0.236 0.122 0.113 0.084 Detail A Detail B (Bottom Side View) 0.120 Min. 0.316 0.116 0.082 0.216 0.291 0.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications 2.110 ±0.008 +0.001 –0.002 6X 0.124 58 0.375 ±0.008 0.000 0.250 ±0.008 0.500 ±0.008 0.978 ±0.008 0.000 Detail A 4X0.365 ±0.005 8XR0.0625 ±0.002 See Detail A Figure 27. S.E.C.C.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 28. S.E.C.C. Packaged Processor — Extended Thermal Plate Attachment Detail Dimensions, Continued 0.0032 / 1.000 x 1.000 1.250 2.500 v008 Figure 29. S.E.C.C. Packaged Processor Substrate — Edge Finger Contact Dimensions Thermal Plate Cover Pin A1 Pin A121 Y Substrate See Detail A in Next Figure 1.85 2.835 W 2.992 ±.008 .045 70° +.007 .062 -.005 Z 2.01 ±.008 5.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 30. S.E.C.C. Packaged Processor Substrate — Edge Finger Contact Dimensions, Detail A .098 .098 Pin A74 Pin A73 .010 .008 .360 .045 .236 .138 ±.005 .039 Y .074 ±.002 W 121 X 0.043 ±.002 .008 ZW .002 Z 121 X 0.16 ±.002 .008 .002 .037 ZW Z NOTE: 1. All dimensions without tolerance information are considered reference dimensions on Figure 31. Intel® Pentium® III Processor Markings (S.E.C.C.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Table 29. Description Table for Processor Markings (S.E.C.C. Packaged Processor) Code Letter 5.2 Description A Logo C Trademark D Logo E Product Name F Dynamic Mark Area – with 2-D matrix S.E.C.C.2 Mechanical Specification S.E.C.C.2 drawings and dimension details are provided in Figure 32 through Figure 44. Figure 32 shows multiple views of the Pentium III processor in an S.E.C.C.2 package; Figure 33 through Figure 37 show an S.E.C.C.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 33. S.E.C.C.2 Packaged Processor Assembly — Primary View L2 Cache (CPUID 067xh Only PLGA CPUID 067xh 0.725 ±0.13 0.954 ±0.13 CPUID 068xh 0.685 ±0.13 0.954 ±0.13 OLGA Figure 34. S.E.C.C.2 Packaged Processor Assembly — Cover View with Dimensions OLGA +.015 CPUID 067xh = .021PLGA -.012 +.015 CPUID 068xh = .017OLGA -.012 4.918 ±0.006 1.849 ±0.010 2.440 ±0.005 0.615 ±0.013 1.546 ±0.013 5.000 ±0.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 35. S.E.C.C.2 Packaged Processor Assembly — Heatsink Attach Boss Section φ 0.112 ±0.001 φ 0.005 φ 0.025 ±0.001 Substrate 0.100 0.062 +0.007 -0.005 0.283 0.020 ±0.010 0.154 5.0° Cover 82.0° Dimensions in inches Figure 36. S.E.C.C.2 Packaged Processor Assembly — Side View OLGA OLGA CPUID 067xh = 0.094" ±0.005" CPUID 068xh = 0.090" ±0.005" Core Package TQFP BS RAM Package (067xh) 0.129 ±0.025 0.061 ±0.005 0.365 ±0.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 38. S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact Dimensions Keep Out Zone (Front Side View) +.007 .062 -.005 .045 Figure 39. S.E.C.C.2 Packaged Processor Substrate — Edge Finger Contact Dimensions (Detail A) Pin A74 Pin A73 .010 .008 .360 .045 .236 .138 ±.005 Y 121 X 0.043 ±.002 .008 ZW .002 Z .039 W .037 .074 ±.002 121 X 0.16 ±.002 .008 .002 ZW Z NOTE: 1.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 40. S.E.C.C.2 Packaged Processor Substrate (CPUID=067xh) — Keep-In Zones NON-KEEPOUT AREA .448 .0275 TYP MAX NON-KEEPOUT AREA .405 Figure 41. S.E.C.C.2 Packaged Processor Substrate (CPUID=068xh) — Keep-In Zones PRIMARY SIDE NON-KEEPOUT AREA ..632 .363 .0275 TYP MAX NON-KEEPOUT AREA 0.448 .
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 42. S.E.C.C.2 Packaged Processor Substrate (CPUID=067xh) — Keep-Out Zone Keep Out Zone (Bottom Side View) Figure 43. S.E.C.C.2 Packaged Processor Substrate (CPUID=068xh) — Keep-Out Zone Keep Out Zone (Front Side View) .362 .363 .440 .
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 44. Intel® Pentium® III Processor Markings (S.E.C.C.2 Package) """" """""""""" " """" " """ " "" " """" """""" """" """"" " " "" """" "" """" """""" """"""""" "" "" "" "" "" "" """"" "" " "" F D NOTE: Please refer to the Pentium® III Processor Specification Update for this information. Table 30. Description Table for Processor Markings (S.E.C.C.2 Packaged Processor) Code Letter 5.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Figure 46. Substrate Deflection toward the Heatsink .160 in. max. deflection 0.050 30 seconds maximum 10 cycles maximum F/2Processor Substrate F/2 F Figure 47. S.E.C.C.2 Packaged Processor Specifications .080 in. max. defle 30 seconds maxim 5 cycles maximum F 2 F Table 31. S.E.C.C.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications 5.4 Processor Package Materials Information Both the S.E.C.C. and S.E.C.C.2 processor packages are comprised of multiple pieces to make the complete assembly. This section provides the weight of each piece and the entire package. Table 32 and Table 33 contain piece-part information of the S.E.C.C. and S.E.C.C.2 processor packages, respectively. Table 32. S.E.C.C. Materials S.E.C.C.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications Table 34.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 34.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 34.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 35. Signal Listing in Order by Signal Name Pin Name Datasheet Pin # Signal Group Table 35.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 35. Signal Listing in Order by Signal Name (Continued) Pin Name 74 Pin # Signal Group Table 35.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 35. Signal Listing in Order by Signal Name (Continued) Pin Name Datasheet Pin # Signal Group Table 35.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications 5.6 Intel® Pentium® III Processor Core Pad to Substrate Via Assignments These test points are the closest locations to the processor core die pad and should be used to validate processor core timings and signal quality on the back of the S.E.C.C. or the S.E.C.C.2 package. See the SECC Disassembly Process Application Note for the instructions on removing the cover of the SECC package. 5.6.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 36. Datasheet Via Listing in Order by Signal Name Table 36.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 36. Via Listing in Order by Signal Name (Continued) 78 Table 36.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 36. Datasheet Via Listing in Order by Signal Name (Continued) Table 36.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 36. Via Listing in Order by Signal Name (Continued) 80 Table 36.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 36. Datasheet Via Listing in Order by Signal Name (Continued) Table 36.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 37. Via Listing in Order by VIA Location 82 Table 37.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 37. Datasheet Via Listing in Order by VIA Location (Continued) Table 37.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 37. Via Listing in Order by VIA Location (Continued) 84 Table 37.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 37. Datasheet Via Listing in Order by VIA Location (Continued) Table 37.
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Intel® Pentium® III Processor for the SC242 at 450 MHz to 1.0 GHz Table 37. Via Listing in Order by VIA Location (Continued) 86 Table 37.
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S.E.C.C. and S.E.C.C.2 Mechanical Specifications 5.6.3 Processor Core Pad Via Assignments (CPUID=068xh) Figure 49 shows the via locations on the back of the processor substrate. Figure 49. Intel® Pentium® III Processor S.E.C.C.
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Boxed Processor Specifications 6.0 Boxed Processor Specifications 6.1 Introduction The Pentium III processor is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and components. Boxed Pentium III processors are supplied with an attached fan heatsink. This section documents baseboard and system requirements for the fan heatsink that will be supplied with the boxed Pentium III processor.
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Boxed Processor Specifications Figure 51. Side View Space Requirements for the Intel® Boxed Processor with S.E.C.C.2 Packaging Figure 52. Front View Space Requirements for the Intel® Boxed Processor with S.E.C.C.
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Boxed Processor Specifications Figure 53. Top View Air Space Requirements for the Intel® Boxed Processor Table 38. Intel® Boxed Processor Fan Heatsink Spatial Dimensions 6.2.2 Fig. Ref. Label Refers to Figure A 51 S.E.C.C.2 Fan Heatsink Depth (off processor substrate) B 51 S.E.C.C.2 Fan Heatsink Height Above Baseboard C 52 S.E.C.C.2 Fan Heatsink Height 2.2 D 52 S.E.C.C.2 Fan Heatsink Width (plastic shroud only) 4.9 E 52 S.E.C.C.
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Boxed Processor Specifications Baseboards designed to accept both Pentium II processors and Pentium III processors have component height restrictions for passive heatsink support designs, as described in AP-588, Mechanical and Assembly Technology for S.E.C. Cartridge Processors (Document Number 243333). 6.3 Fan Heatsink Electrical Requirements 6.3.1 Fan Heatsink Power Supply The boxed processor's fan heatsink requires a +12 V power supply.
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Boxed Processor Specifications Figure 55. Recommended Baseboard Power Header Placement Relative to Fan Power Connector and Intel® Pentium® III Processor 242-Contact Slot Connector Fan power connector location (1.56 inches above motherboard V W X Motherboard fan power header should be positioned within 4.75 inches of the fan power connector (lateral distance). Table 40. Baseboard Fan Power Connector Location Fig. Ref. Labels 6.
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Intel® Pentium® III Processor Signal Description 7.0 Intel® Pentium® III Processor Signal Description This section provides an alphabetical listing of all Pentium III processor signals. The tables at the end of this section summarize the signals by direction: output, input, and I/O. 7.1 Alphabetical Signals Reference Table 41. Signal Description (Sheet 1 of 7) Name A[35:3]# Type I/O Description The A[35:3]# (Address) signals define a 236-byte physical memory address space.
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Intel® Pentium® III Processor Signal Description Table 41. Signal Description (Sheet 2 of 7) Name Type Description The BERR# (Bus Error) signal is asserted to indicate an unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents, and must connect the appropriate pins of all such agents, if used. However, Pentium III processors do not observe assertions of the BERR# signal. BERR# I/O BERR# assertion conditions are configurable at a system level.
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Intel® Pentium® III Processor Signal Description Table 41. Signal Description (Sheet 3 of 7) Name Type Description The BR0# and BR1# (Bus Request) pins drive the BREQ[1:0]# signals in the system. The BREQ[1:0]# signals are interconnected in a rotating manner to individual processor pins. The table below gives the rotating interconnect between the processor and bus signals.
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Intel® Pentium® III Processor Signal Description Table 41. Signal Description (Sheet 4 of 7) Name Type Description EMI I EMI pins should be connected to baseboard ground and/or to chassis ground through zero ohm (0 Ω) resistors. The 0 Ω resistors should be placed in close proximity to the processor connector. The path to chassis ground should be short in length and have a low impedance. These pins are used for EMI management purposes.
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Intel® Pentium® III Processor Signal Description Table 41. Signal Description (Sheet 5 of 7) Name Type Description The LOCK# signal indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of all processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction end of the last transaction.
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Intel® Pentium® III Processor Signal Description Table 41. Signal Description (Sheet 6 of 7) Name Type Description Asserting the RESET# signal resets all processors to known states and invalidates their L1 and L2 caches without writing back any of their contents. For a Power-on or “warm” reset, RESET# must stay active for at least one millisecond after VccCORE and CLK have reached their proper specifications.
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Intel® Pentium® III Processor Signal Description Table 41. Signal Description (Sheet 7 of 7) Name Description I The SMI# (System Management Interrupt) signal is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
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Intel® Pentium® III Processor Signal Description 7.2 Signal Summaries Table 42 through Table 45 list attributes of the processor output, input, and I/O signals. Table 42. Output Signals Name Active Level Clock Signal Group FERR# Low Asynch CMOS Output IERR# Low Asynch CMOS Output PRDY# Low BCLK AGTL+ Output SLOTOCC# Low Asynch Power/Other TDO High TCK TAP Output THERMTRIP# Low Asynch CMOS Output VID[4:0] High Asynch Power/Other Table 43.
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Intel® Pentium® III Processor Signal Description Table 44.