dNode Integration Specification On-Ramp Wireless Confidential and Proprietary. This document is not to be used, disclosed, or distributed to anyone without express written consent from On-Ramp Wireless. The recipient of this document shall respect the security of this document and maintain the confidentiality of the information it contains. The master copy of this document is stored in electronic format, therefore any hard or soft copy used for distribution purposes must be considered as uncontrolled.
On-Ramp Wireless Incorporated 10920 Via Frontera, Suite 200 San Diego, CA 92127 U.S.A. Copyright © 2012 On-Ramp Wireless Incorporated. All Rights Reserved. The information disclosed in this document is proprietary to On-Ramp Wireless Inc., and is not to be used or disclosed to unauthorized persons without the written consent of On-Ramp Wireless. The recipient of this document shall respect the security of this document and maintain the confidentiality of the information it contains.
Contents 1 Overview ................................................................................................................ 1 1.1 ULP Wireless Network ............................................................................................................... 1 1.2 dNode ......................................................................................................................................... 2 1.3 Referenced Documents ..............................................................
dNode Integration Specification Contents 5.1.1 Power Off State .............................................................................................................. 20 5.1.2 Deep Sleep State ........................................................................................................... 21 5.1.3 Oscillator Calibration State ............................................................................................. 21 5.1.4 Idle State ..................................................
dNode Integration Specification Contents 11 Errata ................................................................................................................. 44 Appendix A Abbreviations and Terms ................................................................. 45 Appendix B dNode Mechanical Drawing ............................................................. 47 On-Ramp Wireless Confidential and Proprietary v 014-0038-00 Rev.
dNode Integration Specification Contents Figures Figure 1. On-Ramp Wireless ULP Network ..................................................................................... 1 Figure 2. dNode (Top and Bottom Views)........................................................................................ 2 Figure 3. Typical Application Diagram ............................................................................................. 2 Figure 4.
dNode Integration Specification Contents Tables Table 1. Absolute Maximum Ratings ............................................................................................... 4 Table 2. Operating Conditions ......................................................................................................... 4 Table 3. Operating Characteristics .................................................................................................. 4 Table 4. dNode J701 Pin Descriptions...................
Revision History Revision Release Date Change Description A May 24, 2012 Initial release. B July 11, 2012 Updated the Maximum RF Conducted Power and clarified antenna configuration and defaults. On-Ramp Wireless Confidential and Proprietary viii 014-0038-00 Rev.
1 Overview This document provides a brief overview of the Ultra-Link Processing™ (ULP) wireless network as well as guidelines allowing an integrator to design a Host product that utilizes the dNode and ensures that the system meets all of its technical objectives and requirements to enable remote wireless communication. 1.1 ULP Wireless Network The On-Ramp Wireless ULP network is comprised of dNodes and Access Points (AP) and operates in the unlicensed 2.4 ISM band at a receive-sensitivity of -142 dBm.
dNode Integration Specification Overview 1.2 dNode The ULP dNode is a third generation, small form factor wireless network module that easily integrates with various devices and sensors using an industry standard Serial Peripheral Interface (SPI). Most of the top side of the printed circuit board (PCB) is enclosed with a radio frequency (RF) shield except for the two RF connectors. The RF connectors are MMCX (Jack) receptacles. The PCB bottom side consists of two single-row, 0.1 in pitch (2.
dNode Integration Specification Overview 1.3 Referenced Documents The following documents are referenced and provide more detail. n ULP Node Interface Library (UNIL) (010-0066-00) Provides information about the library of portable C code provided by On-Ramp Wireless which can be integrated into a customer’s existing software architecture. n UNIL API (010-0072-00) Provides details relating to the UNIL Application Programming Interface.
2 DC and AC Characteristics 2.1 Absolute Maximum Ratings Operating outside of these ranges may damage the unit. Table 1. Absolute Maximum Ratings Parameter Min Max Unit Storage Temperature -40 85 ⁰C Operating Temperature -40 85 ⁰C Input Voltage 2.5 5.5 V 2.2 Recommended Operating Conditions Table 2. Operating Conditions Parameter Min Max Unit Input voltage, VBATT 2.5 5.
dNode Integration Specification DC and AC Characteristics Description Min Typ Ramp Temperature (maximum rate at which operating temperature should change) Max Units 30 °C/Hr. Receiver Receiver Sensitivity – Note 3 -130 -133 -135 dBm Receiver Image Reject 38 45 50 dB Noise Figure 3.5 5.0 6.
dNode Integration Specification 5. 6. 7. 8. 9. 10. DC and AC Characteristics c. Japan: CH41; 2481.60 MHz. Maximum TX RF power is limited by FCC/IC grant to 20.9 dBm in these markets. Spec and test method comes from FCC 15.247(d); Band Edge Emissions, 2 MHz offset. At any TX power level, VSWR ≤ 3:1. Harmonics fall into FCC restricted bands. Estimated sum of all contributors with VSWR ≤ 1.5:1. Normal link mode. At any TX power level, VSWR ≤ 3:1. Applies to spurious, not ACPR or harmonics.
dNode Integration Specification DC and AC Characteristics Figure 4. dNode Deep Sleep Power Consumption (mW Power vs Voltage Input) Figure 5. RX State Power Consumption (mW Power vs VBATT Input) On-Ramp Wireless Confidential and Proprietary 7 014-0038-00 Rev.
dNode Integration Specification DC and AC Characteristics Figure 6. TX Power Consumption at 20.9 dBm (mW Power vs VBATT Input) On-Ramp Wireless Confidential and Proprietary 8 014-0038-00 Rev.
3 Electrical Interface This chapter describes the electrical interface of the dNode and how the Host processor controls the dNode. 3.1 Signal Connectors n The PCB bottom side consists of two single-row 0.1 inch pitch (2.54 mm) headers, J701 and J703. All user interfaces to the dNode, with the exception of RF, are through these two connectors. n The header mating contacts are 0.228 inch (5.8 mm). n J701, 1x10 SIP headers, 2.54 mm pitch, 5.8 mm long n J703, 1x10 SIP headers, 2.54 mm pitch, 5.
dNode Integration Specification J701 Pin # Electrical Interface Pin Name Signal Direction Relative to dNode Signal Type Polarity Comment 3 T_OUT Output CMOS_O Active High Time Sync Pulse 4 RESET Input CMOS_I Active Low dNode Reset 5 SPI_CS Input CMOS_I Active Low SPI Chip Select 6 SPI_SCLK Input CMOS_I 7 SPI_MOSI Input CMOS_I Active High Master Out Slave In 8 SPI_MISO Output CMOS_O Active High Master In Slave Out 9 GND Ground Power 10 GND Ground Power Polari
dNode Integration Specification Electrical Interface 3.3 Signal Descriptions 3.3.1 VBATT This is the main power to the dNode. This needs a low impedance source to the Host’s power source. It is recommended that the Host have provision for up to a 100 µF low ESR capacitor. It is likely this capacitor is not required if low impedance design rules are followed. 3.3.2 RESET_N The RESET_N pin serves a dual purpose.
dNode Integration Specification Electrical Interface 3.3.7 SPI System The SPI system is the generic term used for all SPI signals (MOSI, MISO, CS, SCLK) to be set up for SPI communications to occur between Host and dNode. The dNode SPI is the Slave in the Master/Slave communications and is defined in section 4.2: SPI Mode and Timing. 3.3.8 RF The dNode supports two MMCX ports. These two ports are required for antenna diversity. Each port is a nominal 50 Ohms.
4 SPI Interface and Sequences 4.1 SPI System Interface Overview The SPI slave interface is currently the only supported interface for Host-to-Node communication. NOTE: The dNode must be the only SPI slave on the bus. The SPI slave interface provides communication with an external Host through a 7-wire interface. The Host is the SPI master and the dNode is the SPI slave. In addition to the four standard SPI signals, three additional signals are used to complement the SPI bus: MRQ, SRQ, and SRDY.
dNode Integration Specification SPI Interface and Sequences 4.2 SPI Mode and Timing SPCK Cycle (for reference) 1 2 3 4 5 6 7 8 SPCK (CPOL = 0) MOSI (from master) MISO (from slave) MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) Figure 8. SPI Timing, CPOL = 0, CPHA = 0 4.3 Startup (Power On) Sequence During, and immediately after Power On Reset (POR), the Host has no control of its I/O power states.
dNode Integration Specification SPI Interface and Sequences VBATT Hi-Z Reset_N MRQ Hi-Z SPI Bus (Driven as appropriate) SRDY 10 ms t0 t1 4 ms < 5 sec t3 t2 t4 Figure 9. dNode Host-driven Initial Power-up Sequence The timing sequence shown in the figure above is described below. NOTE: The timing shown in the figure is not to scale. n t0 This transition shows the power-up and possible random states of Host I/O, before the Host is able to properly configure its pins.
dNode Integration Specification n SPI Interface and Sequences The dNode can “self-awaken” due to network events. In this case, a timer internal to the dNode “pops” and triggers the dNode to “Wake.” When the dNode is awake it asserts its SRDY as a matter of course to indicate to the Host (if it needs to) that it can start communicating with the dNode while it is awake. This is an Asynchronous Wake Sequence. 4.4.
dNode Integration Specification SPI Interface and Sequences 4.4.2 Wake Sequence (Asynchronous) In this scenario, the dNode is already awake due to a networking event (SRDY is already High) and the Host wants to communicate with the dNode while it is awake. The Host asserts MRQ to ensure that the dNode stays awake during its communication cycle. NOTE: The timing shown in the figure is not to scale. MRQ SPI Bus Hi-Z (Driven as appropriate) SRDY < 250 μs t0 >0 t1 t2 t3 Figure 11.
dNode Integration Specification SPI Interface and Sequences 4.5 Host-Driven Reset Sequence If the dNode fails to communicate (or similar), it may be necessary to Reset the dNode. The following figure shows the proper sequence to reset the device. NOTE: Resetting the device causes it to go through a Cold Acquisition process to reacquire the network. VBATT Hi-Z Hi-Z Reset_N MRQ (Driven as appropriate) Hi-Z SPI Bus SRDY 10 ms t0 4 ms < 5 sec t1 t2 t3 Figure 12.
dNode Integration Specification SPI Interface and Sequences 4.6 Host MRQ Release/dNode Allowed to Sleep Sequence If the Host determines there are no more messages or SPI transactions required, it should disable the interface to allow the dNode to fall back to Deep Sleep (lowest power mode). As the figure below indicates, the SPI bus must be disabled (tri-stated) before MRQ is de-asserted. These operations can be performed back to back. NOTE: The timing shown in the figure is not to scale.
5 Power States The dNode has a number of states it runs through during its various operating modes. General comments: 1. The dNode accepts a wide input voltage range (2.5-5.5V). 2. The dNode has low drop out (LDO) regulators that will operate 100% of the time the dNode is powered (RESET_N signal set high or left floating by the Host). 3. There are 3.3V/1.2V Buck/Boost Switching regulators that use the wide input range to drive key RF and Digital circuits. The 3.
dNode Integration Specification Power States 5.1.2 Deep Sleep State The dNode shuts off all its power regulators except a couple low quiescent LDO regulators. These regulators keep a minimal amount of circuitry alive for tracking network timers, enable a 32 kHz clock, and some minor interface circuitry. 5.1.3 Oscillator Calibration State When the dNode is in Deep Sleep state, it attempts to maintain accuracy of its low power 32 kHz clock to enable faster network synchronizing when it wakes up.
dNode Integration Specification Power States 5.1.4 Idle State Idle state has various sub-states but generally refers to a state where the dNode is “awake” and its system clock is on, the CPU is awake, but the RF is OFF. 5.1.5 RX State The dNode turns on all its clocks, the main CPU and the RF in an RX-only state. The RF transceiver, in RX state, consumes a moderate amount of power. 5.1.6 TX State When the dNode transmits, it uses a variable transmit power that is correlated to its received RSSI.
dNode Integration Specification Power States Figure 15. Representative Current Consumption During Deep Sleep, Idle, RX, and TX; x16 Spreading Factor (Amps vs Seconds) The plot shown in the figure above represents the nominal transitions for the dNode from Deep Sleep, Idle, Receive, and Transmit states. In this case, a TX spreading factor of 16 is used.
6 Messaging Protocol The details of Host/Node messaging are typically not necessary for integrators to implement, given the functional interface provided by the ULP Node Interface Library (UNIL) (010-0066-00) and UNIL API (010-0072-00). However, low-level understanding of the SPI protocol used may be critical in resolving Host interface issues. For mid-level details of the messages that may be sent over this interface, refer to ULP Node Host Message Specification (014-0020-00). 6.
dNode Integration Specification Messaging Protocol size. If the message payload size exceeds the receive buffer size, then a new request must be made after a turn-around delay with a payload size that does not exceed the receive buffer size. After a successful message request transfer, the Host waits a turn-around delay and then initiates the transfer with a message header command.
dNode Integration Specification Messaging Protocol Node Host Slave Request MRQ=1 Arbitration Slave Ready SRDY=1 Arbitration Acknowledge ArbREQ ArbACK Validation Acknowledge ValREQ ValACK wait Arbitration Request wait Validation Request MRQ=1 SRDY=1 wait Host-to- Node Message Transfer MMsgREQ+Size MMsgACK+Size Master Message Acknowledge Master Message Request wait Master Header Acknowledge MHdrREQ MHdrACK Payload Receive PAYLOAD Master Header Request Payload Transmit wait Repeat 5 step
dNode Integration Specification Messaging Protocol bubbles indicate a predefined turn-around delay which provides ISR processing time and avoids race conditions between Host and Node. 6.3 Host Interface SPI Bus State Machine This section illustrates the sequence of messages that can take place on the Host interface SPI bus. The design and implementation of the actual state machine on the Host software is up to the Host software designer.
dNode Integration Specification Messaging Protocol 6.4 SPI Bus Timing Example This section provides an example illustration of an exchange of messages first from master (Host) to slave (Node) and then from slave (Node) to master (Host). Each step in the timing sequence is described below: 9 SRQ MRQ SRDY 6 5 10 1 11 2 CS SCLK MISO MOSI 3 4 7 8 Figure 18. SPI Timing Example Note that MRQ state transitions must respect the timing requirements shown in chapter 4.
dNode Integration Specification Messaging Protocol 6. At some time in the future, the Node desires to send a message to the Host. It indicates this to the Host by driving SRQ high. Since SRQ is high, the Host drives MRQ and then CS high. It then waits for SRDY to go high, which it already is. 7. The Host starts the SPI data transaction.
dNode Integration Specification Messaging Protocol MOSI) are read on the SCLK rising edge and are set or cleared on the SCLK falling edge, and is commonly referred to as CPOL=0, CPHA=0.
dNode Integration Specification Messaging Protocol opcode=MHdrACK (1010) Hard coded byte=1 (00000001) Unused Extra Data (0000…...0) MOSI: from master to slave (10) length of message=2 (10) opcode =MhdrREQ (1010) Hard coded byte=1 (00000001) Payload: length=8 (0000100000000000) message type=VERSION (0001010101000000) trailing sequence (11110000111100001010010110100101) The payload is Little Endian. The least significant byte is transmitted over SPI first.
dNode Integration Specification Messaging Protocol opcode =MmsgREQ (1001) payload size=6 (00000110) The MMsg exchange is followed by the MHdr exchange, which includes the payload of the CONNECT message.
dNode Integration Specification Messaging Protocol These bits indicate: MISO: from slave to master (01) length of message=2 (10) opcode=SMsgACK (1011) buffer size=255 (11111111) payload size=4 (00000100) MOSI: from master to slave (10) length of message=2 (10) opcode =SmsgREQ (1011) buffer size=255 (11111111) The SMsg exchange is followed by the SHdr exchange, which includes the payload of the ACK message.
7 dNode Configuration Node Provisioning Tools (NPT) are used for Node provisioning. Complete provisioning of Nodes involves three distinct utilities: 1. Node Software Upgrade Utility (sw_upgrade.py) This utility is used for upgrading the Node firmware. 2. Node Flash Configuration Utility (config_node.py) This utility is used for programming Node flash configuration parameters. 3. Node Key Provisioning Utility (provision_node_keys.
8 Antenna Diversity The dNode supports Antenna Diversity for optimal System performance. In many cases, the dNode and Host system are mounted in fixed locations that often experience nulls in the RF spectrum. Antenna Diversity can help with optimization of the RX and TX paths. In marginal coverage areas, an RF null could easily disadvantage the dNode to enforce it to transmit at a higher TX Power (more current) or causes network loss and frequent rescanning to reacquire the network (again, more current).
9 Regulatory Considerations The dNode uses two MMCX connectors for its RF ports. On-Ramp Wireless provides FCC/IC modular approval certification as well as ETSI certification for the dNode. The dNode was certified on an On-Ramp Wireless application platform known as the eHost. These documents and results are available to System Integrators to ensure that the product can be certified.
dNode Integration Specification Regulatory Considerations 9.2 Certifications The dNode is designed to meet regulations for world-wide use. It is has modular approval certification in the United States and Canada, and ETSI certification in Europe. The certifications currently achieved are listed in the following table. Table 8.
dNode Integration Specification NOTE: Regulatory Considerations This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. WARNING: This equipment generates, uses, and can radiate radio frequency energy.
dNode Integration Specification Regulatory Considerations 9.5 ETSI Warnings None known. 9.6 Usage FCC ID: XTE-ULPD100. IC: 8655A-ULPD100. This device is only authorized for use in fixed and mobile applications. To meet FCC and other national radio frequency (RF) exposure requirements, the antenna for this device must be installed to ensure a separation distance of at least 20cm (8 inches) from the antenna to a person. 9.6.
dNode Integration Specification Regulatory Considerations program cost and schedule, the ability to reuse this antenna is highly dependent on the application. n Customers can recertify the final product with any antenna type and gain desired. In the case of FCC/IC EMC certifications, it is almost always required for the final product to be recertified with the dNode. If this is the case, note that the recertification is the required time to introduce the final product’s actual antenna.
10 Design Considerations for the Host The dNode has two 10-pin Single Inline Package (SIP) headers that allow for two Host mounting methods: Socketed and Direct Solder. 10.1 Host Mounting Method: Socketed The Socketed Host mounting method is preferred since it permits easy insertion, removal, and network provisioning of the dNode on a separate Host. It is important to follow some layout constraints and the recommended design guidelines of the socket manufacturer.
dNode Integration Specification Design Considerations for the Host 10.1.2 Pad Stack for Mill-Max Series 834 Paste In Hole (PIH) soldering technique allows for installation of the Mill-Max 834 series connectors during the SMD reflow process. As shown below, the component side pad is a large rounded rectangular (100x60 mils) and all other pads are 60 mil round pads, with all pads using a plated drill hole of 46 mils. Figure 23.
dNode Integration Specification Design Considerations for the Host 10.2 Host Mounting Method: Direct Solder The Direct Solder method of mounting the dNode gives little flexibility in insertion/removal but is the least expensive and can provide Low resistance on the Vbatt/Ground paths. PCB layout considerations are provided below. Optional square pads to indicate Pin 1 of connectors. Same drill diameter. .844 [21.44] (TYP) Optional Stencil Marks .040 [1.02] DIA (TYP) x20 .100 [2.
11 Errata Degraded RF Channels The dNode uses a Channel scheme such as the following: n n n n Channel 1 = 2402 MHz and each successive channel is 1.99 MHz offset to that Channel 1. Channel 2 = 2403.99 MHz Channel 3 = 2405.98 MHz Etc. The dNode uses a 26 MHz reference clock for processing and for the direct conversion radio. It has been found that 26 MHz harmonics can create strong tones that cause some RF sensitivity degradation on these harmonic channels. n n n 93*26 MHz = 2418 MHz.
Appendix A Abbreviations and Terms Abbreviation/Term Definition AGC Automatic Gain Control ALC Automatic Level Control AP Access Point (this product) API Application Programming Interface ASIC Application-Specific Integrated Circuit BOM Bill of Materials BW Bandwidth CMOS Complementary Metal-Oxide-Semiconductor CPOL Clock Polarity (for SPI) CPU Central Processing Unit DFS Dynamic Frequency Selection dNode Third generation of the ULP wireless module that integrates with OEM sensors a
dNode Integration Specification Abbreviations and Terms Abbreviation/Term Definition OTA Over-the-Air PA Power Amplifier PAPR Peak-to-Average Power Ratio PCB Printed Circuit Board POR Power On Reset QoS Quality of Service RF Radio Frequency RFIC Radio Frequency Integrated Circuit RoHS Restriction of Hazardous Substances RSSI Receive Signal Strength Indicator RT Remote Terminal RTC Real Time Clock RX Receive/Receiver SCLK Serial Clock SMT Surface Mount Technology SNR Signal
Appendix B dNode Mechanical Drawing Figure 25. dNode Mechanical Dimensions On-Ramp Wireless Confidential and Proprietary 47 014-0038-00 Rev.