8 J1 7 6 5 4 REFERENCE: 32350759-001 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 NEXT ASSY: 32350760-001 INITIAL APPLICATION 3 A NCNCNCNCNCNC DRAWN BY Tony.Gao DESIGNER Tony.
7 8 5 6 4 3 2 1 CAD MAINTAINED.
8 5 6 7 4 3 2 1 +3V3 RT1 L6 TP60 USB2SDIO_POWER BLM21PG221SN1D 2A THMS_PTC_FUSE__0.6W 50050360-001 600mW 1206L020YR D USB2SDIO_POWER Note: C1 D1 0.1uF ESD5Z3.3T1G 16V 3.
8 5 6 7 U1 NCP380HMUAJAATBG C19 0.
8 5 6 7 4 3 2 1 D D C35 C2 1uF 0.1uF 10% 10% CAP__C1608X7R1C105K 16V 16V +3V3 L2 BLM21PG221SN1D 2A C23 10uF 10% 10V C16 0.1uF 10% 16V C17 0.1uF 10% 16V U8 USB2642-I/ML C18 0.1uF 10% 16V +3V3 +3V3 +3V3 +3V3 C22 10uF 10% 10V C Note: C4 0.1uF 10% 16V C12 0.1uF 10% 16V C13 0.1uF 10% 16V C14 0.1uF 10% 16V C15 0.1uF 10% 16V C36 C3 0.
8 5 6 7 4 3 2 1 U11 WM-BAC-BM-25 WiFi_3V3 WiFi_3V3 WLAN MDL WiFi_3V3 24 25 GPIO4_11 D GPIO4_11 WiFi Reg ON. Internal Pull-down.
D 7 6 5 4 NOTES: 3 2 1 D SHEET FUNCTION DESCRIPTION SHEET UNLESS OTHERWISE SPECIFIED: 1. THIS DRAWING IS CAD GENERATED AND MAINTAINED. CHANGES SHALL BE INCORPORATED BY THE CURRENT DESIGN ACTIVITY. 2. PARTIAL REFERENCE DESIGNATIONS ARE SHOWN: FOR COMPLETE DESIGNATION PREFIX WITH UNIT NUMBER, ASSEMBLY DESIGNATIONS AND SUBASSEMBLY DESIGNATIONS PLEASE SEE BOM.
8 7 6 5 4 3 2 1 BLOCK DIAGRAM D D C C B B A A DRAWN BY M Back Number SOM Board 23Jun2017 HONEYWELL CONFIDENTIAL AND PROPRIETARY HONEYWELL INTERNATIONAL INC. HOME & BUILDING TECHNOLOGIES SIZE D DRAWING NO.
8 SODIMM_CONNECTOR 5 6 7 POWER VIN VIN VIN 4 3 2 1 PROCESSOR VDD_ARM VDD_ARM DDR3L_256K_X16_1 VDD_ARM MMDC VDD_SNVS D VDD_SNVS MMDC VDD_SNVS DDR_ADDR[0:14] V33 DDR Byte lanes swapped to optimise layout V33 DDR_SDBA[0:2] V33 DDR_CTRL DDR_ADDR[0:14] D DDR_SDBA[0:2] DDR_CTRL Byte Order 0 2 1 0 LDO1 LDO3 LDO4 VDD_ENET VDD_1P8 DDR_DATA[16:23] VDD_EMMC DDR_DATA[0:7] DDR_DQM0 POR_B INT_B PWR_OFF_B PWR_OFF_B PWR_OFF_B I2C_1 POR_B INT_B POR_B DDR_SDQS0_N INT_B DDR_SDQS0
8 5 6 7 4 3 2 1 Q1 FDMA908PZ 1 2 5 6 D D TP10 TP46 TP47 R49 VIN TP11 D 7 TP48 4 8 220m 1% 250mW G 3 S TP53 V33 V33 TP49 TP63 VIN_2 LDO1 C87 22uF 20% 10V U7 INA219AIDCNR C85 22uF 20% 10V C86 22uF 20% 10V TP61 LDO3 +3.3V TP62 VDD_1P8 CUR/PWR MON 2 1 7 8 -IN +IN GND +3.3V 4 3 A0 A1 5 6 C VS LDO4 C74 0.1uF 10% 16V C73 0.1uF 10% 16V SCL SDA C99 4.7uF 10% 25V C115 1uF 10% 25V C102 4.7uF 10% 25V C100 4.7uF 10% 25V C101 4.
8 5 6 7 4 TP4 NC TP3 Boot Mode D TP2 00 - Boot from Fuses only 01 - Serial downloader on USB1_OTG 10 - Internal boot - use BOOT_CFG pins Production designs should have all Boot Mode resistors deleted and boot based on fuse settings.
8 5 6 7 4 3 2 1 MMDC MMDC U1 MCIMX6X2CVN08AC 2 OF 5 R35 MIPRCS K1 D L1 P1 P2 G1 H2 W2 W1 B1 B2 T2 T1 R2 M1 L2 N1 H1 K2 J2 J1 F1 E2 E1 W4 Y4 W3 Y2 U1 V2 W6 DRAM_ADDR11 DRAM_DATA01 DRAM_ADDR12 DRAM_DATA02 DRAM_ADDR13 DRAM_DATA03 DRAM_ADDR14 DRAM_DATA05 DRAM_SDBA0 DRAM_DATA06 DRAM_SDBA1 DRAM_DATA07 DRAM_SDBA2 DRAM_DATA09 DRAM_RESET DRAM_DATA10 DRAM_RAS_B DRAM_DATA11 DRAM_CAS_B DRAM_DATA12 DRAM_CS0_B DRAM_DATA13 DRAM_CS1_B DRAM_DATA14 DRAM_SDWE_B DRAM_DATA16 DRAM_SDCKE0
8 5 6 7 4 3 2 1 U1 MCIMX6X2CVN08AC ENET1 SDIO_2 SDIO_2 ENET1 ENET1 3 OF 5 MIPRCS C10 E9 D8 C9 D D7 E8 E10 C11 Boot configuration for development only. Production boot configuration should be programmed into internal fusebox. Production designs may have all of these resistors below deleted. D11 ENET2 C12 ENET2 E11 ENET2 D10 B9 Boot configuration set for eMMC device on USDHC4 with normal boot. Fast boot can be set once normal boot is operating properly.
8 5 6 7 4 3 2 1 VDD_SNVS VDD_SNVS VDD_SNVS D TP30 D NVCC_PLL_CAP VDD_ARM VDD_ARM C23 0.22uF 10% 16V V33 V33 C98 4.7uF 10% 25V +3.3V V33 TP26 22uF cap on C16 VDD_ARM_CAP C27 0.22uF 10% 16V C28 0.22uF 10% 16V U1 MCIMX6X2CVN08AC C29 0.22uF 10% 16V 4 OF 5 MIPRCS W20 VDD_EMMC R11 VDD_EMMC H15 VDD_EMMC F6 F15 C30 0.22uF 10% 16V C G15 F13 V10 R6 VDD_ENET F14 VDD_ENET F8 VDD_ENET F9 C32 0.22uF 10% 16V C26 0.22uF 10% 16V R12 R11 TP24 V13 V5 10K 1% 63mW +1.
8 7 DDR_ADDR[0:14] 5 6 4 3 2 1 U4 MT41K256M16TW-107_IT DDR_ADDR[0:14] +1.35V DRAM 32MX16 8 BANKS N3 P7 P3 N2 D P8 P2 R8 R2 T8 R3 L7 R7 DDR_SDBA[0:2] N7 DDR_SDBA[0:2] T3 T7 M2 DDR_CTRL N8 DDR_CTRL M3 K1 J3 K3 L2 T2 K9 C J7 D3 L3 D9 A1 DDR_DQM0 DDR_DQM1 J1 J9 L1 L9 M7 M8 DDR_VREF_CA H1 DDR_VREF_DQ Route DDR_VREF_CA and DDR_VREF_DQ separately from where they are generated. Trace width of at least 0.025in and kept away from other noisy signals. C58 0.1uF 10% 16V C33 0.
8 7 DDR_ADDR[0:14] 5 6 4 3 2 1 U5 MT41K256M16TW-107_IT DDR_ADDR[0:14] +1.35V DRAM 32MX16 8 BANKS N3 P7 P3 N2 D P8 P2 R8 R2 T8 R3 L7 R7 DDR_SDBA[0:2] N7 DDR_SDBA[0:2] T3 T7 M2 DDR_CTRL N8 DDR_CTRL M3 K1 J3 K3 L2 T2 K9 C J7 D3 L3 D9 A1 DDR_DQM0 DDR_DQM1 J1 J9 L1 L9 M7 M8 DDR_VREF_CA H1 DDR_VREF_DQ Route DDR_VREF_CA and DDR_VREF_DQ separately from where they are generated. Trace width of at least 0.025in and kept away from other noisy signals. C69 0.1uF 10% 16V C37 0.
8 5 6 7 4 3 2 1 VDD_IO VDD_IO D D +3.3V TP65 EMMC_VDDM_CAP R12 10K 1% 63mW R13 10K 1% 63mW C79 0.1uF 10% 16V U8 MTFC4GACAJCN-1M_WT C116 1uF 10% 25V C103 4.7uF 10% 25V 1 OF 2 U8 MTFC4GACAJCN-1M_WT C43 0.22uF 10% 16V 2 OF 2 FLASH 4GX8 C2 K5 RST_B M5 CMD TP73 R45 M6 CLK TP74 33.
8 5 6 7 4 D2 VIN D1 BAS16 T/R VIN P1 DFLS160-7 60V DEV P3 105017-0001 1 IO 2 IO 3 IO 4 IO 5 IO DDR3 SODIMM EDGE CONNECTOR 1 3 D 5 7 IO IO IO IO IO IO IO IO 2 4 6 8 DEV 3 2 USB1_OTG USB1_OTG 85V R39 TP35 GPIO GPIO D 0 DEV R40 TP36 P1 NC DDR3 SODIMM EDGE CONNECTOR 0 73 DEV +3.3V 9 11 13 LDO1 15 LDO1 IO IO IO IO IO IO IO IO +3.
8 5 6 7 123 SDIO_3 SDIO_3 IO 4 IO 3 2 124 USB1_OTG R44 125 IO IO 1 126 USB1_OTG USB1_D_N USB1_OTG 33.2 127 129 131 D IO IO IO IO IO IO 128 USB1_D_P 130 132 USB1_VBUS USB2_HST 133 IO IO 134 USB2_HST D USB2_VBUS USB2_PWR 135 IO IO 136 USB2_OC_B 137 139 141 SDIO_2 SDIO_2 IO IO IO IO IO 138 USB2_D_N 140 USB2_D_P 33.
8 7 DDR_ADDR[0:14] 5 6 4 3 2 1 U? MT41K256M16TW-107_IT DDR_ADDR[0:14] +1.35V DRAM 32MX16 8 BANKS N3 P7 P3 N2 D P8 P2 R8 R2 T8 R3 L7 R7 DDR_SDBA[0:2] N7 DDR_SDBA[0:2] T3 T7 M2 DDR_CTRL N8 DDR_CTRL M3 K1 J3 K3 L2 T2 K9 C J7 D3 L3 D9 A1 DDR_DQM0 DDR_DQM1 J1 J9 L1 L9 M7 M8 DDR_VREF_CA H1 DDR_VREF_DQ Route DDR_VREF_CA and DDR_VREF_DQ separately from where they are generated. Trace width of at least 0.025in and kept away from other noisy signals. C? 0.1uF 10% 16V C? 0.
8 5 6 7 4 TP? NC TP? Boot Mode D 00 - Boot from Fuses only 01 - Serial downloader on USB1_OTG 10 - Internal boot - use BOOT_CFG pins TP? Production designs should have all Boot Mode resistors deleted and boot based on fuse settings.
8 5 6 7 4 3 2 1 MMDC MMDC U? MCIMX6X2CVN08AC 2 OF 5 R? MIPRCS K1 D L1 P1 P2 G1 H2 W2 W1 B1 B2 T2 T1 R2 M1 L2 N1 H1 K2 J2 J1 F1 E2 E1 W4 Y4 W3 Y2 U1 V2 W6 DRAM_ADDR11 DRAM_DATA01 DRAM_ADDR12 DRAM_DATA02 DRAM_ADDR13 DRAM_DATA03 DRAM_ADDR14 DRAM_DATA05 DRAM_SDBA0 DRAM_DATA06 DRAM_SDBA1 DRAM_DATA07 DRAM_SDBA2 DRAM_DATA09 DRAM_RESET DRAM_DATA10 DRAM_RAS_B DRAM_DATA11 DRAM_CAS_B DRAM_DATA12 DRAM_CS0_B DRAM_DATA13 DRAM_CS1_B DRAM_DATA14 DRAM_SDWE_B DRAM_DATA16 DRAM_SDCKE0
8 5 6 7 4 3 2 1 U? MCIMX6X2CVN08AC ENET1 SDIO_2 SDIO_2 ENET1 ENET1 3 OF 5 MIPRCS C10 E9 D8 C9 D D7 E8 E10 C11 Boot configuration for development only. Production boot configuration should be programmed into internal fusebox. Production designs may have all of these resistors below deleted. D11 ENET2 C12 ENET2 E11 ENET2 D10 B9 Boot configuration set for eMMC device on USDHC4 with normal boot. Fast boot can be set once normal boot is operating properly.
8 5 6 7 4 3 2 1 VDD_SNVS VDD_SNVS VDD_SNVS D TP? D NVCC_PLL_CAP VDD_ARM VDD_ARM C? 0.22uF 10% 16V V33 V33 C? 4.7uF 10% 25V +3.3V V33 TP? 22uF cap on C16 VDD_ARM_CAP C? 0.22uF 10% 16V C? 0.22uF 10% 16V U? MCIMX6X2CVN08AC C? 0.22uF 10% 16V 4 OF 5 MIPRCS W20 VDD_EMMC R11 VDD_EMMC H15 VDD_EMMC F6 F15 C? 0.22uF 10% 16V C G15 F13 V10 R6 VDD_ENET F14 VDD_ENET F8 VDD_ENET F9 C? 0.22uF 10% 16V C? 0.22uF 10% 16V R12 R? TP? V13 V5 10K 1% 63mW +1.35V G6 H6 J6 K6 C? 0.
8 5 6 7 4 D? VIN D? BAS16 T/R VIN P1 DFLS160-7 60V DEV P? 105017-0001 DDR3 SODIMM EDGE CONNECTOR 1 3 D 5 7 IO IO IO IO IO IO IO IO 2 4 DEV USB1_OTG USB1_OTG TP? GPIO D 0 DEV R? IO TP? P? NC IO DDR3 SODIMM EDGE CONNECTOR 0 IO 73 DEV +3.3V 9 11 13 LDO1 15 LDO1 IO IO IO IO IO IO IO IO +3.
8 5 6 7 123 SDIO_3 SDIO_3 IO 4 IO 3 2 124 USB1_OTG R? 125 IO IO 1 126 USB1_OTG USB1_D_N USB1_OTG 33.2 127 129 131 D IO IO IO IO IO IO 128 USB1_D_P 130 132 USB1_VBUS USB2_HST 133 IO IO 134 USB2_HST D USB2_VBUS USB2_PWR 135 IO IO 136 USB2_OC_B 137 139 141 SDIO_2 SDIO_2 IO IO IO IO IO 138 USB2_D_N 140 USB2_D_P 33.
8 5 6 7 4 3 2 1 VDD_IO VDD_IO D D +3.3V TP? EMMC_VDDM_CAP R? 10K 1% 63mW R? 10K 1% 63mW C? 0.1uF 10% 16V U? MTFC4GACAJCN-1M_WT C? 1uF 10% 25V C? 4.7uF 10% 25V 1 OF 2 U? MTFC4GACAJCN-1M_WT C? 0.22uF 10% 16V 2 OF 2 FLASH 4GX8 C2 K5 RST_B M5 CMD TP? R? M6 CLK TP? 33.
8 5 6 7 4 3 2 1 Q? FDMA908PZ 1 2 5 6 D D TP? TP? TP? R? VIN TP? D 7 TP? 4 8 220m 1% 250mW G 3 S TP? V33 V33 TP? TP? VIN_2 LDO1 C? 22uF 20% 10V U? INA219AIDCNR C? 22uF 20% 10V C? 22uF 20% 10V TP? LDO3 +3.3V TP? VDD_1P8 CUR/PWR MON -IN +IN LDO4 +3.3V VS GND A0 A1 C? 0.1uF 10% 16V C? 0.1uF 10% 16V SCL SDA C C? 4.7uF 10% 25V C? 1uF 10% 25V C? 4.7uF 10% 25V C? 4.7uF 10% 25V C? 4.
8 5 6 7 4 3 2 1 D D VCC_5V R29 220 1% 62.5mW DL1 R16 TP1 U1_Tx_LED U1_Tx_LED Q1 BSS138 TP7 R15 0 U1_Tx_LED LED APT2012LZGCK GREEN 5V C5 0.1uF 10% 16V R9 10K 220 1% 62.5mW VCC_5V R30 220 1% 62.5mW DL2 R17 U1_Rx_LED TP2 C U1_Rx_LED TP8 U1_Rx_LED R24 10K U2_Tx_LED R26 10K 0 C7 0.1uF 10% 16V R31 220 1% 62.5mW U5_Tx_LED R27 10K U5_Rx_LED U5_Rx_LED 0 U2_Tx_LED APT2012LZGCK GREEN 5V R28 10K 220 1% 62.5mW VCC_5V R32 220 1% 62.
8 5 6 7 4 3 2 1 D D VCC_3V3 VCC_5V C4 LED_ALM GPIO4_08 LED_ALM 1 0.1uF 5 10% 16V 4 GPIO4_08 2 3 U2 SN74LVC1G08 C1 10uF 10% 10V C2 4.7uF 100V 10% C3 0.1uF U1 IS31FL3236-TQLS2 LED DRVR GND 41 R8 R19 4.7K 1% 63mW R20 C 4.7K 1% 63mW SCL_C SDA_C TP22 44 3.
8 D VCC_5V 5 6 7 VCC_5V DL7 ISSI_OUT1 ISSI_OUT1 4 3 VCC_5V DL13 ISSI_OUT7 TP48 2 DL19 ISSI_OUT7 ISSI_OUT13 APT2012LZGCK GREEN 5V ISSI_OUT2 APT2012YC YELLOW 5V DL9 ISSI_OUT3 ISSI_OUT14 APT2012SURCK RED 5V ISSI_OUT9 APT2012YC YELLOW 5V DL10 D2 1N4148W-13 DL21 ISSI_OUT3 R4 C ISSI_OUT16 ISSI_OUT10 APT2012YC YELLOW 5V DL11 ISSI_OUT16 ISSI_OUT10 APT2012SURCK RED 5V DL23 APT2012LZGCK GREEN 5V DL17 D4 1N4148W-13 R5 100 1% 62.
8 7 5 6 4 3 2 1 D D SCL_C J1 61001621821 2 IO J1 61001621821 1 IO U1_Rx_LED U1_Rx_LED SCL_C J1 61001621821 4 IO J1 61001621821 3 IO U1_Tx_LED U1_Tx_LED SDA_C J1 61001621821 6 IO J1 61001621821 5 IO J1 61001621821 8 IO J1 61001621821 7 IO GPIO4_08 J1 61001621821 10 IO J1 61001621821 9 IO U2_Tx_LED LED_ALM J1 61001621821 12 IO J1 61001621821 11 IO U5_Rx_LED U5_Rx_LED J1 61001621821 14 IO J1 61001621821 13 IO U5_Tx_LED U5_Tx_LED J1 61001621821 16 IO J1 61001621821 15 IO
8 5 6 7 D 4 3 2 1 D RT4 1 2 24VAC_OUT 24VAC_OUT RKEF400 3.7W 24VAC V_PREREG 1 D2 1 1 2 TP229 RT3 TP228 2 A C V_PREREG TP230 1 1 1 L11 TP227 4A THMS_PTC_FUSE 1 2920L110/60MR 2W RV1 V56MLA1206N 1 C160 0.1uF 2100V 2 C161 1 0.01uF 100V 2 200V S3DB-13-F C D24 1 A 43V 2 C163 0.001F 20% 50V C C R133 2 1 R131 2 PWR_OFF_B RES 93.1K 1% 100mW 698K 1% 100mW U27 TPS54260DGQR EN: Vinh=1.36V Max V_PREREG L6 1 2 1TP150 2 6.8uH 20% 1.1A B 1 C153 4.
8 5 6 7 4 3 2 1 VCC_5V VCC_5V 1 U5_TX_5V U5_TX_5V R70 2 1 1 TP336 U3_TX_5V S Q1 G 1K D 2 U3_TX_5V 1 R77 2 1 S Q7 G 1K D BSS84PH6327XTSA2 3 VCC_5V 2 D BSS84PH6327XTSA2 3 U1_TX_5V U1_TX_5V 1 R72 D 1 TP352 2 1 2 S Q3 G 1K D BSS84PH6327XTSA2 3 VCC_5V 1 VCC_5V 1 33 1 R52 4.7K 2 U5_RX_5V 1 1 33 UART_LED 2 R82 R71 1 R55 4.
8 5 6 7 4 TP44 SOM_3V3 1 1 R213 20 TP55 1 D41 D42 1N4148W-13 TP43 1 1N4148W-13 A C A C 100V 100V U14 M41T83SMY6 SER RT CLK D43 1N4148W-13 A C 100V D 1 C53 0.1uF 2 10% 16V V_RTC D28 1N4148W-13 A C 15 8 1 TP177 1 100V 2 C119 1F 80% 5.5V 1 C120 0.1uF 2 10% 16V I2C_2 I2C_2 SOM_3V3 1 R8 4.7K 2 1% 1 R27 4.
8 5 6 7 4 3 2 1 VCC_5V SOM_3V3 1 C179 UART5 D UART_5 UART_5 UART5_TX VCC_5V 1 R207 2 0.1uF 16V 10K 2 1% 63mW GND 1 TP184 U30 SN74LV1T34DCKR 5 4 1 2 2 0.1uF TP181 3 GND VCC_5V 5 2 2 0.1uF 2 8 GND GND 1TP366 7 U5_TX_5V U5_TX_5V 1TP365 5 TP182 U5_RX_5V 1 TP183 UART5_RX VCC 1TP364 4 U5_RX_5V VISOOUT Y Z TXD RE A B 1 C C84 0.1uF 2 0.1uF 2 19 FGND1 1 L17 2 12 1BLM15HD182SN1D C94 200mA 2 0.1uF 13 15 GND2 GND1 3 2 0.001uF 10% 2KV GND 1 A1 2 D15 2 7.
8 5 6 7 4 3 2 1 VCC_5V ENET_1 UART_1_TX EN1_MDIO 1 TP218 C182 U33 GND 1 2 SN74LV1T34DCKR GPIO3_19 0.1uF 5 2 4 GND GPIO_ALT_FUNC GPIO_ALT_FUNC 1 R174 4.7K 2 1 TP326 1TP327 GND EN1_MDC 1 SOM_3V3 1 RE 4 1 3 9 GND 10 GND1 C198 1 4 GND 3 1 1 1 L14 2 1 TP25 A3 A3 2 D35 BLM15HD182SN1D 200mA 7.5V 2 1 TP215 1 L29 2 FGND3 470pF 10% 2KV C63 1 2 2 1200315010 TP214 ACML-0603-202-T 200mA ACML-0603-202-T 1 R129 200mA 100K 2 1% 62.
8 5 6 7 D SDIO_3 UART_4_RE/DE UART4 UART_4_TX VCC_5V SOM_3V3 1 R130 4.7K 2 1 R104 10K 2 1% 63mW SD3_CMD 1 R103 10K 2 1% 63mW 3 2 1 1 GND [RTX] EN1[DE] VDD EN2[RE] GND [D] 8 1 SD3_DATA3 Rs485_MMI_A Rs485_MMI_A 6 7 Rs485_MMI_B Rs485_MMI_B 2[R] UART_4_RX SOM_3V3 2 D 1 C102 0.1uF 2 5 1 1 TP223 1 1 TP222 4 TP226 2 VCC_5V U26 GPIO4_01 SDIO_3 3 RS485 for MMI 1 TP219 GPIO_ALT_FUNC GPIO_ALT_FUNC 4 GND C83 0.
8 5 6 7 4 3 2 1 U19 KSZ9897RTXI VDD_2V5 1 TP314 96 nSW_RESET 100 nETH_SPI_CS R1 127 1 2 60 NC 6.04K 79 1% 100mW NC 51 NC 69 NC Y2 1 D 2 LF XTAL036742 1 C70 22pF 2 5% 50V LDO4_1V8 SOM_3V3 1 R2 U1 4.7K 2 SN74LV1T34DCKR SPI_5 SPI_5 2 1 ENET_1 ENET_1 EN1_TX_CTL 49 ENET_2 1 5 2 S5_SS3_B TP306 R155 2 0 EN2_TX_CTL1 4 nETH_SPI_CS 3 EN2_TXC LDO4_1V8 R1581 R1591 EN2_TXDAT1 EN2_TXDAT0 C 1 C46 0.1uF 2 U2 SN74LV1T34DCKR SW_TXRX P2_TXRXA_P12 4 P2_TXRXA_N13 ETH_SPI_SCK 3 1 R3 4.
8 5 6 7 4 3 2 1 D D VDD_1V2 1 C67 10uF 2 10% 10V 1 C68 10uF 2 10% 10V 1 C69 10uF 2 10% 10V VREG 12 1 2 4 1 TP60 1 1 NOTE: CAPACITORS C21 MUST BE LOCATED AS CLOSE TO PINS 6 AND 7 AS POSSIBLE VCC AVIN TP59 PGOOD 1 C28 0.0068uF 2 10% 25V R24 2.74K 1 1% 100mW 2 TP62 10 11 15 17 1 TP63 1 C22 0.
8 5 6 7 4 VDDA_3V3_100M D SOM_3V3 ABM8G-25_000MHZ-18-D2Y-T Y3 U18 KSZ8863RLLI 1 LDO4_1V8 1 L10 2 BLM21PG221SN1D 2A 1 C177 1 C173 1uF 22uF 2 10% 2 10% 16V GND 10V 2 LDO4_1V8 1 L13 2 VDDA_3V3_100M 1C169 0.1uF 2 3 1 L12 2 BLM21PG221SN1D 1 C171 2A 1 C175 1uF 22uF 2 10% 2 10% 16V GND 10V 1C166 0.1uF 2 1C167 0.1uF 2 1C168 0.
8 5 6 7 4 3 2 1 SW_TXRX SW_TXRX VDDA_3V3_100M P1_TXRXA_P 100M_TXRX 100M_TXRX P1_TXRXA_N R1501 20 R1511 20 100M_P1_RX_P DN1 DIONTWK 100M_P1_RX_N R1861 20 R1851 20 VDDA_3V3_100M 1 3 ETH1_10 D 100M_P1_TX_P 5 2 100M_P1_TX_N R1421 6 1 C47 0.
8 5 6 7 4 3 2 1 VDDA_3V3_100M SW_TXRX SW_TXRX P2_TXRXA_P P2_TXRXA_N 100M_TXRX DN3 DIONTWK ETH2_10 100M_TXRX R1621 1 100M_P2_TX_NR163 20 20 R1561 R1571 100M_P2_RX_N 20 20 100M_P2_TX_P 1 3 R1881 20 R1871 20 1 C192 10uF 2 10% 10V ETH2_11 100M_P2_RX_P D VDDA_3V3_100M 1 C50 0.
8 5 6 7 4 3 2 1 SOM_3V3 SOM_3V3 GPIO_ALT_FUNC 21 GPIO_ALT_FUNC 1 TP126 33 1 R63 2 GPIO4_14_nBB_RESET WiFi/BLE PWR RST 1 3 D 4 IO USB2_HST USB2_HST USB2_HST 5 USB2_DP 7 USB2_DN 9 USB1_DP 13 USB1_DN 15 VCC_5V 17 19 23 GPIO_ALT_FUNC 6 USB2_PWR 8 IO IO IO 12 IO IO IO USB1_PWR_3V3 IO VCC_5V IO USB1_ID IO 20 IO 24 SDIO_2 IO SDIO_2 26 IO 28 IO UART_LED SOM_3V3 UART_LED SOM_3V3 30 SD2_DATA1 IO 33 1 R189 1 4.
8 5 6 7 4 3 2 1 Top connector 1 R217 2 RES Top connector 1 0 R216 2 RES 0 Isolated RS485 C207 GND3 CH3- CH3+ GND2 CH2- CH2+ GND1 CH1- CH1+ 1 AC24V D 24V GND 24VAC EARTH D 0.001uF 10% 2KV C206 1 2 2 C43 1 1 1 TP324 To the 3-pin terminals: Pin1 ---- 24VAC Pin2 ---- EGND PIn3 ---- GND 1 TP325 24VAC 0.001uF 10% 2KV C112 1 2 0.
8 5 6 7 4 3 2 1 TP16 1 WD_COM WD_COM K1 ALQ1F05 4 2 1 5 VCC_5V 2 TP17 1K C VCC_5V C103 0.1uF 2 11 U20 LM339D 3 10 + - 13 3 4 12 1 R119 1K 2 1% 63mW TP1731 3 1 2 A SOM_3V3 VCC_5V U20 LM339D A 1 D20 1N4148W-13 2 100V C 9 1 TP165 1 R101 4.7K 2 1 TP166 3 14 + - D1 BAV99LT1G SOM_3V3 SOM_3V3 8 R1121 1 C151 1uF 2 10% 16V U43 CAT811TTBI-GT3 1C80 0.1uF 2 4 20 3 12 1 1C205 1 NOTE: 0.1uF CAPACITOR C205 can share same package 2 2 with C128 C104 0.
