User's Manual

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DKL1608-S User Manual

FCC ID: SQ9DKL1608 IC: 5768A-DKL1608

1 CONTROL STATES

1.1 POWER-ON RESET

When power is applied to VDD and is over 1.9V threshold, DKL1608-S will run power-on reset.

Once power-on reset is completed, the device will be in power-down mode.

1.2 POWER-DOWN MODE

In power-down mode, DKL1608-S is in deep-sleep and only the SPI interface is active. DKL1608-S

is in power-down mode when PWR_ON is set to 0.

The device enters power-down mode whenever PWR_ON is set to zero.

1.3 STANDBY MODE

Setting PWR_ON bit to “1” will activate device to standby mode (while CE remains 0). In standby

mode, the crystal oscillator is active, and the device is ready to quickly enter TX or RX mode.

1.4 TX MODE

DKL1608-S transmits packets in TX mode. To operate in TX mode, the device needs to be set up as

a PTX (RX_ON=0), standby mode (PWR_ON=1), and a payload(s) in FIFO. There are two modes of

TX: pulsed (single packet mode) and continuous mode. A CE high pulse of at least 10 us triggers a

single packet to be sent. Keeping CE high will set the device to continuous TX mode, which will

send out all packets in FIFO. After FIFO is emptied, the device will power-off radio and digital

baseband to save current, but the device will commence transmission as soon as a new payload

enters FIFO.

When auto-ACK feature is enabled, a PRX device automatically enters TX mode to send back an

ACK packet after a valid packet is received from a PTX.

1.5 RX MODE

DKL1608-S receives packets in RX mode. The device needs to be set up as a PRX (RX_ON=1) and

in standby mode (PWR_ON=1). Pulling CE pin high sets the device to RX mode and will continue

listening for packets as long as CE is held high. Payloads of valid packets will be placed into the RX

FIFO.

When auto-ACK feature is enabled, a PTX device automatically enters RX mode after transmission

to listen for an ACK packet from the PRX.

1.6 RADIO SETUP

DKL1608-S supports 250kbps, 1Mbps, and 2 Mbps air bit rate. The choice of which bit rate to use

depends on range, current consumption, and data rate needed. Lower bit rate has longer range,

while higher bit rate has lower current consumption and reduced probability of in-air collision.

Air rate is set by the SETUP_RF register.

The channel may be set in 1 MHz increment from 2400 MHz to 2483 MHz. Although it is possible

Summary of content (15 pages)

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DKL1608-S User Manual FCC ID: SQ9DKL1608 IC: 5768A-DKL1608 1 CONTROL STATES 1.1 POWER-ON RESET When power is applied to VDD and is over 1.9V threshold, DKL1608-S will run power-on reset. Once power-on reset is completed, the device will be in power-down mode. 1.2 POWER-DOWN MODE In power-down mode, DKL1608-S is in deep-sleep and only the SPI interface is active. DKL1608-S is in power-down mode when PWR_ON is set to 0. The device enters power-down mode whenever PWR_ON is set to zero. 1.
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to set the channel frequency higher than 2483 MHz, it is not recommended for this may violate regional regulations. For 250kbps and 1Mbps operation, the channel may be set in 1 MHz increment; for 2Mbps operation, the channel spacing should be 2 MHz or more. Channel selection is set by the RF_CH register. In addition to the device address, the bit rate and channel frequency need to be set the same for the radios to communicate with each other. 1.
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2 PACKET INFORMATION 2.1 PACKET FORMAT Packet Format The packet consists of 5 portions: preamble, address, packet control, payload, and CRC. The preamble, address, and payload are required fields; packet control and CRC are optional fields, depending on settings. 2.2 PREAMBLE The preamble is a one-byte alternating sequence of 01010101 or 10101010, depending on the first bit in the address.
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2.5 PAYLOAD The payload can be 1 to 32 bytes wide. The payload can be set either static or dynamic in length, defined by the packet control field. The default setup is static payload length. The static payload length is set by the RX_PW_Px register on the receiver side. Payload length on the transmitter side is set by the number of bytes placed in the TX_FIFO and must be equal to the value set in the RX_PW_Px register on the receiver side.
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used as an indicator of overall channel quality. The PTX device will retransmit if its RX FIFO is full but receives an ACK packet with payload. As an alternative for the PTX to auto retransmit, it is possible to manually set the device to retransmit a packet a number of times. This is done by the REUSE_TX_PL command. When auto-ACK is enabled, it is possible for the PRX to send a payload along with the ACK packet. To use this feature, the EN_ACK_PAY bit in the FEATURE register needs to be set.
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Interrupt is activated when the TX_DS, RX_DR, or MAX_RT in the STATUS register is set high. The IRQ pin is reset when the host writes “1” to the IRQ source bit in the STATUS register. In the CONFIG register, there are three mask bits, which may be used to set which event triggers the IRQ pin. By default all IRQ sources are enabled. Please note that the 3-bit pipe information in the STATUS register is updated during the IRQ pin transition.
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unwritten MSByte(s) unchanged. Note: The 3 bit pipe information in the STATUS register is updated when IRQ pin changes from high to low. Therefore, the pipe information is unreliable if the STATUS register is read during an IRQ transition. Table 1: SPI Commands Command name Command word Number (binary) of data Description bytes R_REG 000X XXXX 1 to 5 Read registers. XXXXX is the 5-bit register address W_REG 001Y YYYY 1 to 5 Write to registers. YYYYY is the 5bit register address.
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R_RX_PL_WID 0110 0000 1 Read RX payload width of the top R_RX_PLOAD in the RX FIFO. * If read value is larger than 32 bytes, then FLUSH_RX. W_ACK_PLOAD 1010 1ZZZ 1 to 32 W_TX_PLOAD_NOACK 1011 0000 1 to 32 NOP 1111 1111 0 Used in RX mode. Write payload to be transmitted w/ ACK packet on pipe ZZZ. (ZZZ is from 000 to 101) Maximum of three ACK packet payloads may be pending. Used in TX mode. Disable auto- ACK for this specific packet No operation.
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SPI NOP Command Table2: SPI Timing Symbol Tdc Tdh Tcsd Tcd Tcl Tch FCLK Tr/Tf Tcc Tcch Tcwh Tcdz Parameters Data to CLK setup CLK to data hold CSN to data valid CLK to data valid CLK low time CLK high time CLK frequency CLK rise & fall time CSN to CLK setup CLK to CSN hold CSN inactive time CSN to output high Z Minimum 3 3 Maximum 38 55 40 40 0 10 100 3 3 50 38 Units n n n n n n MH n n n s n s n 3.
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00 01 02 CFG_TOP Top-level configuration 7 0 R/W Must be 0 for normal operation Reserved MASK_RX_DR 6 0 MASK_TX_DS 5 0 R/W Mask interrupt caused by RX_DR; 1: interrupt not reflected on IRQ pin; 0: reflect RX_DR as active low interrupt on IRQ pin R/W Mask interrupt caused by TX_DS; 1: interrupt not reflected on IRQ pin; 0: reflect TX_DS as active low interrupt on IRQ pin MASK_MAX_RT 4 0 R/W EN_CRC 3 1 R/W CRCC 2 0 R/W CRC scheme 0: 1 byte, 1: 2 bytes PWR_ON 1 0 R/W 1: power-up,
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03 ENRX_P5 5 0 R/W Enable data pipe 5 ENRX_P4 4 0 R/W Enable data pipe 4 ENRX_P3 3 0 R/W Enable data pipe 3 ENRX_P2 2 0 R/W Enable data pipe 2 ENRX_P1 1 1 R/W Enable data pipe 1 ENRX_P0 0 1 R/W Enable data pipe 0 SETUP_AW Address width & timing setup Reserved 7:4 0 R/W Unused Reserved 3:2 11 R/W Reserved setting, must be set to 11 1:0 11 R/W Reserved setting, must be set to 11 Reserved 04 05 06 SETUP_RETR Automatic retransmission setup ARD[3:0] 7:4 0000
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07 08 09 TX_ATTN 4 0 R/W TX low-power mode Confirm actual attenuation level RF_DR_HIGH 3 0 R/W RF_PWR[1:0] 2:1 01 R/W Reserved 0 0 R/W [RF_DR_LOW, RF_DR_HIGH] 00: 1Mbps 01: 2Mbps 10: 250kbps Set RF output power in TX mode 00: -18 dBm 01: -12 dBm 10: -6 dBm Unused Status (read-out from SDO pin during SPI command word input); SDO output may be adjusted Unused STATUS Reserved 7 0 R/W RX_DR 6 0 R/W TX_DS 5 0 R/W MAX_RT 4 0 R/W RX_P_NO[2:0] 3:1 111 R TX_FULL 0 0 R OB
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EN_RSSI 4 0 R/W Enable RSSI 3 0 R Reserved register readout 2 0 R Reserved register readout RSSI2 1 0 R RSSI indicator at threshold 2 RSSI1 0 0 R RSSI indicator at threshold 1 Reserved Reserved 0xE7 39:0 E7E7 E7E7 0xC2 39:0 C2C2 C2C2 RX address data pipe 0. 5 bytes maximum. LSB byte written first. Number of bytes used set by SETUP_AW. RX address data pipe 1. 5 bytes maximum. LSB byte written first. Number of bytes used set by SETUP_AW.
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15 16 17 Reserved 7:6 00 R/W Unused RX_PW_P3 5:0 0 R/W Number of bytes in RX payload in data pipe 3 (1 to 32). 0: pipe not used Reserved 7:6 00 R/W Unused RX_PW_P4 5:0 0 R/W Number of bytes in RX payload in data pipe 4 (1 to 32). 0: pipe not used Reserved 7:6 00 R/W Unused RX_PW_P5 5:0 0 R/W Number of bytes in RX payload in data pipe 5 (1 to 32).
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1C 1D RSSIREC2[7:0 ] 15:8 01110 R 010 RSSIREC1[7:0 ] 7:0 01000 R 001 RSSI2 recorder, MSB is most recent recording, any write command on this register will flush RSSI setting; when RX_ON=0, PWR_ON=0 register will RSSI1 recorder, MSB& CE=0, is most recent recording, any write command on this register will flush RSSI setting; when RX_ON=0, PWR_ON=0 & CE=0, register will Dynamic payload length Reserved 7:6 00 R/W Unused DPL_P5 5 0 R/W Set 1 to enable dynamic payload length data pipe 5 (requires