GM500-U1G_A Hardware Development Guide Version: V1.0 Date: 2020-11-20 LTE Module Series Website: www.gosuncnwelink.com E-mail: welink@gosuncn.
GM500-U1G_A Hardware Development Guide Revision History Version Date Description 1.
GM500-U1G_A Hardware Development Guide About This Document A. Application Range This document is the Product Technical Specification for the GM500-U1G_AGSM/WCDMA/LTE-FDD module. It defines the high level product features and illustrates the interface for these features. This document is intended to cover the hardware aspects of the product, including electrical and mechanical. B. Reading Note The symbols below are the reading notes you should pay attention on: : WARNING or ATTENTION C.
GM500-U1G_A Hardware Development Guide LDO Low-Dropout LED Light Emitting Diode LTE Long Term Evolution ME Mobile Equipment MO Mobile Origination Call MT Mobile Termination Call MSB Most Significant Bit PC Personal Computer PCB Printed Circuit Board PDA Personal Digital Assistant PDU Protocol Data Unit PAP Password Authentication Protocol PPP Point to Point Protocol RTC Real Time Clock SMS Short Messaging Service SMT Surface Mount Technology SPI Serial Peripheral Interface
GM500-U1G_A Hardware Development Guide Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating ME3610 module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel and to incorporate these guidelines into all manuals supplied with the product.
GM500-U1G_A Hardware Development Guide Contents Revision History ........................................................................................................................................................................... I About This Document ....................................................................................................................................................................... II Safety Information ............................................................
GM500-U1G_A Hardware Development Guide 2.16. GPIO Interface ................................................................................................................................................................................. 49 2.17. USB_BOOT ................................................................................................................................................................................. 50 2.18. SD Card Interface ................................................
GM500-U1G_A Hardware Development Guide 7.4.3. Module Baking Conditions ......................................................................................................................................................
GM500-U1G_A Hardware Development Guide Tables Table 1-1 GM500-U1G_A Supported Band .................................................................................. 12 Table 1-2 GM500-U1G_A Key Features....................................................................................... 12 Table 2-1 IO Parameters Definition .............................................................................................. 17 Table 2-2 Logic levels Description .................................................
GM500-U1G_A Hardware Development Guide Table 4-1 Absolute Maximum Ratings .......................................................................................... 58 Table 4-2 Operating Temperature ................................................................................................ 58 Table 4-3 ESD characteristic ........................................................................................................ 58 Table 4-4 Averaged standby DC power consumption [1] ......................
GM500-U1G_A Hardware Development Guide Figures Figure 1–1 System Connection Structure ..................................................................................... 14 Figure 2–1 Pin Assignment .......................................................................................................... 16 Figure 2–2 The input reference circuit of VBAT ............................................................................ 25 Figure 2–3 Reference circuit of DC-DC ...................................
GM500-U1G_A Hardware Development Guide Figure 2–30 WAKEUP_IN input sequence ................................................................................. 47 Figure 2–31 WAKEUP_IN reference design ................................................................................. 48 Figure 2–32 The output signal of WAKEUP_OUT ........................................................................ 49 Figure 2–33 WAKEUP_OUT reference design ................................................................
GM500-U1G_A Hardware Development Guide 1. Product Overview 1.1. General Description GM500-U1G_A isaLTE/WCDMA wireless communication module with LCC+LGA interface. It is widely applied to but not limited to the various products and equipment such as laptops, vehicle-mounted terminals, and electric devices, by providing data services. Customer can choose the dedicated type based on the wireless network configurationand using area.
GM500-U1G_A Hardware Development Guide Support RTS and CTS hardware flow control Baud rate can reach up to 921600 bps,115200 bps by default Used for AT command, data transmission or firmware upgrade Debug UART interface: Two lines on debug UART interface, can be used for software debug, firmware upgrade USB Interface Compliant with USB 2.0 specification (slave only) Used for AT command communication, data transmission, software debug and firmware upgrade. SDIO interface 1.
GM500-U1G_A Hardware Development Guide Data Control Baseband Rx&Tx Control Rx GNSS Rx RF Transceiver Tx Duplexer Duplexer RF PA Rx 80PIN LCC Connector Interface FLASH & LPDDR2 USB USIM UART I2C SDIO SPI LED ADC GPIO MAIN_ANT DIV_ANT Figure 1–1System Connection Structure 1.4.
GM500-U1G_A Hardware Development Guide 2. Application Interface 2.1. General Description GM500-U1G_A is equipped with 80 LCC pads plus 16 ground pads and 22 LGA pads that connect to customer’s cellular application platform.
GM500-U1G_A Hardware Development Guide Figure 2–1 Pin Assignment 2.3. Pin Description The following table shows the IO Parameters Definition.
GM500-U1G_A Hardware Development Guide Table 2-1 IO Parameters Definition Type Description IO Bidirectional input/output DI Digital input DO Digital output PI Power input PO Power output AI Analog input AO Analog output OD Open drain The logic levels are described in the following table. Table 2-2 Logic levels Description Parameter Min Max Unit VIH 0.65*VDD_IO VDD_IO+0.3 V VIL -0.3 0.35* VDD_IO V VOH VDD_IO-0.45 VDD_IO V VOL 0 0.
GM500-U1G_A Hardware Development Guide 117 Turn On/Off Pin Name Pin NO. I/O Description DC Characteristics Comment POWER_ON 1 DI Turn on/off VIH max = 2.1V Pull-up to 0.8V internally, active low module,level trigger VIH min = 1.17V (active low) VIL max = 0.63V Level high triggered VIH max = 2.1V power on input VIH min = 1.17V PON_TRIG 66 DI VIL max = 0.63V RESET_N 2 DI Reset module VIH max = 2.1V Active low VIH min = 1.17V VIL max = 0.63V Status Indication Pin Name Pin NO.
GM500-U1G_A Hardware Development Guide USIM1_DATA 38 IO Data signal of USIM1 For 1.8V USIM: Pull-up to USIM1_VCC with 10k card VIL max = 0.63V resistor internally VIH min = 1.17V VOL max = 0.45V VOH min = 1.35V For 3V USIM: VIL max = 1.05V VIH min = 1.95V VOL max = 0.45V VOH min = 2.6V USIM1_CLK 37 DO Clock signal of USIM1 For 1.8V USIM: card VOL max = 0.45V VOH min = 1.35V For 3V USIM: VOL max = 0.45V VOH min = 2.6V USIM1_RST 39 DO Reset signal of USIM1 For 1.
GM500-U1G_A Hardware Development Guide VIH max = 2.1V UART_CTS 56 DI Clear to send VOL max = 0.45V 1.8V power domain VOH min = 1.35V UART_DSR 57 DO Data set ready VIL min = -0.3V 1.8V power domain. VIL max = 0.63V DO not pull-up external. VIH min = 1.17V VIH max = 2.1V UART_DTR 58 DI Data terminal ready VIL min = -0.3V 1.8V power domain. VIL max = 0.63V VIH min = 1.17V VIH max = 2.1V UART_DCD UART_RI 59 60 DO DO Data carrier VOL max = 0.45V detection VOH min = 1.
GM500-U1G_A Hardware Development Guide SDIO_CMD 14 IO Secure digital CMD VOL max = 0.45V Pull-up to 1.8V through external 10K VOH min = 1.35V resistance VIL min = -0.3V VIL max = 0.63V VIH min = 1.17V VIH max = 2.1V SDIO_CLK 19 DO Secure digital CLK VOL max = 0.45V 1.8V power domain VOH min = 1.35V SDIO_DATA0 15 IO Secure digital IO data VOL max = 0.45V bit 0 VOH min = 1.35V 1.8V power domain VIL min = -0.3V VIL max = 0.63V VIH min = 1.17V VIH max = 2.
GM500-U1G_A Hardware Development Guide V OL max=0.38V SDC2_DATA0 113 IO Secure digital V OH min=2.01V controller 2 data bit 0 V IL min=-0.3V V IL max=0.76V SDC2_CMD 111 IO Secure digital V IH min=1.72V controller 2 V IH max=3.34V command SDC2_CLK 112 DO Secure digital 1.8V： controller 2 clock V OL max=0.45V V OH min=1.4V 3.0V： V OL max=0.38V V OH min=2.01V SDC2_DET_N 114 DI Secure digital card V IL min=-0.3V detection V IL max=0.6V V IH min=1.2V 1.
GM500-U1G_A Hardware Development Guide For 2.85V: VOLmax=0.35V VOHmin=2.14V VILmax=0.71V VIHmin=1.78V SGMII_MDIO_CLK 85 DO Management data For 1.8V: 1.8V/2.85V power domain input output clock VOLmax=0.45V If do not need this, leave this pin not VOHmin=1.4V connected. For 2.85V: VOLmax=0.35V VOHmin=2.14V SGMII_RX_P 103 AI SGMII RX+ Use 0.1 µF AC coupled capacitor, and place closer to module. If do not need SGMII, leave this pin not connected. SGMII_RX_M 104 AI SGMII RX- Use 0.
GM500-U1G_A Hardware Development Guide VIH max = 2.1V SPI Interface Pin Name Pin NO. I/O Description DC Characteristics Comment SPI_MISO 32 IO SPI main input slave VOL max = 0.45V 1.8V power domain output VOH min = 1.35V VIL min = -0.3V VIL max = 0.63V VIH min = 1.17V VIH max = 2.1V SPI_MOSI 33 IO SPI main output slave VOL max = 0.45V input VOH min = 1.35V 1.8V power domain VIL min = -0.3V VIL max = 0.63V VIH min = 1.17V VIH max = 2.1V SPI_CLK 34 DO SPI clock VOL max = 0.45V 1.
GM500-U1G_A Hardware Development Guide Table 2-4Power Supply Pin Name Pin NO. Description Minimum Typical Maximum Unit VBAT 50,51 Power supply for module 3.4 3.8 4.2 V GND 3,9,11,20,21,31,36,46,49,5 Ground - - 2,61,63,78,80,81,87~102,1 07,117 GND signal is the power and signal ground of the module, which needs to be connected to the ground on the system board. If the GND signal is not connected completely, the performance of module will be affected. 2.4.2.
GM500-U1G_A Hardware Development Guide Figure 2–3 Reference circuit of DC-DC Option 2:LDO The over-current capability of LDO is above 2.5A. This LDO is apply to this situation: input and output voltage difference is small. The reference power supply circuit design with LDO is shown as figure below: Figure 2–4 Reference circuit of LDO 2.5.
GM500-U1G_A Hardware Development Guide Figure 2–5 Reference circuit of POWER_ON The table below is the information of power-on/off pin Table 2-5 Definition of POWER_ON Pin Name Pin NO. I/O Description Comment POWER_ON 1 DI Turn on/off the module low active. Pull-up to 0.8V internally The power on scenarios is illustrated as the following figure, the module will power on and working when the POWER_ON pin keep in low level for T1, in this process , please ensure VBAT steady.
GM500-U1G_A Hardware Development Guide Ensure VBAT steady VBAT T1 POWER_ON T2 RESET_N Figure 2–6 Timing of Turning on Mode Table 2-6 Power-on Time Parameter Description Min Typical Max Unit T1 The period that the Power-on signal for power on operation is kept on the low PWL 0.1 0.2 -- Second T2 The minimum interval between the POWER_ON and RESET signals if you want to 10 15 -- Second reset the module after power-on. 2.6.
GM500-U1G_A Hardware Development Guide VBAT high level T2 POWER_ON T3 Module Status Running Turning off Power off Figure 2–7Timing of Turning off Mode Mode 2: Send command of AT+ZTURNOFF, and the power off process will take 15s at least. Note:when using modules, you need to avoid power off abnormally and frequently, as it will cause several risks shown as below: 1. it will damage the flash permanently. 2.
GM500-U1G_A Hardware Development Guide Figure 2–8reference circuit to reset module The reset scenario is illustrated as the following figure, VBAT high level 1s RESET_N 27s Module Status Running Resetting COM can send/receive AT Running Figure 2–9Timing of Reset Mode Mode 2: Send command of AT+ZRST, and the RESET process until the AT port can communicate will take 27s at least.
GM500-U1G_A Hardware Development Guide 2.8. USIM Card Interface 2.8.1. Description of USIM pins The USIM card interface circuitry meets ETSI and IMT-2000 SIM interface requirements. Both 1.8V and 3.0V USIM cards are supported. Table 2-8Pin Definition of the USIM Interface Pin Name Pin NO. I/O Description Comment USIM1_VCC 40 PO Power supply for USIM1 card Either 1.
GM500-U1G_A Hardware Development Guide Figure 2–10Reference Circuit of the 8 Pin USIM Card GM500-U1G_A supports USIM card hot-plugging via the USIM_ DETECT pin. For details, refer to document [AT Command Reference Guide of Module Product GM500-U1G_A]. If you do not need the USIM card detect function, keep USIM_ DETECT unconnected. The reference circuit for using a 6-pin USIM card socket is illustrated as the following figure.
GM500-U1G_A Hardware Development Guide Figure 2–12Molex 91228 USIM Card Holder Table 2-9Pin Description of Molex USIM Card Holder Pin Name Pin NO. Function GND 1 Ground VPP 2 Not connected DATA I/O 3 USIM card data CLK 4 USIM card clock RST 5 USIM card reset VDD 6 USIM card power supply DETECT 7 USIM card Detection NC 8 Not defined, Connect to Ground For 6-pin USIM card holder, it is recommended to use Amphenol C707 10M006 512 2. Please visit http://www.amphenol.
GM500-U1G_A Hardware Development Guide Figure 2–13Amphenol C707 10M006 512 2 USIM Card Holder Table 2-10Pin Description of Amphenol USIM Card Holder Pin Name Pin NO.
GM500-U1G_A Hardware Development Guide RST 5 USIM card reset VDD 6 USIM card power supply 2.9. USB Interface GM500-U1G_A contains one integrated USB transceiver which complies with the USB 2.0 specification and supports high speed (480 Mbps), full speed (12 Mbps) and low speed (1.5 Mbps) mode. The USB interface is primarily used for AT command, data transmission, software debug and firmware upgrade. The following table shows the pin definition of USB interface.
GM500-U1G_A Hardware Development Guide Figure 2–15Reference Circuit of USB Communication between module and AP When USB is not the desired function, connect differential signal, power and GND via test points. We recommend to connect these pins to the standard pin header in order to convenient for debugging and upgrading. Figure 2–16 Reference circuit of USB when USB is not the desired function Note: we recommend connecting the USB interface for update and debugging the module.
GM500-U1G_A Hardware Development Guide 2.10. UART Interface The module provides two UART interfaces: Main UART Port and Debug UART Port. The Main UART Port can work in full function mode while the Debug UART Port is used for software debugging . The following show the different features.
GM500-U1G_A Hardware Development Guide Figure 2–17Schematic of 8-wire UART Connection 2. 3-wire UART connection: (DCE) Serial Port (DTE) Serial Port TX D TX D RX D RX D RTS RTS CTS CTS DTR DTR DCD DCD RING RING DS R DS R GND GND Figure 2–18 Schematic of 3-wire UART Connection 3.
GM500-U1G_A Hardware Development Guide Figure 2–20Recommended TXD circuit All Rights reserved, No Spreading abroad without GOSUNCN Permission 39
GM500-U1G_A Hardware Development Guide Figure 2–21Recommended RXD circuit All Rights reserved, No Spreading abroad without GOSUNCN Permission 40
GM500-U1G_A Hardware Development Guide Figure 2–22Recommended RTS circuit All Rights reserved, No Spreading abroad without GOSUNCN Permission 41
GM500-U1G_A Hardware Development Guide Figure 2–23Recommended CTS circuit All Rights reserved, No Spreading abroad without GOSUNCN Permission 42
GM500-U1G_A Hardware Development Guide 2.10.3.
GM500-U1G_A Hardware Development Guide Figure 2–25Recommended 4-wires UART level switch circuit Figure 2–26Recommended 2-wires UART level switch circuit Debug UART Interface Debug UART Interface is 2-wires interface, we recommend the use to connect this two pins to test points or jumper header. Figure 2–27 The test point of debug UART 2.11. Network Status Indication The network indication pin LED_MODE can be used to drive a network status indicator LED.
GM500-U1G_A Hardware Development Guide Table 2-15Working State of the Network Indicator LED Status Module status High level, LED on Module register to networksuccess Low level, LED off Module not register to network(module is in flight mode or power off) Low level 1s(LED off), High level 1s(LED on) PDP activated, and get the IP address or Socket established Figure below is the reference circuit design diagram.
GM500-U1G_A Hardware Development Guide 2.13. ADC Interface The module provides 3 ADCs to digitize the analog signal to 15-bit digital data such as battery voltage, temperature and so on. Using AT commandcan read the voltage value on ADC pin. The read value is expressed in mV. For more details of these AT commands, please refer to document [AT Command Reference Guide of Module Product GM500-U1G_A]. In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground.
GM500-U1G_A Hardware Development Guide ADC3 0.3 VBAT 1/3 1M 100 nA Table 2-20ADC interface features(x1 scaling) Item VIN Min(V) VIN Max(V) ADC channel Minimum input Maximum configuration resistance(MΩ) input current ADC1 0.1 1.7 1 10M 100 nA ADC2 0.1 1.7 1 10M 100 nA ADC3 0.1 1.7 1 10M 100 nA NOTE: ADC input voltage should not exceed VBAT; The internal reference voltage of ADC is 1.
GM500-U1G_A Hardware Development Guide Figure 2–31 WAKEUP_IN reference design NOTE: There is Anti-shake design with WAKEUP_IN pin internal, when pull up or down this pin by external processor, the level must last more than 500ms.WAKEUP_IN Usage scenario you can refer to the document namedGOSUNCNGM500-U1G_AModule Power Management Design Guide.pdf 2.15. WAKEUP_OUT Signal The module provides the WAKEUP_OUT pin which is used to wake up the external devices.
GM500-U1G_A Hardware Development Guide 1s High WAKEUP_OUT： low Module state： Sleep state Wake up state Figure 2–32 The output signal of WAKEUP_OUT Figure 2–33 WAKEUP_OUTreference design NOTE: WAKEUP_OUT Usage scenario you can refer to the document namedGOSUNCNME3630Module Power Management Design Guide.pdf 2.16. GPIO Interface Module provides 9 GPIO pins. The direction and output voltage level of the GPIO can be set by AT command "AT+ZGPIO".
GM500-U1G_A Hardware Development Guide document [AT Command Reference Guide of Module Product GM500-U1G_A]. NOTE: All the GPIO pins are pull-down internally and are input pins in default. Table 2-23Pin Definition of GPIO Pin Name Pin NO. I/O Description Comment GPIO1 27 IO General input/output 1.8V power domain, GPIO2 28 IO General input/output 1.8V power domain GPIO3 29 IO General input/output 1.8V power domain GPIO4 30 IO General input/output 1.
GM500-U1G_A Hardware Development Guide SDC2_CLK 112 DO Secure digital controller 2 clock SDC2_DET_N 114 DI Secure digital card detection 1.8V power domain If do not need this, leave this pin not connected. SDC2_PWR_EN 115 DO Secure digital card power enable 1.8V power domain If do not need this, leave this pin not connected. VREF_2P85 116 PO Secure digital card signal pull up 1.8V/2.
GM500-U1G_A Hardware Development Guide 6) In order to ensure the signal quality, it is recommended to add pull-ups R7 ~ R11, default NA,on the SDC2_DATA_[0:3] and SDC2_CMD lines. The resistance range is 10 ~ 100k Ω, recommended 100k Ω. 2.19. SGMII Interface Table 2-26 Pin Definition of SGMIIInterface Pin Name Pin NO. I/O Description Comment EPHY_INT_N 82 DI Ethernet PHY interrupt 1.8V power domain If do not need this, leave this pin not connected. EPHY_RST_N 83 DO Ethernet PHY reset 1.8V/2.
GM500-U1G_A Hardware Development Guide Module AR8033 VREF_L5 VREF_1V8 1.5K 10K EPHY_INT_N EPHY_RST_N SGMII _MDIO _DATA INT RST_N MDIO SGMII_MDIO _CLK SGMII_RX_P SGMII _RX_M SGMII _TX_P SGMII _TX_M MDC 0.1uF SOP 0.1uF 0.1uF 0.1uF SDN SIP SIN Figure 2–36 SGMII + AR8033typical connection NOTE: 1) Route SGMII differential signals with a controlled impedance of 100 Ω; 2) Keep SGMII away from other sensitive signals such as analog circuits, RF circuits, audio signals, etc.
GM500-U1G_A Hardware Development Guide 3. Antenna Interface GM500-U1G_A antenna interface includes a main antenna, an Rx-diversity antenna and a GNSS antenna to improve receiving performance. The antenna interface has an impedance of 50Ω. 3.1. Pin Definition The main antenna and Rx-diversity antenna pins definition are shown below. Table 3-1Pin Definition ofAntenna Pin Name Pin NO.
GM500-U1G_A Hardware Development Guide Figure 3–1Reference Circuit of Antenna Interface The following picture is the reference of GNSS active antenna, VDD is its power, power supply should be designed by actual requirements. Figure 3–2Reference Circuit of GNSS Antenna NOTE: Keep a proper distance between main and diversity antenna to improve the receiving sensitivity.
GM500-U1G_A Hardware Development Guide 3.3. Reference PCB Layout of Antenna Please follow the following criterion in the process of antenna line PCB layout design: Make sure that the transmission line’s characteristic impedance is 50ohm; Keep line on the PCB as short as possible, since the antenna line loss shall be less than 0.
GM500-U1G_A Hardware Development Guide 3.5. Test Methods for Whole-Set Antenna OTA Figure below is the diagram of OTA test system of CTIA. The system is mainly composed of test chamber, high-precision positioning system and its controller, Windows based PC running test software and RF test instruments with automatic test program. The main RF instruments are integrated RF test equipment, Spectrum Analyzer, Network Analyzer.
GM500-U1G_A Hardware Development Guide 4. Electrical, Reliability and Radio Characteristics 4.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of module are listed in the following table: Table 4-1Absolute Maximum Ratings Parameter Min Max Unit VBAT 3.4 4.2 V Peak current of VBAT 0 2 A Voltage at digital pin -0.3 2.1 V Voltage at ADC1 0.05 4.15 V Voltage at ADC2 0.05 4.15 V 4.2.
GM500-U1G_A Hardware Development Guide Table 4-5 Averaged working current [1] Parameter Condition Typical Value（Bandwidth=10MHz） Unit LTE LTE FDD Band 2, Pout=23dBm 575 mA LTE FDD Band 4, Pout=23dBm 530 mA LTE FDD Band 5 ,Pout=23dBm 610 mA LTE FDD Band 12,Pout=23dBm 630 mA LTE FDD Band 13,Pout=23dBm 720 mA LTE FDD Band 17, Pout=23dBm 600 mA LTE FDD Band 25, Pout=23dBm 650 mA LTE FDD Band 26, Pout=23dBm 700 mA Table 4-6 Averaged working current [2] Parameter Condition Typical Va
GM500-U1G_A Hardware Development Guide LTE FDD Band 17 -97 dBm -94 dBm / LTE FDD Band 25 -97 dBm -94 dBm -91 dBm LTE FDD Band 26 -98 dBm -95 dBm / Table 4-9 Conducted RF Receiving Sensitivity Typical Value [2] Band Sensitivity WCDMA Band 2 -104.7 dBm WCDMA Band 5 -104.7 dBm 4.5. GNSS Technical Parameters The following table shows the GNSS technical parameters of GM500-U1G_A module. Table 4-10GNSS Technical Parameters GNSS (GNSS/GLONASS) Technical specification GNSS Frequency 1575.42±1.
GM500-U1G_A Hardware Development Guide 5. Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm. 5.1.
GM500-U1G_A Hardware Development Guide Figure 5–2GM500-U1G_A Bottom Dimensions (perspectiveview) Note: The diameter of test point is 1mm. 5.2.
GM500-U1G_A Hardware Development Guide Figure 5–3 Recommended Footprint (perspectiveview) NOTE: Keep out the area below the test point (blue area on the above figure) in the host PCB. In order to maintain the module, keep about 3mm between the module and other components in the host PCB.
GM500-U1G_A Hardware Development Guide 6. Related Test & Test Standard 6.1. Testing Reference The related tests of MODULE comply with the IEC standard, including the equipment running under high/low temperature, storage under high/low temperature, temperature shock and EMC. Table 6-1 is the list of testing standard, which includes the related testing standards for MODULE.
GM500-U1G_A Hardware Development Guide Normal working condition -30°C 75°C All the indexes are good. Extreme working condition -40~ -30°C 75~85°C Some indexes become poorer.
GM500-U1G_A Hardware Development Guide 7. SMT Process and Baking Guide This chapter describes module’s storage, PAD design, SMT process parameters, baking requirements, etc., and it is applicable for the process guide to second-level assembly of LCC encapsulation module. 7.1. Storage Requirements Storage conditions: temperature<40℃, relative humidity<90% (RH), 12 months weld ability guaranteed under this circumstances of excellent sealing package.
GM500-U1G_A Hardware Development Guide G≥0.5mm Drill holes at 100% scale in the direction of width; extend 0.3mm outward in the direction of length Contract 0.05~0.1mm in the G＜0.5mm direction of width; Contract 0.05~0.1mm inward in the direction of length, extend 0.5mm outward in the direction of length. 0.1mm 0.1mm 0.5mm Steel mesh opening Module PAD on PCB 0.1mm Figure 7–1 Module Board’s Steel Mesh Diagram 7.3.3.
GM500-U1G_A Hardware Development Guide The following picture is the tape reel specific dimension for your reference: A: Whole dimension: B: Detailed dimension: Figure 7–3 Tape Reel Dimension 3） Mounting Pressure: In order to ensure a good contact between the module and the solder paste on main board, the pressure of placing the module board on main board should be 2-5N according to our experiences. Different modules have different numbers of pads, therefore the pressure selected are different.
GM500-U1G_A Hardware Development Guide Temperature drop rate: －2〜－4℃/S NOTE: The test board of furnace temperature must be the main board with the module board mounted on, and there must be testing points at the position of module board. Figure 7–4Module Furnace Temperature Curve Reference Diagram 7.3.5. Reflow method If the main board used by customers is a double-sided board, it is recommended to mount the module board at the second time.
GM500-U1G_A Hardware Development Guide WARNING: The product’s transportation, storage and processing must conform to IPC/JEDEC J-STD-033. 7.4.2. Baking device and operation procedure Baking device: Any oven where the temperature can rise up to 125°C or above. Precautions regarding baking: during the baking process, the modules should be put in the high-temperature resistant pallet flatly and slightly to avoid the collisions and frictions between the modules.
GM500-U1G_A Hardware Development Guide Manual Information to the End User The OEM integrator has to be aware not to provide information to the end user regarding how to install or remove this RF module in the user’s manual of the end product which integrates this module. The end user manual shall include all required regulatory information/warning as show in this manual. Federal Communication Commission Interference Statement This device complies with Part 15 of the FCC Rules.
GM500-U1G_A Hardware Development Guide This device is intended only for OEM integrators under the following conditions: (For module device use) 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and and the maximum antenna gain allowed for use with this device is 3 dBi. 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required.
