Doc. No. MV-S109936-00, Rev. A February 3, 2015, 1.
n Co & g lo b al N giz r rk Li gh tin 88MW300/302 Datasheet *G o Document Conventions 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two -i7 2 hp 4v 3 Note: Provides related information or information of special importance. a g1 2 l8 Caution: Indicates potential damage to hardware or software, or loss of data. blg w kc 18 9 Warning: Indicates a risk of personal injury. 8 hg a yp 7 Doc Status: 1.
n Co & g gh tin lo b al N rk Li giz r *G o -i7 2 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two 88MW300/302 WLAN Microcontroller Datasheet hp 4v 3 a g1 2 l8 blg w PRODUCT OVERVIEW az c & g tin gh Li 2f rk The SoC provides a full array of peripheral interfaces including SSP/SPI/I2S (3x), UART (3x), I2C (2x), General Purpose Timers and PWM, ADC, DAC, Analog Comparator, and GPIOs.
n Co & g lo b al N giz r rk Li gh tin 88MW300/302 Datasheet o -i7 2 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two *G Figure 1: Block Diagram hp 4v 3 a g1 2 88MW300/302 l8 blg w Code RAM1 S1 Data RAM0 S2 Data RAM1 S3 az M4 DAC I2C ACOMP PMU 4k SRAM GPIO Timer/PWM X2/12 Digital Analog I/O Direct Conversion WLAN RF 1x1 SISO nt ro Co & g 802.11 Baseband (DSSS/OFDM, 1x1 SISO) PA 2.
n Co & g lo b al N tin Package gh Signal Diagram rk Li giz r 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two hp Package a g1 2 l8 Signal Diagram blg w o -i7 2 1.
Doc. No. MV-S109936-00 Rev. A 3 4 5 GPIO_2 GPIO_3 VDDIO_0 GPIO_1 61 62 64 88MW300 66 20 67 68 19 18 1. Connect pin 17 to ground.
February 3, 2015, 1.00 GPIO_4 GPIO_5 GPIO_6 GPIO_7 80 81 1. Connect pin 22 to ground.
NA UT l HO D IO N Copyright © 2015 Marvell February 3, 2015, 1.00 OR yp m xa Co & In c . nt ro Note: QFN package uses Epad size Option #3 only. See Section 22.4, Package Thermal Conditions, on page 315 for electrical specifications. See Section 23.2, Package Marking, on page 336 for package marking. -U n p AL 1u y Figure 5: Mechanical Drawing—68-Pin QFN TI E vw i Document Classification: Proprietary n Mechanical Drawing—68-Pin QFN EN l l8 1.3.
ID EN TI NA UT l IO HO Document Classification: Proprietary Doc. No. MV-S109936-00 Rev. A n Page 45 OR yp N n D E vw i l8 p m xa In c . nt ro L Note: QFN package uses Epad size Option #3 only. See Section 22.4, Package Thermal Conditions, on page 315 for electrical specifications. See Section 23.2, Package Marking, on page 336 for package marking. -U l 1u y AL cm CONFIDENTIAL cm Figure 6: Mechanical Drawing—88-Pin QFN CO NF 8 v cy February 3, 2015, 1.
n Co & g lo b al N giz r Pin Description 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two Pin Types P i n Ty p e Description l8 blg w Digital input kc 18 9 O 8 hg a A, I Analog input A, O Analog output NC No connect DNC Do not connect PWR Power Ground Ground & g tin gh am dr x 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two rk
n Co & g lo b al N tin Package gh Pin Description giz r Li rk USB 2.0 OTG Interface1 *G o -i7 2 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two Table 5: hp Ty p e Supply Description USB_VBUS A, I/O USB_AVDD33 USB VBUS Selection Input In Device Mode Unused in host mode; I/O for OTG mode to supply +5V@10mA during session negotiation.
n Co & g lo b al N giz r rk Li gh tin 88MW300/302 Datasheet UART Interface1 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two Signal Name Ty p e Supply D e s c r i p t io n -- UART0_RTSn O VDDIO_3 UART 0 RTSn (active low) UART0_TXD O VDDIO_3 UART 0 TXD I VDDIO_0 UART 1 CTSn (active low) O VDDIO_0 UART 1 RTSn (active low) yp 7 VDDIO_0 UART 1 TXD VDDIO_0 UART 1 RXD GPIO_27 l8 blg w kc 18 9 hp 4v 3
n Co & g gh tin lo b al N giz r Li D e s c ri p ti o n GPT0_CH0 I/O VDDIO_0 General Purpose Timer 0, Channel 0 GPT0_CH1 I/O VDDIO_0 General Purpose Timer 0, Channel 1 GPT0_CH2 I/O VDDIO_0 General Purpose Timer 0, Channel 2 I/O VDDIO_0 General Purpose Timer 0, Channel 3 I/O VDDIO_0 General Purpose Timer 0, Channel 4 VDDIO_0 General Purpose Timer 0, Channel 5 VDDIO_3 General Purpose Timer 0, Clock Input GPT0_CH5 8 az GPT0_CLKIN I GPIO_28 GPT1_CH0 I/O VDDIO_2 GPIO_29 GPT1_C
n Co & g lo b al N giz r rk Li gh tin 88MW300/302 Datasheet GPT Interface1 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two 68-Pin Signal Name Ty p e Supply D e s c ri p ti o n -- GPT3_CH4 I/O VDDIO_1 General Purpose Timer 3, Channel 4 GPT3_CH5 I/O VDDIO_3 General Purpose Timer 3, Channel 5 I VDDIO_3 General Purpose Timer 2, Clock Input 4v 3 GPIO_34 -- a l8 hp GPIO_21 GPIO_39 blg w o -i7 2 8 8 -P
n Co & g lo b al N tin Package gh Pin Description giz r Li rk SSP Interface1 (Continued) 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two Ty p e Supply Description -- SSP1_TXD O VDDIO_3 SSP 1 TXD SSP1_RXD I VDDIO_3 SSP 1 RXD I/O VDDIO_3 SSP 1 Serial Clock I/O VDDIO_3 SSP 1 Frame Indicator yp 7 VDDIO_3 SSP 1 TXD VDDIO_3 SSP 1 RXD l8 blg w kc 18 9 hp GPIO_39 Pin Name 4v 3 GPIO_38 6 8 -P i n a
n Co & g lo b al N giz r rk Li gh tin 88MW300/302 Datasheet I2C Interface1 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two Pin Name Ty p e Supply D e s c r i p t io n I2C0_SDA I/O VDDIO_0 I2C 0 SDA I/O VDDIO_0 I2C 0 SCL I/O VDDIO_0 I2C 1 SDA I/O VDDIO_0 I2C 1 SCL l8 GPIO_5 GPIO_8 blg w I2C0_SCL I2C1_SDA GPIO_10 I2C1_SCL nt ro kc 18 9 GPIO_6 GPIO_9 8 hg a az yp 7 hp 4v 3 GPIO_4 GPIO_7 68-Pi
n Co & g lo b al N tin Package gh Pin Description rk Li giz r *G o Table 11: GPIO Interface 1 2 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two -i7 2 P i n /S ig n a l N a m e Type S u p p ly D e s c ri p ti o n 1 GPIO_0 I/O VDDIO_0 General Purpose I/O 0 GPT0_CH0 I/O General Purpose Timer 0, Channel 0 I UART 0 CTSn (active low) I/O SSP 0 Serial Clock a g1 2 hp 1 68-Pin 4v 3 8 8 -P in l8 blg w U
n Co & g lo b al N giz r rk Li gh tin 88MW300/302 Datasheet *G o Table 11: GPIO Interface 1 (Continued)2 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two -i7 2 68-Pin hp 4v 3 8 8 -P in P i n /S ig n a l N a m e Type S u p p ly D e s c ri p ti o n GPIO_6 I/O VDDIO_0 General Purpose I/O 6 a l8 blg w TDO kc 8 g1 2 8 18 9 I2C1_SDA O JTAG Test Data I/O I2C 1 SDA 8 GPIO_8 I/O SSP2_TXD I2C1_SDA 12
n Co & g lo b al N tin Package gh Pin Description rk Li giz r *G o Table 11: GPIO Interface 1 (Continued)2 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two -i7 2 P i n /S ig n a l N a m e Type S u p p ly D e s c ri p ti o n -- GPIO_11 I/O VDDIO_0 General Purpose I/O 11 GPT2_CH0 I/O General Purpose Timer 2, Channel 0 I UART 1 CTSn (active low) I/O SSP 1 Serial Clock a g1 2 hp 13 68-Pin 4v 3 8 8 -P i
n Co & g lo b al N giz r rk Li gh tin 88MW300/302 Datasheet Type S u p p ly D e s c ri p ti o n -- GPIO_17 I/O VDDIO_1 General Purpose I/O 17 GPT3_CH0 I/O General Purpose Timer 3, Channel 0 I/O I2C 1 SCL kc 18 9 8 I/O az yp 7 GPIO_18 hg a GPT3_CH1 VDDIO_1 General Purpose I/O 18 I/O General Purpose Timer 3, Channel 1 I2C 1 SDA I2C1_SDA I/O SSP1_CLK I/O GPIO_19 I/O GPT3_CH2 I/O General Purpose Timer 3, Channel 2 I2C1_SCL I/O I2C 1 SDA I/O SSP 1 Frame Indicator m
n Co & g lo b al N tin Package gh Pin Description rk Li giz r *G o Table 11: GPIO Interface 1 (Continued)2 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two -i7 2 P i n /S ig n a l N a m e Type S u p p ly D e s c ri p ti o n 37 GPIO_23 I/O VDDIO_ AON General Purpose I/O 23 UART0_CTSn I UART 0 CTSn (active low) I Wake-Up 1 I LDO18 Comparator Input, Positive Positive input to LDO18 comparator.
n Co & g lo b al N giz r rk Li gh tin 88MW300/302 Datasheet *G o Table 11: GPIO Interface 1 (Continued)2 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two -i7 2 68-Pin hp 4v 3 8 8 -P in P i n /S ig n a l N a m e Type S u p p ly D e s c ri p ti o n GPIO_29 I/O VDDIO_2 General Purpose I/O 29 a I2C 0 SCL I/O General Purpose Timer 1, Channel 1 GPT1_CH2 I/O UART0_RTSn vc yp SSP0_FRM 46 GPIO_32 wi am 1u
n Co & g lo b al N tin Package gh Pin Description rk Li giz r *G o Table 11: GPIO Interface 1 (Continued)2 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two -i7 2 68-Pin hp 4v 3 8 8 -P in P i n /S ig n a l N a m e Type S u p p ly D e s c ri p ti o n GPIO_34 I/O VDDIO_3 General Purpose I/O 34 a I/O kc 18 9 8 I/O az GPIO_35 yp 7 GPT0_CLKIN VDDIO_3 I General Purpose I/O 35 General Purpose Timer 0, Cl
n Co & g lo b al N giz r o 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two -i7 2 P i n /S ig n a l N a m e Type S u p p ly D e s c ri p ti o n 55 GPIO_40 I/O VDDIO_3 General Purpose I/O 40 ADC_DAC_TRIGGER0 I ADC/DAC External Trigger 0 O ACOMP0 GPIO Output ACOMP0 output synchronous or asynchronous level signals. O ACOMP1 GPIO Output ACOMP1 output synchronous or asynchronous level signals.
n Co & g lo b al N tin Package gh Pin Description o 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two -i7 2 P i n /S ig n a l N a m e Type S u p p ly D e s c ri p ti o n 59 GPIO_43 I/O VDDIO_3 General Purpose I/O 43 ADC0_1 / ACOMP1 / TS_INN / DACB / VOICE_N A, I ADC0 Channel 1 ACOMP0 Channel 1 ACOMP1 Channel 1 Temperature sensor remote sensing negative input Voice sensing negative input O UART 1 RTSn (active low)
n Co & g lo b al N giz r rk Li gh tin 88MW300/302 Datasheet 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two Type S u p p ly D e s c ri p ti o n 63 GPIO_47 I/O VDDIO_3 General Purpose I/O 47 ADC0_5 / ACOMP5 A, I ADC0 Channel 5 ACOMP0 Channel 5 ACOMP1 Channel 5 O UART 2 RTSn (active low) I/O SSP 2 Frame Indicator SSP2_TXD O pv I/O ADC0_7 / ACOMP7 SSP2_RXD SSP 2 TXD VDDIO_3 General Purpose I/O 49 A, I A
n Co & g lo b al N tin Package gh Pin Description rk Li giz r 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two D e s c ri p t i o n XTAL_IN A, I AVDD18 Crystal Oscillator Input A, O AVDD18 Crystal Oscillator Output Connect to ground when an external oscillator used. A, I VDDIO_AON 32.768 kHz Crystal Input A, O VDDIO_AON 32.
n Co & g lo b al N giz r ACOMP0_GPIO_OUT O VDDIO_3 blg w ACOMP0 GPIO Output ACOMP0 output synchronous or asynchronous level signals O VDDIO_3 ACOMP1 GPIO Output ACOMP1 output synchronous or asynchronous level signals I VDDIO_3 ADC/DAC External Trigger 0 O VDDIO_3 ACOMP Edge Pulse 0 Output pulse aligned with synchronized comparison result.
n Co & g lo b al N tin Package gh Pin Description 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two Pin Name Type S u p p ly Description ADC0_1 / ACOMP1 / TS_INN / DACB / VOICE_N A, I VDDIO_3 ADC0 Channel 1 ACOMP0 Channel 1 ACOMP1 Channel 1 Temperature sensor remote sensing negative input Voice sensing negative input a g1 2 hp 4v 3 A, I VDDIO_3 ADC0 Channel 0 ACOMP0 Channel 0 ACOMP1 Channel 0 Temperature sensor rem
n Co & g lo b al N giz r rk Li gh tin 88MW300/302 Datasheet *G o Table 16: Power and Ground 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two -i7 2 NOTE: See Section 22.2, Recommended Operating Conditions, on page 314 for ratings. 29 VDDIO_1 48 VDDIO_2 57 VDDIO_3 8 nt ro az yp 7 Co c l8v 53 m wi nc PWR 3.3V OTP Analog Power Supply -- USB_AVDD33 PWR 3.
n Co & g tin lo b al N gh Package giz r *G o 1.5 rk Li Configuration Pins Configuration Pins -i7 2 7a M zhg AR a8 VE 18 LL 9kc CO blg NF wl ID 8g1 EN 2a TI 4v AL 3h , U pND i72 ER og NDizr * A# Gl 12 oba 15 l N 02 e 08 two Table 17 shows the pins used as configuration inputs to set parameters following a reset. The definition of these pins changes immediately after reset to their usual function. To set a configuration bit to 0, attach a 100 kΩ resistor from the pin to ground.
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.
