Cinterion® ELS61-AUS Hardware Interface Description Version: DocId: 00.031 ELS61-AUS_HID_v00.031 M2M.GEMALTO.
Cinterion® ELS61-AUS Hardware Interface Description Page 2 of 102 2 Document Name: Cinterion® ELS61-AUS Hardware Interface Description Version: 00.031 Date: 2016-06-03 DocId: ELS61-AUS_HID_v00.031 Status Confidential / Preliminary GENERAL NOTE THE USE OF THE PRODUCT INCLUDING THE SOFTWARE AND DOCUMENTATION (THE "PRODUCT") IS SUBJECT TO THE RELEASE NOTE PROVIDED TOGETHER WITH PRODUCT. IN ANY EVENT THE PROVISIONS OF THE RELEASE NOTE SHALL PREVAIL.
Cinterion® ELS61-AUS Hardware Interface Description Page 3 of 102 Contents 102 Contents 1 Introduction ................................................................................................................. 9 1.1 Key Features at a Glance .................................................................................. 9 1.2 ELS61-AUS System Overview......................................................................... 12 1.3 Circuit Concept .................................................
Cinterion® ELS61-AUS Hardware Interface Description Page 4 of 102 Contents 102 3.2.2 3.3 3.4 3.5 3.6 3.7 3.8 4 Restart ELS61-AUS ............................................................................ 57 3.2.2.1 Restart ELS61-AUS via AT+CFUN Command.................... 57 3.2.2.2 Restart ELS61-AUS Using EMERG_RST........................... 58 3.2.3 Signal States after Startup .................................................................. 59 3.2.4 Turn off ELS61-AUS .......................
Cinterion® ELS61-AUS Hardware Interface Description Page 5 of 102 Contents 102 4.3.2 4.3.3 Shipping Materials .............................................................................. 85 4.3.2.1 Moisture Barrier Bag ........................................................... 85 4.3.2.2 Transportation Box .............................................................. 87 Trays ...................................................................................................
Cinterion® ELS61-AUS Hardware Interface Description Page 6 of 102 Tables 114 Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Pad assignments............................................................................................ 16 Signal properties .........................................
Cinterion® ELS61-AUS Hardware Interface Description Page 7 of 102 Figures 114 Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Fig
Cinterion® ELS61-AUS Hardware Interface Description Page 8 of 102 Figures 114 Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Moisture barrier bag (MBB) with imprint......................................................... Moisture Sensitivity Label .............................................................................. Humidity Indicator Card - HIC ........................................................................ Tray dimensions...................................................
Cinterion® ELS61-AUS Hardware Interface Description Page 9 of 102 1 Introduction 14 1 Introduction This document1 describes the hardware of the Cinterion® ELS61-AUS module. It helps you quickly retrieve interface specifications, electrical and mechanical details and information on the requirements to be considered for integrating further components. 1.
Cinterion® ELS61-AUS Hardware Interface Description Page 10 of 102 1.1 Key Features at a Glance 14 Feature Implementation SMS Point-to-point MT and MO Cell broadcast Text and PDU mode Storage: SIM card plus SMS locations in mobile equipment Software AT commands Hayes 3GPP TS 27.007, TS 27.005, Gemalto M2M AT commands for RIL compatibility Java™ Open Platform Java™ Open Platform with • Java™ profile IMP-NG & CLDC 1.
Cinterion® ELS61-AUS Hardware Interface Description Page 11 of 102 1.1 Key Features at a Glance 14 Feature Implementation GPIO interface 22 GPIO lines comprising: 13 lines shared with ASC0, ASC1 and SPI lines, with network status indication, PWM functionality, fast shutdown and pulse counter 9 GPIO lines not shared I2C interface Supports I2C serial interface SPI interface Serial peripheral interface, shared with GPIO lines Antenna interface pads 50Ω.
Cinterion® ELS61-AUS Hardware Interface Description Page 12 of 102 1.2 ELS61-AUS System Overview 14 1.
Cinterion® ELS61-AUS Hardware Interface Description Page 13 of 102 1.3 Circuit Concept 14 1.
Cinterion® ELS61-AUS Hardware Interface Description Page 14 of 102 1.
Cinterion® ELS61-AUS Hardware Interface Description Page 15 of 102 2 Interface Characteristics 52 2 Interface Characteristics ELS61-AUS is equipped with an SMT application interface that connects to the external application. The SMT application interface incorporates the various application interfaces as well as the RF antenna interface. 2.1 Application Interface 2.1.
Cinterion® ELS61-AUS Hardware Interface Description Page 16 of 102 2.1 Application Interface 52 Table 1: Pad assignments Pad no.
Cinterion® ELS61-AUS Hardware Interface Description Page 17 of 102 2.1 Application Interface 52 2.1.2 Signal Properties Table 2: Signal properties Function Signal name IO Signal form and level Comment Power supply BATT+BB BATT+RF I WCDMA activated: VImax = 4.5V VInorm = 4.0V VImin = 3.0V during Transmit active. Imax = 700mA during Tx Lines of BATT+ and GND must be connected in parallel for supply purposes because higher peak currents may occur. LTE activated: VImax = 4.5V VInorm = 4.
Cinterion® ELS61-AUS Hardware Interface Description Page 18 of 102 2.1 Application Interface 52 Table 2: Signal properties Function Signal name IO Signal form and level Comment Fast shutdown FST_SHDN I VILmax = 0.35V VIHmin = 1.30V VIHmax = 1.85V This line must be driven low. If unused keep line open. ~~|___|~~ low impulse width > 10ms Note that the fast shutdown line is originally available as GPIO line.
Cinterion® ELS61-AUS Hardware Interface Description Page 19 of 102 2.1 Application Interface 52 Table 2: Signal properties Function Signal name IO Signal form and level Comment Serial Interface ASC1 RXD1 O If unused keep line open. TXD1 I VOLmax = 0.25V at I = 1mA VOHmin = 1.55V at I = -1mA VOHmax = 1.85V RTS1 I CTS1 O CCIN I SIM card detection VILmax = 0.35V VIHmin = 1.30V VIHmax = 1.85V RI ≈ 110kΩ VIHmin = 1.45V at I = 15µA, VIHmax= 1.9V VILmax = 0.
Cinterion® ELS61-AUS Hardware Interface Description Page 20 of 102 2.1 Application Interface 52 Table 2: Signal properties Function Signal name 1.8V SIM CCRST Card Interface CCIO IO Signal form and level Comment O VOLmax = 0.25V at I = 1mA VOHmin = 1.45V at I = -1mA VOHmax = 1.90V Maximum cable length or copper track to SIM card holder should not exceed 100mm. I/O VILmax = 0.35V VIHmin = 1.25V VIHmax = 1.85V VOLmax = 0.25V at I = 1mA VOHmin = 1.50V at I = -1mA VOHmax = 1.
Cinterion® ELS61-AUS Hardware Interface Description Page 21 of 102 2.1 Application Interface 52 Table 2: Signal properties Function Signal name IO Signal form and level Comment GPIO interface GPIO1-GPIO3 IO If unused keep line open. GPIO4 IO VOLmax = 0.25V at I = 1mA VOHmin = 1.55V at I = -1mA VOHmax = 1.85V GPIO5 IO GPIO6 IO GPIO7 IO GPIO8 IO GPIO11GPIO15 IO GPIO16GPIO19 IO GPIO20GPIO23 IO GPIO24 IO Status LED LED PWM O PWM1 O PWM2 O VILmax = 0.35V VIHmin = 1.
Cinterion® ELS61-AUS Hardware Interface Description Page 22 of 102 2.1 Application Interface 52 2.1.2.1 Absolute Maximum Ratings The absolute maximum ratings stated in Table 3 are stress ratings under any conditions. Stresses beyond any of these limits will cause permanent damage to ELS61-AUS. Table 3: Absolute maximum ratings Parameter Min Max Unit Supply voltage BATT+BB, BATT+RF -0.5 +5.5 V Voltage at all digital lines in Power Down mode -0.3 +0.
Cinterion® ELS61-AUS Hardware Interface Description Page 23 of 102 2.1 Application Interface 52 2.1.3 USB Interface ELS61-AUS supports a USB 2.0 High Speed (480Mbit/s) device interface that is Full Speed (12Mbit/s) compliant. The USB interface is primarily intended for use as command and data interface and for downloading firmware. The external application is responsible for supplying the VUSB_IN line. This line is used for cable detection only.
Cinterion® ELS61-AUS Hardware Interface Description Page 24 of 102 2.1 Application Interface 52 2.1.3.1 Reducing Power Consumption While a USB connection is active, the module will never switch into SLEEP mode. Only if the USB interface is in Suspended state or Detached (i.e., VUSB_IN = 0) is the module able to switch into SLEEP mode thereby saving power.
Cinterion® ELS61-AUS Hardware Interface Description Page 25 of 102 2.1 Application Interface 52 2.1.4 Serial Interface ASC0 ELS61-AUS offers an 8-wire unbalanced, asynchronous modem interface ASC0 conforming to ITU-T V.24 protocol DCE signalling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit or inactive state). For electrical characteristics please refer to Table 2.
Cinterion® ELS61-AUS Hardware Interface Description Page 26 of 102 2.1 Application Interface 52 The following figure shows the startup behavior of the asynchronous serial interface ASC0.
Cinterion® ELS61-AUS Hardware Interface Description Page 27 of 102 2.1 Application Interface 52 2.1.5 Serial Interface ASC1 Four ELS61-AUS GPIO lines can be configured as ASC1 interface signals to provide a 4-wire unbalanced, asynchronous modem interface ASC1 conforming to ITU-T V.24 protocol DCE signalling. The electrical characteristics do not comply with ITU-T V.28. The significant levels are 0V (for low data bit or active state) and 1.8V (for high data bit or inactive state).
Cinterion® ELS61-AUS Hardware Interface Description Page 28 of 102 2.1 Application Interface 52 The following figure shows the startup behavior of the asynchronous serial interface ASC1. Power supply active Start up Reset state Firmware initialization Command interface initialization Interface active ON VCORE V180 EMERG_RST TXD1/GPIO17 PD RXD1/GPIO16 PD RTS1/GPIO18 PD CTS1/GPIO19 PD PD *) For pull-down values see Table 10. Figure 9: ASC1 startup behavior ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 29 of 102 2.1 Application Interface 52 2.1.6 UICC/SIM/USIM Interface ELS61-AUS has an integrated UICC/SIM/USIM interface compatible with the 3GPP 31.102 and ETSI 102 221. This is wired to the host interface in order to be connected to an external SIM card holder. Five pads on the SMT application interface are reserved for the SIM interface. The UICC/SIM/USIM interface supports 3V and 1.8V SIM cards.
Cinterion® ELS61-AUS Hardware Interface Description Page 30 of 102 2.1 Application Interface 52 The figure below shows a circuit to connect an external SIM card holder. V180 CCIN CCVCC SIM 220nF 1nF CCRST CCIO CCCLK Figure 10: External UICC/SIM/USIM card holder circuit The total cable length between the SMT application interface pads on ELS61-AUS and the pads of the external SIM card holder must not exceed 100mm in order to meet the specifications of 3GPP TS 51.
Cinterion® ELS61-AUS Hardware Interface Description Page 31 of 102 2.1 Application Interface 52 2.1.6.1 Enhanced ESD Protection for SIM Interface To optimize ESD protection for the SIM interface it is possible to add ESD diodes to the SIM interface lines as shown in the example given in Figure 11. The example was designed to meet ESD protection according ETSI EN 301 489-1/7: Contact discharge: ± 4kV, air discharge: ± 8kV.
Cinterion® ELS61-AUS Hardware Interface Description Page 32 of 102 2.1 Application Interface 52 2.1.7 RTC Backup The internal Real Time Clock of ELS61-AUS is supplied from a separate voltage regulator in the power supply component which is also active when ELS61-AUS is in Power Down mode and BATT+ is available. An alarm function is provided that allows to wake up ELS61-AUS without logging on to the UMTS network. In addition, you can use the VDDLP pad to backup the RTC from an external capacitor.
Cinterion® ELS61-AUS Hardware Interface Description Page 33 of 102 2.1 Application Interface 52 2.1.8 GPIO Interface ELS61-AUS offers a GPIO interface with 22 GPIO lines. The GPIO lines are shared with other interfaces or functions: Fast shutdown (see Section 2.1.13.4), status LED (see Section 2.1.13.1), the PWM functionality (see Section 2.1.11), an pulse counter (see Section 2.1.12), ASC0 (see Section 2.1.4), ASC1 (see Section 2.1.5), an SPI interface (see Section 2.1.10).
Cinterion® ELS61-AUS Hardware Interface Description Page 34 of 102 2.1 Application Interface 52 The following figure shows the startup behavior of the GPIO interface. With an active state of the ASC0 interface (i.e. CTS0 is at low level) the initialization of the GPIO interface lines is also finished.
Cinterion® ELS61-AUS Hardware Interface Description Page 35 of 102 2.1 Application Interface 52 2.1.9 I2C Interface I2C is a serial, 8-bit oriented data transfer bus for bit rates up to 400kbps in Fast mode. It consists of two lines, the serial data line I2CDAT and the serial clock line I2CCLK. The module acts as a single master device, e.g. the clock I2CCLK is driven by the module. I2CDAT is a bi-directional line.
Cinterion® ELS61-AUS Hardware Interface Description Page 36 of 102 2.1 Application Interface 52 The following figure shows the startup behavior of the I2C interface. With an active state of the ASC0 interface (i.e. CTS0 is at low level) the initialization of the I2C interface is also finished.
Cinterion® ELS61-AUS Hardware Interface Description Page 37 of 102 2.1 Application Interface 52 2.1.10 SPI Interface Four ELS61-AUS GPIO interface lines can be configured as Serial Peripheral Interface (SPI). The SPI is a synchronous serial interface for control and data transfer between ELS61-AUS and the external application. Only one application can be connected to the SPI and the interface supports only master mode. The transmission rates are up to 6.5Mbit/s.
Cinterion® ELS61-AUS Hardware Interface Description Page 38 of 102 2.1 Application Interface 52 2.1.11 PWM Interfaces The GPIO6 and GPIO7 interface lines can be configured as Pulse Width Modulation interface lines PWM1 and PWM2. The PWM interface lines can be used, for example, to connect buzzers. The PWM1 line is shared with GPIO7 and the PWM2 line is shared with GPIO6 (for GPIOs see Section 2.1.8). GPIO and PWM functionality are mutually exclusive.
Cinterion® ELS61-AUS Hardware Interface Description Page 39 of 102 2.1 Application Interface 52 2.1.13.2 Power Indication Circuit In Power Down mode the maximum voltage at any digital or analog interface line must not exceed +0.3V (see also Section 2.1.2.1). Exceeding this limit for any length of time might cause permanent damage to the module. It is therefore recommended to implement a power indication signal that reports the module’s power state and shows whether it is active or in Power Down mode.
Cinterion® ELS61-AUS Hardware Interface Description Page 40 of 102 2.1 Application Interface 52 2.1.13.4 Fast Shutdown The GPIO4 interface line can be configured as fast shutdown signal line FST_SHDN. The configured FST_SHDN line is an active low control signal and must be applied for at least 10 milliseconds. If unused this line can be left open because of a configured internal pull-up resistor. Before setting the FST_SHDN line to low, the ON signal should be set to low (see Figure 19).
Cinterion® ELS61-AUS Hardware Interface Description Page 41 of 102 2.2 RF Antenna Interface 52 2.2 RF Antenna Interface The ELS61-AUS UMT/LTE antenna interface comprises a UMTS/LTE main antenna as well as a UMTS/LTE Rx diversity antenna to improve signal reliability and quality1. The RF interface has an impedance of 50Ω. ELS61-AUS is capable of sustaining a total mismatch at the antenna line without any damage, even when transmitting at maximum RF power.
Cinterion® ELS61-AUS Hardware Interface Description Page 42 of 102 2.2 RF Antenna Interface 52 Table 8: RF Antenna interface UMTS/LTE (at operating temperature range1) Parameter Conditions RF Power @ ARP with 50Ω Load Min. Typical Max. Unit UMTS 2100 Band I +23.5 dBm UMTS 850 Band V +23.5 dBm UMTS 900 Band VIII +23.5 dBm 1. No active power reduction implemented- any deviations are hardware related. 2. Applies also to UMTS/LTE Rx diversity antenna. ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 43 of 102 2.2 RF Antenna Interface 52 2.2.2 Antenna Installation The antenna is connected by soldering the antenna pad (ANT_MAIN or ANT_DRX) and its neighboring ground pads (GND) directly to the application’s PCB. The antenna pads are the antenna reference points (ARP) for ELS61-AUS. All RF data specified throughout this document is related to the ARP.
Cinterion® ELS61-AUS Hardware Interface Description Page 44 of 102 2.2 RF Antenna Interface 52 2.2.3 2.2.3.1 RF Line Routing Design Line Arrangement Examples Several dedicated tools are available to calculate line arrangements for specific applications and PCB materials - for example from http://www.polarinstruments.com/ (commercial software) or from http://web.awrcorp.com/Usa/Products/Optional-Products/TX-Line/ (free software).
Cinterion® ELS61-AUS Hardware Interface Description Page 45 of 102 2.2 RF Antenna Interface 52 Micro-Stripline This section gives two line arrangement examples for micro-stripline. • Micro-Stripline on 1.0mm Standard FR4 2-Layer PCB The following two figures show examples with different values for D1 (ground strip separation). Application board Ground line Antenna line Ground line Figure 22: Micro-Stripline on 1.0mm standard FR4 2-layer PCB - example 1 ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 46 of 102 2.2 RF Antenna Interface 52 Application board Ground line Antenna line Ground line Figure 23: Micro-Stripline on 1.0mm Standard FR4 PCB - example 2 ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 47 of 102 2.2 RF Antenna Interface 52 • Micro-Stripline on 1.5mm Standard FR4 2-Layer PCB The following two figures show examples with different values for D1 (ground strip separation). Application board Ground line Antenna line Ground line Figure 24: Micro-Stripline on 1.5mm Standard FR4 PCB - example 1 ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 48 of 102 2.2 RF Antenna Interface 52 Application board Ground line Antenna line Ground line Figure 25: Micro-Stripline on 1.5mm Standard FR4 PCB - example 2 ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 49 of 102 2.2 RF Antenna Interface 52 2.2.3.2 Routing Example Interface to RF Connector Figure 26 shows the connection of the module‘s antenna pad with an application PCB‘s coaxial antenna connector. Please note that the ELS61-AUS bottom plane appears mirrored, since it is viewed from ELS61-AUS top side. By definition the top of customer's board shall mate with the bottom of the ELS61-AUS module.
Cinterion® ELS61-AUS Hardware Interface Description Page 50 of 102 2.3 Sample Application 52 2.3 Sample Application Figure 27 shows a typical example of how to integrate a ELS61-AUS module with an application. Usage of the various host interfaces depends on the desired features of the application. Because of the very low power consumption design, current flowing from any other source into the module circuit must be avoided, for example reverse current from high state external control lines.
Cinterion® ELS61-AUS Hardware Interface Description Page 51 of 102 2.3 Sample Application 52 Main antenna GND VDDLP ANT_MAIN For switch on circuit see Section 3.2.1.2 GND EMERG_RST ANT_DRX GND 100k RESET Diversity antenna GND ON VDDLP V180 PWR_IND BATT+RF VCORE 22k BATT+BB 150µF, Low ESR! 53 33pF 204 Power supply 100k 50µF, Low ESR! 4.7k 33pF ELS6x 100k Blocking** Blocking** 4 GPIO20...GPIO23 GPIO16...GPIO19/ ASC1/ SPI 4 ASC0 (including GPIO1...
Cinterion® ELS61-AUS Hardware Interface Description Page 52 of 102 2.3 Sample Application 52 2.3.1 Sample Level Conversion Circuit Depending on the micro controller used by an external application ELS61-AUS‘s digital input and output lines (i.e., ASC0, ASC1 and GPIO lines) may require level conversion. The following Figure 28 shows a sample circuit with recommended level shifters for an external application‘s micro controller (with VLOGIC between 3.0V...3.6V).
Cinterion® ELS61-AUS Hardware Interface Description Page 53 of 102 3 Operating Characteristics 73 3 Operating Characteristics 3.1 Operating Modes The table below briefly summarizes the various operating modes referred to throughout the document. Table 9: Overview of operating modes Mode Function Normal UMTS / HSPA / operation LTE SLEEP Power saving set automatically when no call is in progress and the USB connection is suspended by host or not present and no active communication via ASC0.
Cinterion® ELS61-AUS Hardware Interface Description Page 54 of 102 3.2 Power Up/Power Down Scenarios 73 3.2 Power Up/Power Down Scenarios In general, be sure not to turn on ELS61-AUS while it is beyond the safety limits of voltage and temperature stated in Section 2.1.2.1. ELS61-AUS immediately switches off after having started and detected these inappropriate conditions. In extreme cases this can cause permanent damage to the module. 3.2.
Cinterion® ELS61-AUS Hardware Interface Description Page 55 of 102 3.2 Power Up/Power Down Scenarios 73 IRML6401 3.8V 47µF,X5R 47µF,X5R 47µF,X5R 47µF,X5R C3 C4 C5 VBATT Module 10k R6 C2 100nF R1 100k C1 T2 C6 47µF,X5R VBATT_IN µcontroller R2 100k BC847 R3 100k ENABLE Place C2-C5 close to module T1 Figure 29: Sample circuit for applying power using an external µC VBATT Module 3.8V_IN TBD.
Cinterion® ELS61-AUS Hardware Interface Description Page 56 of 102 3.2 Power Up/Power Down Scenarios 73 3.2.1.2 Switch on ELS61-AUS Using ON Signal When the operating voltage BATT+ is applied, ELS61-AUS can be switched on by means of the ON signal. The ON signal is an edge triggered signal and only allows the input voltage level of the VDDLP signal. The module starts into normal mode on detecting the rising edge of the ON signal.
Cinterion® ELS61-AUS Hardware Interface Description Page 57 of 102 3.2 Power Up/Power Down Scenarios 73 Please note that the ON signal is an edge triggered signal. This implies that a milli-second high pulse on the signal line suffices to almost immediately switch on the module, as shown in Figure 32. After module startup the ON signal should always be set to low to prevent possible back powering at this pad.
Cinterion® ELS61-AUS Hardware Interface Description Page 58 of 102 3.2 Power Up/Power Down Scenarios 73 3.2.2.2 Restart ELS61-AUS Using EMERG_RST The EMERG_RST signal is internally connected to the central baseband processor. A low level for more than 10ms sets the processor and with it all the other signal pads to their respective reset state. The reset state is described in Section 3.2.3 as well as in the figures showing the startup behavior of an interface. After releasing the EMERG-RST line, i.e.
Cinterion® ELS61-AUS Hardware Interface Description Page 59 of 102 3.2 Power Up/Power Down Scenarios 73 3.2.3 Signal States after Startup Table 10 lists the states each interface signal passes through during reset phase and the first firmware initialization. For further firmware startup initializations the values may differ because of different GPIO line configurations. The reset state is reached with the rising edge of the EMERG_RST signal - either after a normal module startup (see Section 3.2.1.
Cinterion® ELS61-AUS Hardware Interface Description Page 60 of 102 3.2 Power Up/Power Down Scenarios 73 3.2.4 Turn off ELS61-AUS To switch the module off the following procedures may be used: • Software controlled shutdown procedure: Software controlled by sending an AT command over the serial application interface. See Section 3.2.4.1. • Hardware controlled shutdown procedure: Hardware controlled by disconnecting the module‘s power supply lines BATT+ (see Section 3.2.1.1).
Cinterion® ELS61-AUS Hardware Interface Description Page 61 of 102 3.2 Power Up/Power Down Scenarios 73 3.2.5 Automatic Shutdown Automatic shutdown takes effect if the following event occurs: • ELS61-AUS board is exceeding the critical limits of overtemperature or undertemperature (see Section 3.2.5.1) • Undervoltage or overvoltage is detected (see Section 3.2.5.2 and Section 3.2.5.3) The automatic shutdown procedure is equivalent to the power-down initiated with an AT command, i.e.
Cinterion® ELS61-AUS Hardware Interface Description Page 62 of 102 3.2 Power Up/Power Down Scenarios 73 3.2.5.2 Undervoltage Shutdown The undervoltage shutdown threshold is the specified minimum supply voltage VBATT+ given in Table 2. When the average supply voltage measured by ELS61-AUS approaches the undervoltage shutdown threshold (i.e., 0.
Cinterion® ELS61-AUS Hardware Interface Description Page 63 of 102 3.3 Power Saving 73 3.3 Power Saving ELS61-AUS can be configured to control power consumption: • Using the AT command AT^SPOW it is possible to specify a so-called power saving mode for the module ( = 2; for details on the command see [1]). The module‘s UART interfaces (ASC0 and ASC1) are then deactivated and will only periodically be activated to be able to listen to network paging messages as described in Section 3.3.
Cinterion® ELS61-AUS Hardware Interface Description Page 64 of 102 3.3 Power Saving 73 Generally, power saving depends on the module’s application scenario and may differ from the above mentioned normal operation. The power saving interval may be shorter than 0.64 seconds or longer than 5.12 seconds. 3.3.2 Power Saving while Attached to LTE Networks The power saving possibilities while attached to an LTE network depend on the paging timing cycle of the base station. During normal LTE operation, i.e.
Cinterion® ELS61-AUS Hardware Interface Description Page 65 of 102 3.3 Power Saving 73 3.3.3 Wake-up via RTS0 RTS0 can be used to wake up ELS61-AUS from SLEEP mode configured with AT^SPOW. Assertion of RTS0 (i.e., toggle from inactive high to active low) serves as wake up event, thus allowing an external application to almost immediately terminate power saving. After RTS0 assertion, the CTS0 line signals module wake up, i.e., readiness of the AT command interface.
Cinterion® ELS61-AUS Hardware Interface Description Page 66 of 102 3.4 Power Supply 73 3.4 Power Supply ELS61-AUS needs to be connected to a power supply at the SMT application interface - 2 lines BATT+, and GND. There are two separate voltage domains for BATT+: • BATT+BB with a line mainly for the baseband power supply. • BATT+RF with a line for the UMTS/LTE power amplifier supply.
Cinterion® ELS61-AUS Hardware Interface Description Page 67 of 102 3.4 Power Supply 73 Table 13: Current consumption ratings (TBD) Description Conditions Typical rating Unit IVDDLP @ 1.8V OFF State supply current RTC backup @ BATT+ = 0V IBATT+1 Power Down OFF State supply current (i.e.
Cinterion® ELS61-AUS Hardware Interface Description Page 68 of 102 3.4 Power Supply 73 3.4.2 Measuring the Supply Voltage (VBATT+) To measure the supply voltage VBATT+ it is possible to define two reference points GND and BATT+. GND should be the module’s shielding, while BATT+ should be a test pad on the external application the module is mounted on.
Cinterion® ELS61-AUS Hardware Interface Description Page 69 of 102 3.5 Operating Temperatures 73 3.5 Operating Temperatures Please note that the module’s lifetime, i.e., the MTTF (mean time to failure) may be reduced, if operated outside the extended temperature range. Table 14: Board temperature Parameter Normal operation 1 Min Typ Max Unit -30 +25 +85 °C +90 °C >+90 °C Extended operation -40 Automatic shutdown2 Temperature measured on ELS61-AUS board <-40 --- 1.
Cinterion® ELS61-AUS Hardware Interface Description Page 70 of 102 3.6 Electrostatic Discharge 73 3.6 Electrostatic Discharge The module is not protected against Electrostatic Discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any application that incorporates a ELS61-AUS module.
Cinterion® ELS61-AUS Hardware Interface Description Page 71 of 102 3.7 Blocking against RF on Interface Lines 73 3.7 Blocking against RF on Interface Lines To reduce EMI issues there are serial resistors, or capacitors to GND, implemented on the module for the ignition, emergency restart, and SIM interface lines (cp. Section 2.3). However, all other signal lines have no EMI measures on the module and there are no blocking measures at the module’s interface to an external application.
Cinterion® ELS61-AUS Hardware Interface Description Page 72 of 102 3.7 Blocking against RF on Interface Lines 73 The following table lists for each signal line at the module‘s SMT application interface the EMI measures that may be implemented. Table 16: EMI measures on the application interface Signal name EMI measures A CCIN B C x Remark D E x CCRST x CCIO x CCCLK x The external capacitor should be not higher than 10pF. The value of the capacitor depends on the external application.
Cinterion® ELS61-AUS Hardware Interface Description Page 73 of 102 3.8 Reliability Characteristics 73 3.8 Reliability Characteristics The test conditions stated below are an extract of the complete test specifications.
Cinterion® ELS61-AUS Hardware Interface Description Page 74 of 102 4 Mechanical Dimensions, Mounting and Packaging 88 4 Mechanical Dimensions, Mounting and Packaging 4.1 Mechanical Dimensions of ELS61-AUS Figure 41 shows the top and bottom view of ELS61-AUS and provides an overview of the board's mechanical dimensions. For further details see Figure 42. Product label Top view Bottom view Figure 41: ELS61-AUS– top and bottom view ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 75 of 102 4.1 Mechanical Dimensions of ELS61-AUS 88 Figure 42: Dimensions of ELS61-AUS (all dimensions in mm) ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 76 of 102 4.2 Mounting ELS61-AUS onto the Application Platform 88 4.2 Mounting ELS61-AUS onto the Application Platform This section describes how to mount ELS61-AUS onto the PCBs, including land pattern and stencil design, board-level characterization, soldering conditions, durability and mechanical handling. For more information on issues related to SMT module integration see also [3].
Cinterion® ELS61-AUS Hardware Interface Description Page 77 of 102 4.2 Mounting ELS61-AUS onto the Application Platform 88 Figure 44: Recommended design for 110µm micron thick stencil (top view) Figure 45: Recommended design for 150µm micron thick stencil (top view) ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 78 of 102 4.2 Mounting ELS61-AUS onto the Application Platform 88 4.2.1.2 Board Level Characterization Board level characterization issues should also be taken into account if devising an SMT process. Characterization tests should attempt to optimize the SMT process with regard to board level reliability.
Cinterion® ELS61-AUS Hardware Interface Description Page 79 of 102 4.2 Mounting ELS61-AUS onto the Application Platform 88 4.2.3 Soldering Conditions and Temperature 4.2.3.
Cinterion® ELS61-AUS Hardware Interface Description Page 80 of 102 4.2 Mounting ELS61-AUS onto the Application Platform 88 4.2.3.2 Maximum Temperature and Duration The following limits are recommended for the SMT board-level soldering process to attach the module: • A maximum module temperature of 240°C. This specifies the temperature as measured at the module’s top side. • A maximum duration of 15 seconds at this temperature.
Cinterion® ELS61-AUS Hardware Interface Description Page 81 of 102 4.2 Mounting ELS61-AUS onto the Application Platform 88 4.2.4 Durability and Mechanical Handling 4.2.4.1 Storage Conditions ELS61-AUS modules, as delivered in tape and reel carriers, must be stored in sealed, moisture barrier anti-static bags. The conditions stated below are only valid for modules in their original packed state in weather protected, non-temperature-controlled storage locations.
Cinterion® ELS61-AUS Hardware Interface Description Page 82 of 102 4.2 Mounting ELS61-AUS onto the Application Platform 88 4.2.4.2 Processing Life ELS61-AUS must be soldered to an application within 72 hours after opening the moisture barrier bag (MBB) it was stored in. As specified in the IPC/JEDEC J-STD-033 Standard, the manufacturing site processing the modules should have ambient temperatures below 30°C and a relative humidity below 60%. 4.2.4.
Cinterion® ELS61-AUS Hardware Interface Description Page 83 of 102 4.3 Packaging 88 4.3 Packaging 4.3.1 Tape and Reel The single-feed tape carrier for ELS61-AUS is illustrated in Figure 47. The figure also shows the proper part orientation. The tape width is 44mm and the ELS61-AUS modules are placed on the tape with a 32-mm pitch. The reels are 330mm in diameter with a core diameter of 100mm. Each reel contains 500 modules. 4.3.1.
Cinterion® ELS61-AUS Hardware Interface Description Page 84 of 102 4.3 Packaging 88 4.3.1.2 Barcode Label A barcode label provides detailed information on the tape and its contents. It is attached to the reel. Barcode label Figure 49: Barcode label on tape reel ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 85 of 102 4.3 Packaging 88 4.3.2 Shipping Materials ELS61-AUS is distributed in tape and reel carriers. The tape and reel carriers used to distribute ELS61-AUS are packed as described below, including the following required shipping materials: • Moisture barrier bag, including desiccant and humidity indicator card • Transportation box 4.3.2.
Cinterion® ELS61-AUS Hardware Interface Description Page 86 of 102 4.3 Packaging 88 Figure 51: Moisture Sensitivity Label ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 87 of 102 4.3 Packaging 88 MBBs contain one or more desiccant pouches to absorb moisture that may be in the bag. The humidity indicator card described below should be used to determine whether the enclosed components have absorbed an excessive amount of moisture. The desiccant pouches should not be baked or reused once removed from the MBB.
Cinterion® ELS61-AUS Hardware Interface Description Page 88 of 102 4.3 Packaging 88 4.3.3 Trays If small module quantities are required, e.g., for test and evaluation purposes, ELS61-AUS may be distributed in trays (for dimensions see Figure 53). The small quantity trays are an alternative to the single-feed tape carriers normally used. However, the trays are not designed for machine processing.
Cinterion® ELS61-AUS Hardware Interface Description Page 89 of 102 5 Regulatory and Type Approval Information 94 5 Regulatory and Type Approval Information 5.1 Directives and Standards ELS61-AUS is designed to comply with the directives and standards listed below.
Cinterion® ELS61-AUS Hardware Interface Description Page 90 of 102 5.1 Directives and Standards 94 EN 301 908-13 v5.2.1 Electromagnetic compatibility and Radio spectrum Matters (ERM); Base Stations (BS), Repeaters and User Equipment (UE) for IMT-2000 ThirdGeneration cellular networks; Part 13: Harmonized EN for IMT-2000, Evolved Universal Terrestrial Radio Access (E-UTRA) (UE) covering the essential requirements of article 3.2 of the R&TTE Directive EN 301 489-01 V1.9.
Cinterion® ELS61-AUS Hardware Interface Description Page 91 of 102 5.1 Directives and Standards 94 Table 24: Toxic or hazardous substances or elements with defined concentration limits ELS61-AUS_HID_v00.
Cinterion® ELS61-AUS Hardware Interface Description Page 92 of 102 5.2 SAR requirements specific to portable mobiles 94 5.2 SAR requirements specific to portable mobiles Mobile phones, PDAs or other portable transmitters and receivers incorporating a UMTS module must be in accordance with the guidelines for human exposure to radio frequency energy.
Cinterion® ELS61-AUS Hardware Interface Description Page 93 of 102 5.3 Reference Equipment for Type Approval 94 5.
Cinterion® ELS61-AUS Hardware Interface Description Page 94 of 102 5.4 Compliance with FCC Rules and Regulations 94 5.4 Compliance with FCC Rules and Regulations The Equipment Authorization Certification for the Gemalto M2M reference application described in Section 5.
Cinterion® ELS61-AUS Hardware Interface Description Page 95 of 102 6 Document Information 99 6 Document Information 6.1 Revision History New document: "Cinterion® ELS61-AUS Hardware Interface Description" Version 00.031 Chapter What is new -- Initial document setup. 6.2 [1] [2] [3] [4] [5] Related Documents ELS61-AUS AT Command Set ELS61-AUS Release Note Application Note 48: SMT Module Integration Application Note 40: Thermal Solutions Universal Serial Bus Specification Revision 2.
Cinterion® ELS61-AUS Hardware Interface Description Page 96 of 102 6.3 Terms and Abbreviations 99 6.3 Terms and Abbreviations Abbreviation Description ADC Analog-to-digital converter AGC Automatic Gain Control ANSI American National Standards Institute ARFCN Absolute Radio Frequency Channel Number ARP Antenna Reference Point ASC0/ASC1 Asynchronous Controller.
Cinterion® ELS61-AUS Hardware Interface Description Page 97 of 102 6.
Cinterion® ELS61-AUS Hardware Interface Description Page 98 of 102 6.3 Terms and Abbreviations 99 Abbreviation Description RLS Radio Link Stability RMS Root Mean Square (value) RoHS Restriction of the use of certain hazardous substances in electrical and electronic equipment.
Cinterion® ELS61-AUS Hardware Interface Description Page 99 of 102 6.4 Safety Precaution Notes 99 6.4 Safety Precaution Notes The following safety precautions must be observed during all phases of the operation, usage, service or repair of any cellular terminal or mobile incorporating ELS61-AUS. Manufacturers of the cellular terminal are advised to convey the following safety information to users and operating personnel and to incorporate these guidelines into all manuals supplied with the product.
Cinterion® ELS61-AUS Hardware Interface Description Page 100 of 102 7 Appendix 101 7 Appendix 7.
Cinterion® ELS61-AUS Hardware Interface Description Page 101 of 102 7.1 List of Parts and Accessories 101 Table 26: Molex sales contacts (subject to change) Molex For further information please click: http://www.molex.com Molex Deutschland GmbH Otto-Hahn-Str. 1b 69190 Walldorf Germany Phone: +49-6227-3091-0 Fax: +49-6227-3091-8100 Email: mxgermany@molex.com American Headquarters Lisle, Illinois 60532 U.S.A.
About Gemalto Gemalto (Euronext NL0000400653 GTO) is the world leader in digital security with 2015 annual revenues of €3.1 billion and blue-chip customers in over 180 countries. Our 14,000+ employees operate out of 118 offices, 45 personalization and data centers, and 27 research and software development centers located in 49 countries. Gemalto develops secure embedded software and secure products which we design and personalize.
