GS1500M LOW-POWER WIRELESS SYSTEM-ON-CHIP WI-FI MODULE DATA SHEET USER'S MANUAL USER MANUAL P R ELI MI N AR Y R ELEAS E GainSpan Confidential Information Reference: GS1500M-DS Version: SP-0.
GS1500M DATA SHEET Information in this document is provided in connection with GainSpan products. No license, express or implied, to any intellectual property rights is granted by this document. GainSpan assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of GainSpan products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
GS1500M DATA SHEET Table of Contents 1 1.1 1.2 Overview ................................................................................................................................. 7 Document Overview........................................................................................................... 7 Product Overview ............................................................................................................... 7 2 Architecture ...............................................
GS1500M DATA SHEET 4.8.3 Motorola SPI, clock polarity SPO = 1, clock phase SPH = 0 ..................................... 33 4.8.4 Motorola SPI, clock polarity SPO = 1, clock phase SPH = 1 ..................................... 35 4.9 Electrostatic discharge (ESD) .......................................................................................... 36 5 5.1 Package and Layout Guidelines ............................................................................................
GS1500M DATA SHEET Figures Figure 2-1: GS1500M Block Diagram ........................................................................................................ 9 Figure 2-2: RTC Interface Diagram .......................................................................................................... 12 Figure 2-3: GS1500M System States ........................................................................................................
GS1500M DATA SHEET Tables Table 3-1: Signal Description .................................................................................................................... 22 Table 4-1: Absolute Maximum Ratings .................................................................................................... 24 Table 4-2: Operating Conditions ............................................................................................................... 24 Table 4-3: Internal 1.8V Regulator .............
GS1500M DATA SHEET 1 Overview 1.1 Document Overview the GS1500M Low Power module hardware specification. The GS1500M Tmodule providesdescribes a cost effective, low power, and flexible platform to add Wi-Fi® connectivity for HIS DOCUMENT embedded devices for a variety of applications, such as wireless sensors and thermostats. It combines ARM7-based processors with an RF transceiver, 802.
GS1500M DATA SHEET ► Interfaces: • • • • • • • • • • PCB or external antenna options. Two general-purpose SPI interfaces (each configurable as master or slave) for external sensors, memory, or external CPU interface; one interface may be configured as a high-speed Slave-only. Two multi-purpose UART interfaces. Up to 23 configure able general purpose I/Os. Single 3.3V supply option o I/O supply voltage 1.8 ~ 3.3V option One PWM output I2C master/slave interface.
GS1500M DATA SHEET 2 Architecture 2.1 G1500M Block Diagram Figure 2-1: GS1500M Block Diagram 2.2 Block Diagram Description 2.2.1 Overview GS1500M module is an integrated ultra low power Wi-Fi system-on-chip (SOC) that contains the following: • • The module includes: o a highly integrated IEEE 802.
GS1500M DATA SHEET low-power 10-bit ADC capable of running at up to 32 KSamples/sec., GPIO’s, and LED Drivers/GPIO with 20mA capabilities.
GS1500M DATA SHEET 2.2.5 Clock Circuitries The GS1500M architecture uses a low-power oscillator (i.e. 32 kHz) to provide a minimal subset of functions when the chip is in its low-power deep sleep mode, and a high-speed 44 MHz oscillator to provide clock signals for the processors, bus, and interfaces during active operation. Intermediate modes of operation, in which the 44 MHz oscillator is active but some modules are inactive, are obtained by gating the clock signal to different subsystems.
GS1500M DATA SHEET Figure 2-2: RTC Interface Diagram Resolution of the wake-up timer is one clock cycle, and, with onboard 32KHz. CLK, each 32bit effective register can provide up to 1.5 days worth of standby duration as the longest standby period. Polarity of the rtc_out1 pin is programmable. 2.2.5.3 Real Time Counter The Real Time Counter features: ► 48-bit length (with absolute duration dependent on the crystal frequency used). ► Low-power design.
GS1500M DATA SHEET 2.2.5.4.1 DC_DC_CNTL During Power-on-Reset (e.g. when the battery is connected), the dc_dc_cntl pin is held low; it goes high to indicate completion of RTC power-on-reset. This pin can be used as an enable into an external device such as voltage regulator. For more information, consult the GS1011 Peripheral and Register Description [2] and GS1011 IC data sheet [3] for detailed descriptions. 2.2.5.4.2 RTC_OUT1 The rtc_out1 signal can be disabled or driven by the Wake-up Counter 2.
GS1500M DATA SHEET ► Two clock design: • APB bus clock for bus interface and registers. • Serial input clock for core logic. ► Support of external EEPROM or other non-volatile memory. ► Programmable choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. ► Programmable control of the serial bit rate of the data transfer in serial-master mode of operation. ► Programmable phase and polarity of the bit rate clock.
GS1500M DATA SHEET ► Ignores CBUS addresses (an older ancestor of I C that used to share the I C bus). 2 2 ► Interrupt or polled mode operation. ► Combined interrupt line triggered by: • • • • • • • • Tx FIFO not FULL. Rx FIFO not EMPTY. Rx FIFO FULL (can be used to transfer data by host interface in bursts). Tx FIFO EMPTY (can be used to transfer data by host interface in bursts). Rx FIFO OVER RUN. Master mode to Slave Transfer Request. Slave Transmit Request.
GS1500M DATA SHEET 2.3.5 GPIO & LED Driver / GPIO The GPIO ports are referenced to VDDIO. Two GPIO pins called GPIO30_LED1 & GPO31_LED2 have the capability to sink/source 20 mA typical (VDDIO=3.3V) to connect to devices such as switch contacts or LEDs. I2C_DATA/GPIO8 & I2C_CLK/GPIO9 have the capability to sink/source 12 mA typical (VDDIO=3.3V). Other GPIO’s have the capability to sink/source 4 mA typical (VDDIO=3.3V). All inputs are capable of generating processor interrupts.
GS1500M DATA SHEET 2.4 System States Figure 2-8 shows the power management/clock states of the GS1500M system. Figure 2-3: GS1500M System States The system states of the GS1500M system are as follows: Power OFF: No power source connected to the system. Power Up: When supply voltage is stable and the RTC is powered up, and the system transitions from the Power OFF state to the Power Up state. In this state only the 32.768 kHz clock is running, and the RTC is powered directly by the battery or DC supply.
GS1500M DATA SHEET System Configuration: When a power-up is requested, the system transitions from the Power Up state to the System Configuration state. In this state, the WLAN CPU is released from reset by the RTC. The APP CPU remains in the reset state during System Configuration. The WLAN CPU then executes the required system configurations, releases the APP CPU from reset, and transitions to the Power-ON state.
GS1500M DATA SHEET 3 Pin-out and Signal Description 3.
GS1500M DATA SHEET 3.1.
GS1500M DATA SHEET Pins Name Voltage Domain Internal Bias after hardware reset Signal State Description 23 GPO19_44MHZ VDDIO Pull-down Digital Input Internal Clock Circuitry Test Point / General Purpose Input Output 24 PWM0 / GPIO10 VDDIO Pull-down Digital Output Pulse Width Modulator / General Purpose Input Output 25 I2C_CLK/GPIO9 VDDIO Pull-down (NOTE 4) Digital Input / Output Inter-Integrated Circuit Clock / General Purpose Input Output 26 I2C_DATA/GPIO8 VDDIO Pull-down (NOTE
GS1500M DATA SHEET Pins Name Voltage Domain Internal Bias after hardware reset Signal State Description 42 UART0_CTS / GPIO24 VDDIO Pull-down Digital Input Universal Asynchronous Receiver Transmitter 0 Clear to Send Input / General Purpose Input Output 43 GPO31_LED2 VDDIO Pull-down Digital Output Light Emitting Diode Driver / General Purpose Input Output 44 GPIO30_LED1 VDDIO Pull-down Digital Output Light Emitting Diode Driver / General Purpose Input Output 45 GPIO29 VDDIO Pull-d
GS1500M DATA SHEET Figure 3-2: Module pin connection diagram Note 1) For the noted pin configurations, please refer to data sheet power supply section. Note 2) If I2C interface is used, provide 2KOhm pull-ups, to VDDIO, for pins 25 and 26 (I2C_CLK and I2C_DATA). If not used, leave pins 25 and 26 as No Connects. Note 3) Connect to external HOST SPI (can be left as No Connects if not used).
GS1500M DATA SHEET 4 Electrical Characteristics 4.1 Absolute Maximum Ratings Conditions beyond those cited in Table 4-1 may cause permanent damage to the GS1500M, and must be avoided. Parameter Storage temperature RTC Power Supply I/O Supply voltage Single Supply Port Symbol TST Vbat VDDIO VIN_3V3 Minimum -55 -0.5 -0.5 2.7 Typical 3.3 Maximum +125 4.0 4.0 4.0 Unit ºC V V V Table 4-1: Absolute Maximum Ratings NOTE: For limitations on state voltage ranges, please consult section 2.6.1 Power supply.
GS1500M DATA SHEET 4.4 I/O DC Specifications 4.4.1 Digital Input Specifications Parameter Input Low Voltage Symbol VIL Input High Voltage VIH Minimum -0.3 0.8* VDDIO Typical Maximum 0.25* VDDIO Unit V VDDIO V Note Table 4-4: Digital Input Parameters 4.4.2 Digital Output Specification Parameter Output Low Voltage Symbol Mininum VOL 0 Output High Voltage Output rise time @ VDDIO=3.3V Output fall time @ VDDIO=3.3V Typical 1.3 V Maximum Unit Note 0.
GS1500M DATA SHEET Parameter Output Low Voltage Symbol Mininum VOL Output High Voltage VOH Output rise time @ VDDIO =3.3V Output fall time @ VDDIO = 3.3V Input rise time Input fall time Typical Maximum Unit 0 0.4 V 1.3 V VDDIO V tToLH 7 ns tToHL 7 ns tTiLH tTiHL 7 7 ns ns Note With 4/12/20 mA load With 4/12/20 mA load With 2/6/10 mA load With 4/12/20 mA load, 33 pF With 4/12/20 mA load, 33 pF Table 4-6: I/O Digital Parameters 4.4.
GS1500M DATA SHEET 4.5 Power Consumption (estimated) Test Conditions: VDD33=VDDIO=Vbat=3.3V Temp=25ºC System state Deep Sleep Receive (GS1500M; -xx dBm RX sens. @ xxMbps. Transmit (GS1500M; xx dBm at antenna port @ 11n HT20 MCS7) Current (Typ.) 3mA TBD TBD Table 4-9: Power Consumption in Different States 4.6 Radio Parameters Test Conditions: VIN_3V3=VDDIO=Vbat=3.
GS1500M DATA SHEET 4.7 ADC Parameters Test Conditions: VIN_3V3=VDDIO=Vbat=3.3V Temp=25ºC Parameter ADC Resolution ADC Sample Freq ADC input Clock Freq Minimum 1.024 Typical 10 - Maximum 31.25 Unit Bits ksps 32.768 - 1000 kHz ADC Full Scale Voltage Conversion Time VOUT_1V8 – 0.036 V 32 Clocks ADC Integral Non-Linearity (INL) -2.0 - 2.0 LSB ADC Differential non-linearity (DNL) -1.0 - 1.
GS1500M DATA SHEET 4.8 SPI Interface Timing Test Conditions: VIN_3V3=VDDIO=Vbat=3.3V Temp=25ºC 4.8.1 Motorola SPI, clock polarity SPO = 0, clock phase SPH = 0 Figure 4-1: timing diagram, Master mode, SPO=SPH=0.
GS1500M DATA SHEET Figure 4-2: timing diagram, Slave mode, SPO=SPH=0. Parameter tSSetup tTxdDelay tRxdSetup Description Minimum Minimum time between falling edge of Select line and first rising edge of SPI clock. 4 core SPI clock periods + 68 ns Delay in Slave asserting TX line after falling edge of SPI clock, or the first bit after falling edge of the Select line.
GS1500M DATA SHEET 4.8.2 Motorola SPI, clock polarity SPO = 0, clock phase SPH = 1 Figure 4-3: timing diagram, Master, SPO=0, SPH=1. Parameter tSSetup tTxdDelay tRxdSetup tRxdHold tSSHold Description Minimum Minimum time between falling edge of select line and first rising edge of SPI clock. Delay in Master asserting TX line after rising edge of SPI clock. Time before falling edge of SPI clock by which received data must be ready.
GS1500M DATA SHEET Figure 4-4: timing diagram, Slave, SPO=0, SPH=1. Parameter Description tSSetup Minimum time between falling edge of select line and first rising edge of SPI clock. tTxdDelay Delay in Slave asserting TX line after rising edge of SPI clock. tRxdSetup Time before falling edge of SPI clock by which received data must be ready. tRxdHold Time for which received data must be stable after falling edge of SPI clock.
GS1500M DATA SHEET 4.8.3 Motorola SPI, clock polarity SPO = 1, clock phase SPH = 0 Figure 4-5: timing diagram, Master mode, SPO=1, SPH=0. Parameter Description Minimum tSSetup Minimum time between falling edge of select line and first falling edge of SPI clock. 1 tTxdDelay Delay in Master asserting TX line after falling edge of Select line. tRxdSetup tRxdHold tSSHold Time before falling edge of SPI clock by which received data must be ready.
GS1500M DATA SHEET Figure 4-6: timing diagram, Slave mode, SPO=1, SPH=0. Parameter tSSetup tTxdDelay tRxdSetup Description Minimum Minimum time between falling edge of Select line and first falling edge of SPI clock. 4 core SPI clock periods + 68 ns Delay in Slave asserting TX line after rising edge of SPI clock, or the first bit after falling edge of the Select line. Time before falling edge of SPI clock by which received data must be ready.
GS1500M DATA SHEET 4.8.4 Motorola SPI, clock polarity SPO = 1, clock phase SPH = 1 Figure 4-7: timing diagram, Master mode, SPO=SPH=1. Parameter tSSetup tTxdDelay tRxdSetup tRxdHold tSSHold Description Minimum time between falling edge of select line and first falling edge of SPI clock. Delay in Master asserting TX line after falling edge of SPI clock. Time before rising edge of SPI clock by which received data must be ready. Time for which received data must be stable after rising edge of SPI clock.
GS1500M DATA SHEET Figure 4-8: timing diagram, Slave mode, SPO=SPH=1. Parameter Description Minimum tSSetup Minimum time between falling edge of select line and first falling edge of SPI clock. 15 tTxdDelay Delay in Slave asserting TX line after falling edge of SPI clock. tRxdSetup Time before rising edge of SPI clock by which received data must be ready. tRxdHold Time for which received data must be stable after rising edge of SPI clock.
GS1500M DATA SHEET 5 Package and Layout Guidelines 5.
GS1500M DATA SHEET Figure 5-2: GS1500M Module Dimensions (in inches) PRELIMINARY GAINSPAN CONFIDENTIAL PAGE 38 OF 43
GS1500M DATA SHEET 6 Ordering Information DEVICE DESCRIPTION ORDERING NUMBER Rev Low power module using PCB antenna GS1500M Rev X.
GS1500M DATA SHEET 7 Regulatory Notes Federal Communication Commission Interference Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation.
GS1500M DATA SHEET IC Certification — Canada The labeling requirements for Industry Canada are similar to those of the FCC. A visible label on the outside of the final product must display the IC labeling. The user is responsible for the end product to comply with IC ICES-003 (Unintentional radiators) Manual Information That Must be Included The user’s manual for end users must include the following in-formation in a prominent location.
GS1500M DATA SHEET 8 Limitations THIS DEVICE AND ASSOCIATED SOFTWARE ARE NOT DESIGNED, MANUFACTURED OR INTENDED FOR USE OR RESALE FOR THE OPERATION OF APPLICATION IN A HAZARDOUS ENVIRONMENT, OR REQUIRING FAIL-SAFE PERFORMANCE, OR IN WHICH THE FAILURE OF PRODUCTS COULD LEAD DIRECTLY TO DEATH, PERSONAL INJURY, OR SEVERE PHYSICAL OR ENVIRONMENTAL DAMAGE (COLLECTIVELY, "HIGH RISK APPLICATIONS").
GS1500M DATA SHEET 9 References [1] Title Reference Version Source Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications IEEE Standard 802.11-2007 June 12, 2007 Date IEEE [2] Title Reference Version Source GS1011 Peripheral and Register Description GS1011-PRD 1.0 Date GainSpan [3] Title Reference Version Source GS1011 ULTRA LOW-POWER WIRELESS SYSTEM-ON-CHIP DATA SHEET GS1011-DS 1.
