Freescale Semiconductor Advance Information Document Number: MKW22D512V Rev. 0.1, 01/2013 MKW24D512V MKW24D512V MKW24D512V Also covers MKW22D512V and MKW21D256V Package Information Plastic Package 8x8 56-pin LGA Case 2234-01 Ordering Information Device 1 Introduction The MKW2xDxxxV devices consists of two separate ICs: a 2.4 GHz transceiver and a microcontroller.
1.1 Ordering information Table 1. Orderable parts details Program flash System RAM MKW24D512V (USB) 512 K 64 K MKW22D512V (USB) 512 K 64 K MKW21D256V 256 K 32 K Device 2 Features This section provides a simplified block diagram and highlights MKW2xDxxxV features. 2.1 Block diagram Figure 1 shows a simplified block diagram of the MKW2xDxxxV, which is an IEEE®802.15.4 standard compatible transceiver. Figure 1.
2.2 • • • • • • • • • • • • • 2.3 Radio features 2.4 GHz frequency band of operation 250 kbps data rate with O-QPSK modulation in 5.0 MHz channels with direct sequence spread-spectrum (DSSS) encode and decode Operates on one of 16 selectable channels per IEEE 802.15.4 specification Programmable output power Supports 2.36 to 2.4 GHz Medical Band (MBAN) frequencies with same modulation as IEEE 802.15.
• • • • • • — External watchdog monitor — Analog tamper detects (voltage, temperature, and clock) — External tamper detect — 256-bit secure storage (asynchronously erased on tamper detect) Ultra-low power: — 10 low power operating modes for optimizing peripheral activity and wake-up times for extended battery life.
• • • • Core features — Next generation 32-bit ARM Cortex-M4 core — Supports DSP instructions — Nested vectored interrupt controller (NVIC) — Asynchronous wake-up interrupt controller (AWIC) — Debug and trace capability – 2-pin serial wire debug (SWD) – IEEE 1149.1 Joint Test Action Group (JTAG) – IEEE 1149.
• • • • • 3 3.
• • • 3.2 — Data rate: 250 kbps — Symbol rate: 62.5 kbps — Modulation: OQPSK Receiver sensitivity: –102 dBm, typical (@1% PER for 20 byte payload packet) Differential bidirectional RF input/output port with integrated transmit/receive switch Programmable output power from –30 dBm to +10 dBm. RF interface and usage The MKW2xDxxxV RF output ports are bidirectional (diplexed between receive/transmit modes) and differential enabling interfaces with numerous off-chip devices such as a balun.
3.3.2 Transmit path MKW2xDxxxV transmits OQPSK modulation having power and channel selection adjustment per user application. After the channel of operation is determined, coarse and fine tuning is executed within the Frac-N PLL to engage signal lock. After signal lock is established, the modulated buffered signal is then routed to a multi-stage amplifier for transmission.
3.3.3.4 Energy detection (ED) Energy detection (ED) is based on receiver signal strength indicator (RSSI) and correlator output for the 802.15.4 standard. energy detect (ED) is an average value of signal strength. The magnitude from this measurement is calculated from the digital RSSI value that is averaged over an 128 s duration. 3.3.3.5 Link quality indicator (LQI) Link quality indicator (LQI), is based on receiver signal strength indicator (RSSI) or correlator output for the 802.15.4 standard.
• Supports active promiscuous mode 3.3.5 Packet buffering The packet buffer is a 128-byte random access memory (RAM) dedicated to the storage of 802.15.4 packet contents for both TX and RX sequences. For TX sequences, software stores the contents of the packet buffer starting with the frame length byte at packet buffer address 0, followed by the packet contents at the subsequent packet buffer addresses.
Table 2.
5 Radio Peripherals The MKW2xDxxxV provides a set of I/O pins useful for suppling a system clock to the MCU, controlling external RF modules/circuitry, and GPIO. In addition, there is a special option for streaming the digital packet data for external monitoring (BSM). 5.1 Clock output (CLK_OUT) MKW2xDxxxV integrates a programmable clock to source numerous frequencies for connection with various MCUs.
all 802.15.4 traffic appearing on a network within the range of the MKW2xDxxxV device allowing for PAN-level monitoring and debugging. BSM uses a simple synchronous 3-wire interface consisting of BSM_CLK, BSM_DATA, and BSM_ FRAME outputs. Packet data is shifted out serially at the 802.15.4 bit rate (250 kHz). Signaling is provided on BSM_FRAME to indicate start-of-packet and end-of-packet and to discriminate between TX and RX packet types. BSM_DATA and BSM_FRAME are synchronous to BSM_CLK.
Table 4. Pin configuration summary Tolerance Pin function configuration 3 4 5 6 7 5.3.1 Typ. Max. Source or sink — 10 — mA I/O buffer partial drive mode2 Source or sink — 2 — mA — — 10 nA 2 4 6 ns impedance3 Off state 4 No slew, full drive Rise and fall time No slew, partial drive Rise and fall time 2 4 6 ns Slew, full drive Rise and fall time 6 12 24 ns Slew, partial drive Rise and fall time 6 12 24 ns — — 11 ns Propagation delay5, no slew 2 Units Min.
always shifted out, so that the MCU gets access to IRQSTS1, with the minimum possible latency, on every SPI access. 5.3.1.1 • • • • • • • • • • • 5.3.2 Features 4-wire industry standard interface, supported by all MCUs SPI R_SCLK maximum frequency 16 MHz (for SPI write accesses). SPI R_SCLK maximum frequency 9 MHz (for SPI read accesses). Write and read access to all Coconino registers (direct and indirect) Write and read access to packet buffer SPI accesses can be single-byte or burst.
• • • • Doze (low power with reference oscillator active) Idle Receive Transmit Table 5 lists and describes these modes. Table 5. Radio mode definitions and transition times Current consumption1 Transition time to or from idle Reset / All IC functions off, leakage only. RST asserted. powerdown < 30 nA TBD Low power / Crystal reference oscillator off. (SPI is functional.) hibernate < 1 A TBD Crystal reference oscillator on but CLK_OUT output available only if selected.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
Table 7. Power Modes MCU Mode Radio Mode MCU typical current consumption Radio typical current consumption Stop Idle 320 A 700 A, typ. (no CLOCKOUT) Stop Doze 320 A 600 A, typ. (no CLOCKOUT) VLLS1 Low power / Hibernate 0.6 A <1 A1 VLLS0 Reset / Powerdown <250 nA <30 nA Transmit 12 mA 15 mA Receive 12 mA 15 mA Run2 Run3 1 Value does not include SPI activity.
7 MKW2xDxxxV electrical characteristics 7.1 Recommended operating conditions Table 8. Recommended operating conditions Characteristic Symbol Min Typ Max Unit VBATT, VDDINT 1.8 2.7 3.6 Vdc Input Frequency fin 2.360 — 2.480 GHz Ambient Temperature Range TA –40 25 105 C Logic Input Voltage Low VIL 0 — 30% VDDINT V Logic Input Voltage High VIH 70% VDDINT — VDDINT V SPI Clock Rate fSPI — — 16.
7.4 Symbol Description Min. Max. Unit Nots VHBM Electrostatic discharge voltage, human body model –2000 2000 V 1 VCDM Electrostatic discharge voltage, charged-device model –500 500 V 2 Latch-up current at ambient temperature of 105C –100 100 mA ILAT 1 2 ESD handling ratings Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
7.5.1 EMC radiated emissions operating behaviors 7.5.2 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to http://www.freescale.com. 2. Perform a keyword search for “EMC design.” 7.5.3 Capacitance attributes MKW2xDxxxV Product Electrical Specification, Rev. 0.
8 MCU Electrical characteristics 8.1 Maximum ratings Table 9. Maximum ratings Requirement Symbol Rating level Unit Power Supply Voltage VBAT, VBAT2 –0.3 to 3.6 Vdc Digital Input Voltage Vin –0.3 to (VDDINT + 0.
8.2 8.2.1 General AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 2.
8.2.2 8.2.2.1 Nonswitching electrical specifications Voltage and current operating requirements 1 1. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is greater than VAIO_MIN (=VSS-0.3V) and VIN is less than VAIO_MAX(=VDD+0.3V) is observed, then there is no need to provide current limiting resistors at the pads. If these limits cannot be observed then a current limiting resistor is required.
8.3 LVD and POR operating requirements 1. Rising thresholds are falling threshold + hysteresis voltage. VBAT power operating requirements MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.3.1 Voltage and current operating behaviors 8.3.2 Power mode transition operating behaviors All specifications except tPOR, and VLLSx to RUN recovery times in the following table assume this clock configuration: • • • CPU and system clocks = 50 MHz Bus clock = 50 MHz Flash clock = 25 MHz MKW2xDxxxV Product Electrical Specification, Rev. 0.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.3.3 Power consumption operating behaviors MKW2xDxxxV Product Electrical Specification, Rev. 0.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.4 8.4.1 Switching specification Device clock specifications 1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.4.2 General switching specifications These general purpose specifications apply to all signals configured for GPIO, UART, CMT, and I2C signals. MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.5 8.5.1 Core modules JTAG electricals Figure 3. Test clock input timing MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 4. Boundary scan (JTAG) timing Figure 5. Test access port timing MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 6. TRST timing MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.6 Clock modules MKW2xDxxxV Product Electrical Specification, Rev. 0.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.6.1 Oscillator electrical specifications MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.6.1.1 Oscillator frequency specification MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.6.2 32 kHz oscillator electrical characteristics 8.6.2.1 32 kHz oscillator DC electrical specifications 8.6.2.2 32 kHz oscillator frequency specifications 8.7 8.7.1 8.7.1.1 Memories and memory interfaces Flash electrical specifications Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. MKW2xDxxxV Product Electrical Specification, Rev. 0.
NVM program/erase timing specifications 8.7.1.2 Flash timing specifications — commands MKW2xDxxxV Product Electrical Specification, Rev. 0.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.7.1.3 Flash high voltage current behaviors 8.7.1.4 NVM reliability specifications 8.7.1.5 Write endurance to FlexRAM for EEPROM When the FlexNVM partition code is not set to full data flash, the EEPROM data set size can be set to any of several non-zero values. MKW2xDxxxV Product Electrical Specification, Rev. 0.
The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space.
Figure 7. EEPROM backup writes to FlexRAM 8.7.2 EzPort switching specifications MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 8. ExPort timing diagram 8.8 8.8.1 Analog ADC electrical specifications The 16-bit accuracy specifications are achievable on the differential pins ADCx_DP0, ADCx_DM0. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. MKW2xDxxxV Product Electrical Specification, Rev. 0.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 9. ADC input impedance equivalency diagram MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.8.1.1 16-bit ADC electrical characteristics MKW2xDxxxV Product Electrical Specification, Rev. 0.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 10. Typical ENOB vs. ADC_CLK for 16-bit differential mode Figure 11. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.8.2 CMP and 6-bit DAC electrical specifications MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 12. Typical hysteresis vs. Vin level (VDD=3.3 V, PMODE=0) MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 13. Typical hysteresis vs. Vin level (VDD=3.3 V, PMODE=1) 8.8.3 12-bit DAC electrical characteristics 8.8.3.1 12-bit DAC operating requirements 8.8.3.2 12-bit DAC operating behaviors The following table contains information about the 12-bit DAC on the MCU. MKW2xDxxxV Product Electrical Specification, Rev. 0.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 14. Typical INL error vs. digital code MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 15. Offset at half scale vs. temperature 8.8.4 8.8.4.1 Voltage reference electrical specifications VREF full-range operating requirements MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.8.4.2 VREF full-range operating behaviors 8.8.4.3 VREF limited-range operating requirements 8.8.4.4 VREF limited-range operating behaviors 8.9 8.9.1 Communication interfaces USB electrical specifications The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit http://www.usb.org. MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.9.2 USB DCD electrical specifications 8.9.3 VREG electrical specifications MKW2xDxxxV Product Electrical Specification, Rev. 0.
8.9.4 DSPI switching specifications (limited voltate range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to the DSPI chapter of the Reference Manual for information on the modified transfer formats used for communicating with slower peripheral devices. Master mode Figure 16.
Slave mode Figure 17. DSPI classic SPI timing — slave mode 8.9.5 DSPI switching specification (full voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provides DSPI timing characteristics for classic SPI timing modes.
Master mode DSPI timing (full voltage range) Figure 18. DSPI classic SPI timing — master mode Slave mode DSPI timing (full voltage range) MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 19. DSPI classic SPI timing — slave mode 8.9.6 Normal Run, Wait and Stop mode performance over the fulloperating voltage range This section provides the operating performance over the full operating voltage for the device in Normal Run, Wait and Stop modes. MKW2xDxxxV Product Electrical Specification, Rev. 0.
I2S/SAI master mode timing Figure 20. I2S/SAI timing — master modes MKW2xDxxxV Product Electrical Specification, Rev. 0.
I2S/SAI slave mode timing Figure 21. I2S/SAI timing — slave modes 8.9.7 VLPR, VLPW, and VLPS mode performance over the full operating voltage range This section provides the operating performance over the full operating voltage for the device in VLPR, VLPW, and VLPS modes. MKW2xDxxxV Product Electrical Specification, Rev. 0.
I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) Figure 22. I2S/SAI timing — master modes I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 23. I2S/SAI timing — slave modes 9 Transceiver electrical characteristics 9.1 DC electrical characteristics Table 10. DC electrical characteristics (VBATT, VDDINT = 2.
Table 10. DC electrical characteristics (VBATT, VDDINT = 2.
9.2 AC electrical characteristics Table 11. Receiver AC electrical characteristics (VBATT, VDDINT=2.
9.2.1 SPI timing: R_SSEL_B to R_SCLK The following diagram describes timing constraints that must be guaranteed by the system designer. R_SSEL_B R_SCLK tASC tCSC tCKL tCKH tDT Figure 24. SPI timing: R_SSEL_B to R_SCLK tCSC (CS-to-SCK delay): 31.25 ns tASC (After SCK delay): 31.25 ns tDT (Minimum CS idle time): 62.5 ns tCKH (Minimum R_SCLK high time): 31.25 ns (for SPI writes); 55.55 ns (for SPI reads) tCKL (Minimum R_SCLK low time): 31.25 ns (for SPI writes); 55.
Table 13. RF port impedance Characteristic RFIN Pins for internal T/R switch configuration, TX mode 2.360 GHz 2.420 GHz 2.480 GHz RFIN Pins for internal or external T/R switch configuration, RX mode 2.360 GHz 2.420 GHz 2.480 GHz PAO Pins for external T/R switch configuration, TX mode 2.360 GHz 2.420 GHz 2.
10.2 Crystal requirements The suggested crystal specification for the MKW2xDxxxV is shown in Table 14. A number of the stated parameters are related to desired package, desired temperature range and use of crystal capacitive load trimming. Table 14.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
MKW2xDxxxV Product Electrical Specification, Rev. 0.
12 Packaging information Figure 26. MKW22/24D512V (USB) Pin Assignment MKW2xDxxxV Product Electrical Specification, Rev. 0.
Figure 27. MKW21D256V Pin Assignment MKW2xDxxxV Product Electrical Specification, Rev. 0.
