FLC-BTM805 Datasheet FLC-BTM805 Datasheet Document Type: Bluetooth Module Datasheet Document Number: FLC-BTM805-DS Document Version: V1.6 Release Date: 2012/12/18 Copyright 2012~ 2014 by Flaircomm Microelectronics Inc., All Right Reserved Without written permission from Flaircomm Microelectronics Inc.
FLC-BTM805 Datasheet Release Record Version Release Date 1.0 1.1 2012/6/26 2012/9/6 1.2 1.3 1.4 2012/9/24 2012/11/2 2012/11/22 1.5 1.6 2012/11/27 2012/12/18 Flaircomm Microelectronics Confidential Comments Release Modify operating temperature. Add BT/CE/FCC logo. Add Cautions & Warnings. Modify sensitivity, weight and working current. Add FLC-BTM805 Antenna Statement. Small modification about Antenna Statement and Label Instructions. Add module weight. Modify RF TX Power and FCC Statement.
FLC-BTM805 Datasheet CONTENTS 1. 1.1 1.2 1.3 1.4 INTRODUCTION .................................................................................................................................................. 6 NAMING DECLARATION ........................................................................................................................................ 6 BLOCK DIAGRAM ...............................................................................................................................
FLC-BTM805 Datasheet 9. 10. RECOMMENDED REFLOW PROFILE ......................................................................................................... 35 ORDERING INFORMATION ....................................................................................................................... 36 10.1 PRODUCT PACKAGING INFORMATION ................................................................................................................. 36 10.2 ORDERING INFORMATION ........................
FLC-BTM805 Datasheet Figure 11: 16-Bit Slot Length and Sample Formats ....................................................................................................... 19 Figure 12: PCM Master Timing Long Frame Sync ........................................................................................................ 21 Figure 13: PCM Master Timing Short Frame Sync .......................................................................................................
FLC-BTM805 Datasheet 1. Introduction FLC-BTM805 is a dual-mode Bluetooth HCI module that allows OEM to add Bluetooth wireless capability to their products. The module supports BT3.0-HS and BT4.0 (Bluetooth low energy) with HCI interface that makes it simple to design into fully certified embedded Bluetooth solutions. With FLC’s Bluetooth stack running on a host, designers can easily customize their applications to support different Bluetooth profiles, such HS/HF, A2DP, AVRCP, OPP, DUN, SPP, and etc.
FLC-BTM805 Datasheet Antenna PIOs Filter UART SPI / PCM CSR8811 Crystal VDD Figure 2: BTM805CL2B Block Diagram 1.3 Features Fully qualified Bluetooth® v4.0 specification system Dual-mode Bluetooth /Bluetooth low energy Draft Bluetooth low energy HID boot mode support Full-speed Bluetooth operation with full piconet and scatternet support High speed UART interface WLAN coexistence interface Green (RoHS) 1.
FLC-BTM805 Datasheet 2. General Specification Bluetooth Specification Standard Frequency Band BT2.1+EDR, BT 3.0-HS, BT4.0 BLE 2.402G ~ 2.480G Maximum Data Rate 3Mbps RF Input Impedance 50 ohms Baseband TCXO 26MHz Interface Sensitivity RF TX Power UART, PIO, SPI, PCM/I2S/SPDIF -86dBm@0.1%BER 8.5dBm(MAX) Power Supply Voltage 2.3 ~ 4.
FLC-BTM805 Datasheet 3. Pin Definition 3.
FLC-BTM805 Datasheet Figure 4: BTM805CL2B Pin Configuration 3.2 Pin Definition BTM805CL2A Pin Definition: Pin Symbol I/O Type 1 ANT RF Antenna Port 2 GND Ground Ground 3 VDD_AUX Analogue Regulator decoupler 2.
FLC-BTM805 Datasheet Input with strong internal pulldown Positive supply for all other digital input/output ports including PIO[6.0] and both PCMs 1. Active low reset ; 2.
FLC-BTM805 Datasheet 6 PIO1 7 VDD_DIG 8 PIO4 9 PIO2 10 PIO5 11 VDD_PADS 12 VREG_EN RST# 13 VDD_IN 14 VREG_OUT_HV 15 Bi-directional with programmable strength internal pull-up/down Programmable input/output line Digital Regulator decoupler 2.
FLC-BTM805 Datasheet 4. Physical Interfaces 4.1 Power Control and Regulation Four regulators are integrated in this product. The high-voltage regulator generates the main 1.8V rail from the VDD_IN. This then supplies 3 lower voltage linear regulators: A programmable low-voltage regulator to supply the 0.90V to 1.25V digital supply, VDD_DIG A low-voltage regulator to supply the 1.35V VDD_ RADIO rail An always-on regulator to supply 1.35V to auxiliary and reference circuitry, VDD_AUX 4.1.
FLC-BTM805 Datasheet 4.1.4 Low-voltage VDD_AUX Linear Regulator The on-board low-voltage VDD_AUX Regulator powers BTM805 1.35V VDD_AUX supply. The regulator is controlled by the firmware. 4.1.5 Power-on Sequencing BTM805 does not have any strict relative timing requirements for clock and power supply sequencing during reset or power-on. Follow this sequence of operation to ensure that the initial cold boot is completed successfully: 1、All external power supplies should be stable.
FLC-BTM805 Datasheet Note: Pull-up (PU) and pull-down (PD) default to weak values unless specified otherwise. 4.3 Audio Interfaces BTM805 has two digital audio interfaces that are configurable as either PCM or I2S ports. 4.3.1 PCM Interface There are two audio interfaces. Each can be independently configured as an I2S or a PCM port. The PCM1 interface also shares the same physical set of pins with the SPI interface as described in the Device Terminal Functions section.
FLC-BTM805 Datasheet Figure 5: Configured PCM as a Master Figure 6: Configured PCM as a Slave 4.3.1.2 Long Frame Sync Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When BTM805 is configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long.
FLC-BTM805 Datasheet Figure 7: Long Frame Sync (Shown with 8-bit Companded Sample) BTM805 samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. 4.3.1.3 Short Frame Sync In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always one clock cycle long.
FLC-BTM805 Datasheet Figure 9: Multi-Slot Operation with Two Slots and 8-bit Companded Samples 4.3.1.5 GCI Interface BTM805 is compatible with the General Circuit Interface (GCI), a standard synchronous 2B+D ISDN timing interface. The two 64Kbps B channels are accessed when this mode is configured. Figure 10: GCI Interface The start of a frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. 4.3.1.
FLC-BTM805 Datasheet Little or big endian bit order. For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible with some codecs. Figure 11: 16-Bit Slot Length and Sample Formats 4.3.1.7 Additional Features BTM805 has a mute facility that forces PCM_OUT to be 0. In master mode, BTM805 is compatible with some codecs which control power down by forcing PCM_SYNC to 0 while keeping PCM_CLK running. 4.3.1.
FLC-BTM805 Datasheet Symbol Parameter Min Typical Max Unit - kHz - kHz 128 fmclk tmclkh (a) (a) tmclkl - 4MHz DDS generation. Selection of frequency is programmable. PCL_CLK Frequency 256 512 48MHz DDS generation. Selection of frequency is programmable. PCM_SYNC frequency for SCO connection PCM_CLK 4MHz DDS generation high PCM_CLK low PCM_CLK jitter - 4MHz DDS generation 2.
FLC-BTM805 Datasheet Figure 12: PCM Master Timing Long Frame Sync Figure 13: PCM Master Timing Short Frame Sync Flaircomm Microelectronics Confidential -21-
FLC-BTM805 Datasheet Symbol Parameter Min Typical Max Unit fsclk fsclk tsclkl tsclkh PCM clock frequency (Slave mode: input) PCM clock frequency (GCI mode) PCM_CLK low time PCM_CLK high time 64 128 200 200 - 2048 4096 - kHz kHz ns ns 2 - - ns 20 - - ns - - 15 ns - - 15 ns - - 20 ns 20 - - ns 2 - - ns Table 8: PCM Slave Timing thsclksynch tsusclksynch tdpout tdsclkhpout tdpoutz tsupinsclkl thpinsclkl Hold time from PCM_CLK low to PCM_SYNC high Set-up time for PCM_SY
FLC-BTM805 Datasheet Figure 14: PCM Slave Timing Long Frame Sync Figure 15: PCM Slave Timing Short Frame Sync Flaircomm Microelectronics Confidential -23-
FLC-BTM805 Datasheet 4.3.2 Digital Audio Interface (I2S) The digital audio interface supports the industry standard formats for I2S, left-justified or rightjustified. The interface shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. Table 9 lists these alternative functions. Figure 14 shows the timing diagram.
FLC-BTM805 Datasheet Figure 16: Digital Audio Interface Modes The internal representation of audio samples within BTM805 is 16-bit and data on SD_OUT is limited to 16-bit per channel. Symbol Tch tcl Parameter SCK Frequency WS Frequency SCK high time SCK low time Min Typical Max Unit 80 80 - 6.2 96 - MHz kHz ns ns Min Typical Max Unit 20 2.
FLC-BTM805 Datasheet Topd tisu Tih SCK low to SD_OUT valid delay time SD_IN valid to SCK high set-up time SCK high to SD_IN invalid hold time 18.44 0 - 18.44 - ns ns ns Table 14: Digital Audio Interface Slave Mode Timing Parameters Figure 18: Digital Audio Interface Master Timing 4.4 RF Interface The module integrates a balun filter. The user can connect a 50ohms antenna directly to the RF port for BTM805CL2A. BTM805CL2B integrates an antenna internally. 4.
FLC-BTM805 Datasheet When BTM805 is connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The remaining 2 signals, UART_CTS and UART_RTS, implement RS232 hardware flow control where both are active low indicators. If UART_CTS and UART_RTS are not required for hardware flow control, they are reconfigurable as PIO. UART configuration parameters, such as baud rate and packet format, are set using BTM805 firmware.
FLC-BTM805 Datasheet 5. Electrical Characteristic 5.1 Absolute Maximum Ratings Ratings Min Max Unit Storage Temperature -40 +85 °C VBAT operation(a) 2.3 4.8 V Low-voltage operation (bypassing high-voltage linear regulator) 1.7 2.0 V I/O supply voltage -0.4 +3.6 V VSS-0.4 VDD+0.4 V Other Terminal Voltages Table 16: Absolute Maximum Rating 5.
FLC-BTM805 Datasheet 5.3.2 Low-voltage VDD_DIG linear Regulator Normal Operation Min Typical Max Unit Output voltage 0.90 - 1.25 V Output current - - 30 mA Min Typical Max Unit Output voltage 1.30 1.35 1.40 V Output current - - 5 mA Min Typical Max Unit Output voltage 1.30 1.35 1.45 V Output current - - 60 mA Min Typical Max Unit VIL input logic level low -0.4 - +0.4 V VIH input logic level high 0.7×VDD - VDD+0.4 V - - 0.4 V 0.
FLC-BTM805 Datasheet 6.
FLC-BTM805 Datasheet 7.
FLC-BTM805 Datasheet BTM805CL2B (with Antenna)： Figure 21: BTM805CL2B Footprint Flaircomm Microelectronics Confidential -32-
FLC-BTM805 Datasheet 8. Recommended PCB Layout and Mounting Pattern Placement and PCB layout are critical to optimize the performances of a module without on-board antenna designs. The trace from the antenna port of the module to an external antenna should be 50 and must be as short as possible to avoid any interference into the transceiver of the module. The location of the external antenna and RF-IN port of the module should be kept away from any noise sources and digital traces.
FLC-BTM805 Datasheet Distance between connection and ground area on the top layer should at least be as large as the dielectric thickness. Routing the RF close to digital sections of the system board should be avoided. To reduce signal reflections, sharp angles in the routing of the micro strip line should be avoided. Chamfers or fillets are preferred for rectangular routing; 45-degree routing is preferred over Manhattan style 90-degree routing.
FLC-BTM805 Datasheet 9. Recommended Reflow Profile The soldering profile depends on various parameters necessitating a set up for each application. The data here is given only for guidance on solder reflow. ℃ 250 217 210 A 25 0 B 1 2 C 3 D 4 E 5 6 min Figure 25: Recommended Reflow Profile Pre-heat zone (A) — This zone raises the temperature at a controlled rate, typically 0.5 – 2 C/s. The purpose of this zone is to preheat the PCB board and components to 120 ~ 150 C.
FLC-BTM805 Datasheet 10. Ordering Information 10.1 Product Packaging Information TBD Figure 26: Product Packaging Information 10.2 Ordering information FLC-BTM805XYZA Product Revision Shipping Package Product Package Product Grade Figure 27: Ordering Information Package Host Interface UART Order Number Type Shipment LGA Tape and reel BTM805CL2A BTM805CL2B 10.2.
FLC-BTM805 Datasheet 10.2.3 Product Package Product Package Description Availability Q L B C QFN LGA BGA Connector No Yes No No Table 20: Product Package 10.2.
FLC-BTM805 Datasheet 11. Cautions &Warnings 11.1 FCC Statement 1. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference. (2) This device must accept any interference received, including interference that may cause undesired operation. 2. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.
FLC-BTM805 Datasheet The packaging of host system that uses BTM805 should display a label indicating the information as follows: Contains FCC ID: P4IBTM805 Model: FLC-BTM805 (Series models: FLC-BTM805IL2A/ FLC-BTM805CL2A/ FLC-BTM805VL2A/ FLC-BTM805IL2B/ FLC-BTM805CL2B/ FLC-BTM805VL2B) Any similar wording that expresses the same meaning may also be used. 11.4 FLC-BTM805 Antenna Statement Note: In this section, “A” and “B” in “BTM805A” and “BTM805B” refer to Product Revision. Please see Section 10.2.
FLC-BTM805 Datasheet The following figures show the Radiation Patterns of the antenna in BTM805B.
