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FIBOCOM L850-GL Series

Hardware Guide

Version: V1.1.5

Date: 2020-06-20

Summary of content (59 pages)

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FIBOCOM L850-GL Series Hardware Guide Version: V1.1.
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Applicability Type No. Product Model Description 1 L850-GL-00 NA 2 L850-GL-01 NA 3 L850-GL-02 NA 4 L850-GL-03 NA 5 L850-GL-05 NA 6 L850-GL-10 L850-GL-10 series (except L850-GL-10-06) 7 L850-GL-10-06 NA 8 L850-GL-12 NA 9 L850-GL-20 NA Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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Copyright Copyright © 2020 Fibocom Wireless Inc. All rights reserved. Without the prior written permission of the copyright holder, any company or individual is prohibited to excerpt, copy any part of or the entire document, or distribute the document in any form. Notice The document is subject to update from time to time owing to the product version upgrade or other reasons. Unless otherwise specified, the document only serves as the user guide.
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Change History Version Author Date Remark ● Section 3.3.1, add FCPO# controlling GPIO request V1.1.5 Shu Ying 2020-06-20 ● Section 3.4.1.2, change PEWAKE# pull high resistor to 100KΩ V1.1.4 Li Senhao 2020-04-01 ● Section 3.1.2, add GPIO design request ● Section 3.3.4, add CLKREQ# and PEWAKE# requests ● Section 3.3.1.2, add minimum PCIe detection time note ● Section 3.3.5, add timing application instruction V1.1.3 Guan Xiangyang 2019-12-26 ● Section 3.4.1.
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Version Author Date Remark ● Modify CA combinations and TDD data throughput V1.0.5 Lei Daijun 2018-01-16 ● Modify description of power consumption condition ● Optimize power on/off/reset timing V1.0.4 Lei Daijun 2017-12-06 Update Storage and packing and PCIe signal description, power consumption, CA combine ● Update timing of power on/off and reset V1.0.3 Lei Daijun 2017-07-26 ● Update PCIe, add USB support ● Update power consumption, TX power, RX sensitivity and other data V1.0.
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Contents 1 2 3 Foreword ........................................................................................................................9 1.1 Introduction..................................................................................................................... 9 1.2 Reference Standard ....................................................................................................... 9 1.3 Related Documents .......................................................................
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3.5 3.4.2.1 USB Interface Definition .............................................................................................................. 36 3.4.2.2 USB2.0 Interface Application....................................................................................................... 36 3.4.2.3 USB3.0 Interface Application....................................................................................................... 36 USIM Interface .....................................................
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5.5 Storage ......................................................................................................................... 56 5.5.1 5.6 Storage Life .................................................................................................................56 Packing......................................................................................................................... 56 5.6.1 Tray Package ................................................................................
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1 Foreword 1.1 Introduction The document describes the electrical characteristics, RF performance, dimensions and application environment, etc. of L850-GL (hereinafter referred to as L850). With the assistance of the document and other instructions, the developers can quickly understand the hardware functions of L850 modules and develop products. 1.2 Reference Standard The design of the product complies with the following standards:  3GPP TS 34.121-1 V8.11.
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2 Overview 2.1 Introduction L850 is a highly integrated 4G WWAN module which uses M.2 form factor interface. It supports LTE FDD/LTE TDD/WCDMA systems and can be applied to most cellular networks of mobile carrier in the world. 2.
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Interface Antenna Connector WWAN Main Antenna ×1 WWAN Diversity Antenna ×1 USIM 3V/1.8V PCIe Gen1 ×1 USB 2.0 USB 3.1 Gen1 (Base on Android/Linux) W_Disable# Function Interface BodySAR LED Clock Tunable antenna I2S (Reserved) I2C (Reserved) Software Protocol Stack IPV4/IPV6 AT commands 3GPP TS 27.007 and 27.
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2.
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CA Combinations L850-GL-10-06 2+4, 5, 13 Inter-band 2CA 3CA 4+5, 13 Intra-band (non-contiguous) 2, 4 Intra-band (contiguous) 2 Inter-band 2+4+5, 2+4+13 2 intra-band (non-contiguous) 2+2+5, 2+2+13 plus inter-band 4+4+5, 4+4+13 2.4 Application Framework The peripheral applications for L850 module are shown in Figure 2-1: Div ANT Main ANT Module Power Supply ON/OFF# RESET# SIM PCIe USB2.0 SIM Card Control USB3.
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2.5 Hardware Block Diagram The hardware block diagram in Figure 2-2 shows the main hardware functions of L850 module, including baseband and RF functions. Baseband contains the followings:  UMTS/LTE TDD/LTE FDD controller  PMU  NAND/internal LPDDR2 RAM  Application interface RF contains the followings:  RF Transceiver  RF Power/PA  RF Front end  RF Filter  Antenna Connector +3.
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3 Application Interface 3.1 M.2 Interface The L850 module applies standard M.2 Key-B interface, with a total of 75 pins. 3.1.1 Pin Map Figure 3-1 Pin map Note: Pin “Notch” represents the gap of the gold fingers. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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3.1.2 Pin Definition The pin definition is as follows: Pin Pin Name I/O Reset Value Pin Description Type NC, L850 M.2 module is configured as 1 CONFIG_3 O NC the WWAN – PCIe, USB3.1 interface - type 2 +3.3V PI - Power input Power Supply 3 GND - - GND Power Supply 4 +3.3V PI - Power input Power Supply 5 GND - - GND Power Supply I PU 6 FULL_CARD_ POWER_OFF# Power enable, module power on input, internal pull up 3.3/1.8V 7 USB D+ I/O - USB data plus 0.
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Pin Pin Name I/O Reset Value Pin Description 23 WOWWAN# O PD 24 I2S_TX O PD 25 DPR I PU 26 W_DISABLE2# I PU 27 GND - - 28 I2S_WA O PD 29 USB3.0_TX- O - USB3.0 transmit data minus - 30 UIM_RESET O L SIM reset signal 1.8V/3V 31 USB3.0_TX+ O - USB3.0 transmit data plus - 32 UIM_CLK O L SIM clock signal 1.8V/3V 33 GND - - GND Power Supply 34 UIM_DATA I/O L SIM data input/output 1.8V/3V 35 USB3.0_RX- I - USB3.
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Pin Pin Name I/O Reset Value Pin Description Type 46 SYSCLK O PD 26M clock output 1.8V 47 PERn0 I - 48 TX_BLANKING O PD 49 PERp0 I - PCIe RX differential signal Negative PA blanking timer, Reserved PCIe RX differential signal Positive 1.8V - Asserted to reset module PCIe interface default. If module went into core dump, 50 PERST# I PU it will reset whole module, not only PCIe 3.3V interface.
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Pin Pin Name I/O Reset Value Pin Description Type 59 ANTCTL0 O - Tunable ANT CTRL0, bit0 1.8V Wireless coexistence between WWAN 60 COEX3 I/O PD and WiFi/BT modules, based on BT-SIG coexistence protocol. COEX_EXT_FTA, 1.8V Reserved 61 ANTCTL1 O - Tunable ANT CTRL1, bit1 1.8V Wireless coexistence between WWAN and WiFi/BT modules, based on BT-SIG 62 COEX_RXD I T coexistence protocol. UART receive 1.8V signal(WWAN module side) Reserved 63 ANTCTL2 O - Tunable ANT CTRL2, bit2 1.
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Reset Value: The initial status after module reset, not the status when working.  H: High Voltage Level  L: Low Voltage Level  PD: Pull-Down  PU: Pull-Up  T: Tristate  OD: Open Drain  PP: Push-Pull  PI: Power Input  PO: Power Output Note: Digital IO pins CANNOT be connected to power directly. The unused pins can be left floating. All 3.3V ports are based on +3.3V power domain. When the power supply range is 3.135V~4.4V, the 3.
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Figure 3-2 Power supply design The filter capacitor design for power supply is shown in the following table: Recommended Capacitance Application Description Reduce power fluctuations of the module in operation, requiring capacitors with low ESR. Voltage-stabilizing 220uF×2  LDO or DC/DC power supply requires the capacitor of no less than 440uF capacitors  The capacitor for battery power supply can be reduced to 100~200uF 1uF, 100nF 39pF, 33pF 18pF, 8.2pF, 6.
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Burst transmit Burst transmit Ripple≤300mV Power supply Drop VBAT≥3.135V min:3.135V Figure 3-3 Power supply limit 3.2.2 Logic Level The L850 module 1.8V logic level definition is shown in the following table: Parameter Minimum Typical Maximum Unit 1.8V logic level 1.71 1.8 1.89 V VIH 1.3 1.8 1.89 V VIL -0.3 0 0.3 V The L850 module 3.3V logic level definition is shown in the following table: Parameter Minimum Typical Maximum Unit 3.3V logic level 3.135 3.3 3.465 V VIH 2.
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Parameter IWCDMA-RMS ILTE-RMS Average Mode Condition Radio Off AT+CFUN=4, Flight mode 1.8 WCDMA Data call Band 1 @+23.5dBm 580 WCDMA Data call Band 2 @+23.5dBm 650 WCDMA Data call Band 4 @+23.5dBm 550 WCDMA Data call Band 5 @+23.5dBm 500 WCDMA Data call Band 8 @+23.
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Parameter Mode Average Condition Current (mA) LTE TDD Data call Band 39 @+23dBm 340 LTE TDD Data call Band 40 @+23dBm 380 LTE TDD Data call Band 41 @+23dBm 430 In 3CA mode, the L850 power consumption is shown in the following table: Condition Average (Maximum Data Transfer) Current (mA) Band 1 @+22dBm 720 Band 2 @+22dBm 820 Band 3 @+22dBm 870 Band 4 @+22dBm 820 Band 5 @+22dBm 750 Band 7 @+22dBm 1060 2+29+30 Band 8 @+22dBm 650 3+7+20, 3+7+28 Band 11 @+22dBm 1040 Band 12 @+22d
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3.3 Control Signal The L850 module provides two control signals for power on/off and reset operations. The pin is defined in the following table: Pin Pin Name I/O Reset Value Functions Type Module power on/off input, 6 FULL_CARD_POWER_OFF# I PU internal pull up 3.3/1.8V Power on: High/Floating Power off: Low 67 RESET# I - WWAN reset input, internal pull 1.8V up(10KΩ), active low Asserted to reset module PCIe interface default.
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Figure 3-4 Circuit for module start-up controlled by AP 3.3.1.2 Start-up Timing Sequence When power supply is ready, the PMU of module will power on and start initialization process by pulling high FCPO# signal. After about 10s, module will complete initialization process. The start-up timing is shown in Figure 3-5: tpr +3.3V FCPO# ton1 RESET# ton2 PERST# typical 10s Module State OFF Initialization Activation(AT Command Ready) Figure 3-5 Timing control for start-up Index Min. Recommended Max.
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3.3.2 Module Shutdown The module can be shut down by the following controls: Shutdown Control Action Condition Software Normal shutdown(recommend) Sending AT+CFUN=0 command Only used when a hardware exception Hardware Pull down FCPO# pin occurs and the software control cannot be used. The module can be shut down by sending AT+CFUN=0 command.
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3.3.3 Module Reset The L850 module can reset to its initial status by pulling down the RESET# signal for more than 2ms (10ms is recommended), and module will restart after RESET# signal is released. When customer executes RESET# function, the PMU remains its power inside the module.
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+3.3V toff FCPO# toff2 RESET# ton1 toff1 AT+CFUN=0 ton2 PERST# typical 10s tsd Module State Activation Finalization OFF Initialization Activation Figure 3-9 Reset timing 2nd Index Min. Recommended Max. toff1 16ms 20ms - toff2 2ms 10ms - Comments RESET# should be asserted after PERST#, refer section 3.3.2 FCPO# should be asserted after RESET#, refer section 3.3.
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Power Consumption PCIe Link State PERST# CLKREQ# D0 L1.2 H H Isleep L H Isleep+0.5 L L Isleep+0.8 (mA) Description Refer 3.2.3 Power Consumption D3cold L2 The extra 0.5mA is consumed on PERST# pull down The extra 0.3mA is consumed on CLKREQ# pull down 3.3.4.1 D0 L1.2 Module supports PCIe goes into D0 L1.2 state in Win10 system. The D0 L0@S0/S0ix→ D0 L1.2@S0/S0ix→D0 L0@S0/S0ix timing is shown in figure 3-10: +3.3V FCPO# RESET# PERST# CLKREQ# Module State D0 L0@S0/S0ix D0 L1.
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+3.3V FCPO# RESET# PERST# Host assert Host de-assert CLKREQ# PEWAKE# Module State D0 L0@S0/S0ix D3cold L2@S0/S0ix D0 L0@S0/S0ix Figure 3-11 D3cold L2 timing (Host wakeup) +3.
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3.3.5 Timing Application The recommended timing application in Win10 OS is as below table: System status Timing Application D0 L1.2 S0ix (Modem standby) D3cold L2 Refer to section 3.3.4.1 Figure 3-10 D0 L1.2 Timing S3, S4, S5 G3 boot Refer to section 3.3.4.2 Figure 3-11/3-12 D3cold L2 timing Power on (back to S0) Refer to section 3.3.1.2 Figure 3-5 Timing control for start-up Power off (out of S0) Refer to section 3.3.2 Figure 3-6 Software power off timing Power on Refer to section 3.3.1.
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3.4.1 PCIe Interface L850 module supports PCIe Gen1 interface and one data transmission channel. BIOS configuration must follow X86 platform BKC (Best Know Configuration) reference design. PCIe interface is initialized with host driver, and then mapped MBIM & GNSS port in Win10 OS. The MBIM interface is used for data transfer and GNSS port is used for receiving GNSS data. 3.4.1.
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3.4.1.2 PCIe Interface Application The reference circuit is shown in Figure 3-13: AP side Module side AC Caps PERP0 PETn0 AC Caps PETP0 REFCLKN REFCLKP +3.3V/1.8V 100K PERST# CLKREQ# 10K M.2 Key-B 75pin Connector PERn0 WAKE# PETn0(pin41) PETP0(pin43) PERn0(pin47) PERP0(pin49) REFCLKN(pin53) REFCLKP(pin55) PERST#(pin50) CLKREQ#(pin52) PEWAKE#(pin54) Figure 3-13 Reference circuit for PCIe interface L850 module supports PCIe Gen1 interface, one lane.
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should be at least 3 times the line width (≥ 3W). The largest spacing between the bended part of the serpentine line and another one of the differential lines must be less than 2 times the spacing of normal differential lines (S1 < 2S); ≥1.5W ≥3W ° 35 ≥1 W PCIe Difference Pair 1 S S1<2S ≥20mil PCIe Difference Pair 2 Figure 3-14 Requirement of PCIe line  The difference in length of two data lines in difference pair should be within 5mil, and the length match is required for all parts.
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configured in practical application. 3.4.2.1 USB Interface Definition Pin# Pin Name I/O Description Type 7 USB_D+ I/O USB data plus 9 USB_D- I/O USB data minus 29 USB3.0_TX- O USB3.0 transmit data minus - 31 USB3.0_TX+ O USB3.0 transmit data plus - 35 USB3.0_RX- I USB3.0 receive data minus - 37 USB3.0_RX+ I USB3.0 receive data plus - 0.3---3V, USB2.0 0.3---3V, USB2.0 3.4.2.2 USB2.
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Figure 3-17 Reference circuit for USB3.0 interface USB3.0 signals are super speed differential signal lines with the maximum transfer rate of 5 Gbps. So the following rules should be followed carefully in the case of PCB layout:  USB3.0_TX-/USB3.0_TX+ and USB3.0_RX-/ USB3.0_RX+ are two pairs differential signal lines. The differential impedance should be controlled as 90Ω.  The two pairs differential signal lines should be parallel and have the equal length. The right angle routing should be avoided.
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3.5.2 USIM Interface Circuit 3.5.2.1 N.C. SIM Card Slot The reference circuit design for N.C. (Normally Closed) SIM card slot is shown in Figure 3-18: Figure 3-18 Reference circuit for N.C. SIM card slot The principles of the N.C.SIM card slot are described as follows:  When the SIM card is detached, it connects the short circuit between CD and SW pins, and drives the SIM_DETECT pin low.
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 When the SIM card is inserted, it connects the short circuit between CD and SW pins, and drives the SIM_DETECT pin high. 3.5.3 USIM Hot-Plug The L850 module supports the SIM card hot-plug function, which determines whether the SIM card is inserted or detached by detecting the SIM_DETECT pin state of the SIM card slot.
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least. The filter capacitors and ESD devices for SIM card signals should be placed near to the SIM card slot,  and the ESD devices with 22~33pF capacitance should be used. 3.6 Status Indicator The L850 module provides three signals to indicate the operating status of the module, and the status indicator pins is shown in the following table: Pin Pin Name I/O Reset Value Pin Description Type 10 LED1# O PD System status LED, drain output. 3.
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3.7 Interrupt Control The L850 module provides three interrupt signals, and the pin definition is as follows: Pin Pin Name I/O Reset Value Pin Description Type 8 W_DISABLE1# I PD Enable/Disable RF network 3.3/1.8V 25 DPR I PU BodySAR detection 3.3/1.8V 26 W_DISABLE2# I PU GNSS disable signal, Reserved 3.3/1.8V 3.7.1 W_DISABLE1# The module provides a hardware pin to enable/disable WWAN RF function, and the function can also be controlled by the AT command.
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3.9 ANT Tunable Interface The module supports ANT Tunable interfaces with two different control modes, i.e. MIPI interface and 3bit GPO interface. Through cooperating with external antenna adapter switch via ANT Tunable, it can flexibly configure the bands of LTE antenna to improve the antenna’s working efficiency and save space for the antenna.
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Config_0 Config_1 Config_2 Config_3 Module Type and Main Port (pin21) (pin69) (pin75) (pin1) Host Interface Configuration GND GND GND NC WWAN–USB3.1 Gen1, 0 PCIe Gen1 Please refer to “PCI Express M.2 Specification Rev1.2” for more details. Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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4 Radio Frequency 4.1 RF Interface 4.1.1 RF Interface Functionality The L850 module supports two RF connectors used for external antenna connection. As the Figure 4-1 shows, “M” is for Main antenna, which is used to receive and transmit RF signal; “D/G” is for Diversity antenna, which is used to receive the diversity RF and GNSS signals. Figure 4-1 RF connectors 4.1.2 RF Connector Characteristic Rated Condition Environment Condition Frequency Range DC~6GHz Characteristic Impedance 50Ω 4.1.
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Figure 4-2 RF connector dimensions Figure 4-3 0.81mm coaxial antenna dimensions Figure 4-4 Schematic diagram of 0.81mm coaxial antenna connected to the RF connector Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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4.1.4 RF Connector Assembly Mate RF connector parallel refer Figure 4-5, do not slant mate with strong force. Figure 4-5 Mate RF connector To avoid damage in RF connector unmating, it is recommended using pulling JIG as Figure 4-6, and the pulling JIG must be lifted up vertically to PCB surface (see Figure 4-7 and 4-8). Figure 4-6 Pulling JIG Figure 4-7 Lift up pulling JIG Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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4.
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4.3 Transmitting Power The transmitting power for each band of L850 module is shown in the following table: Tx Power Mode Band 3GPP Requirement (dBm) Note (dBm) WCDMA LTE FDD LTE TDD Band 1 24+1.7/-3.7 23.5±1 - Band 2 24+1.7/-3.7 23.5±1 - Band 4 24+1.7/-3.7 23.5±1 - Band 5 24+1.7/-3.7 23.5±1 - Band 8 24+1.7/-3.7 23.5±1 - Band 1 23±2.7 23±1 10MHz Bandwidth, 1 RB Band 2 23±2.7 23±1 10MHz Bandwidth, 1 RB Band 3 23±2.7 23±1 10MHz Bandwidth, 1 RB Band 4 23±2.
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Mode Band 3GPP Requirement (dBm) Tx Power (dBm) Note Band 40 23±2.7 23±1 10MHz Bandwidth, 1 RB Band 41 23±2.7 23±1 10MHz Bandwidth, 1 RB Note: Band 30 TX power range of L850-GL-03 serial module is between 22±1dBm, not 23±1dBm. 4.4 Receiver Sensitivity The receiver sensitivity for each band of the L850 module is shown in the following table: Mode WCDMA LTE FDD Band 3GPP Requirement (dBm) Rx Sensitivity (dBm) Typical Note Band 1 -106.7 -109.5 BER < 0.1% Band 2 -104.7 -110 BER < 0.
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Mode LTE TDD Band 3GPP Requirement (dBm) Rx Sensitivity (dBm) Typical Note Band 26 -93.8 -103 10MHz Bandwidth Band 28 -94.8 -103 10MHz Bandwidth Band 29 -93.3 -101 10MHz Bandwidth Band 30 -95.3 -100.5 10MHz Bandwidth Band 66 -95.8 -101 10MHz Bandwidth Band 38 -96.3 -101 10MHz Bandwidth Band 39 -96.3 -101.5 10MHz Bandwidth Band 40 -96.3 -100.5 10MHz Bandwidth Band 41 -94.
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4.6 Antenna Design The L850 module provides main and diversity antenna interfaces, and the antenna design requirements are shown in the following table: L850 Module Main Antenna Requirements Frequency range The most proper antenna to adapt the frequencies should be used.
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L850 Module Main Antenna Requirements LTE band 40(2300): 100 MHz LTE band 41(2500): 194 MHz GPS: 2 MHz Bandwidth(GNSS) GLONASS: 8 MHz BDS: 4 MHz Impedance 50Ω Input power > 26dBm average power WCDMA & LTE Recommended standing-wave ratio (SWR) ≤ 2: 1 Note: ANT on B30 suggestion: Peak gain < 0dBi, for FCC EIRP requirement, Efficient > 50% for carrier TRP requirement. If integrator doesn't follow the instruction, Fibocom doesn't take responsibility. Reproduction forbidden without Fibocom Wireless Inc.
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5 Structure Specification 5.1 Product Appearance The product appearance for L850 module is shown in Figure5-1: Figure 5-1 Module appearance 5.2 Dimension of Structure The structural dimension of the L850 module is shown in Figure 5-2: Figure 5-2 Dimension of structure Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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5.3 M.2 Interface Model The L850 M.2 module adopts 75-pin gold finger as external interface, where 67 pins are signal pins and 8 pins are notch pins as shown in Figure 3-1. For module dimension, please refer to 5.2 Dimension of Structure. Based on the M.2 interface definition, L850 module adopts Type 3042-S3-B interface (30x42mm, the component maximum height on t top layer is 1.5mm, PCB thickness is 0.8mm, and KEY ID is B). Figure 5-3 M.2 interface model 5.4 M.
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Figure 5-4 M.2 dimension of structure 5.5 Storage 5.5.1 Storage Life Storage Conditions (recommended): Temperature is 23 ± 5°C, relative humidity is less than RH 60%. Storage period: Under the recommended storage conditions, the storage life is 12 months. 5.6 Packing The L850 module uses the tray sealed packing, combined with the outer packing method using the hard cartoon box, so that the storage, transportation and the usage of modules can be protected to the greatest extent.
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Other L850(except L850-GL-01 serial) module uses tray package, 20 pcs are packed in each tray, with 5 trays including one empty tray on top in each box and 6 boxes in each case. Tray packaging process is shown in Figure 5-6: Figure 5-6 Tray packaging process Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
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5.6.2 Tray Size The pallet size of L850 module is 315×170×6.5mm, as shown in Figure 5-7: Figure 5-7 Tray size (unit: mm) ITEM DIM (Unit: mm) L 315.0±2.0 W 170.0±2.0 H 6.5±0.3 T 0.8±0.1 A 43.0±0.3 B 31.0±0.3 C 79.0±0.2 D 60.0±0.2 E 180.0±0.2 F 60.0±0.2 G 40.0±0.2 Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.