TR6260 DATASHEET 802.11b/g/n Wi-Fi Single Chip Beijing Eswin Technology Co.
Release Notes Data Version Release Notes 2018.10 V1.0 release 2018.12 V2.0 Update 3.6 chapter 2019.5 V2.1 Update pinlist and package information 2019.7 V2.2 Update pin defination Beijing Eswin Technology Co.
Contents 1. Overview ......................................................................................................................................... 1 1.1 Wi-Fi ...................................................................................................................................... 1 1.2 MCU and Advanced Features ................................................................................................ 1 1.3 2. 1.2.1 CPU and Memory ........................................
2.7 3. 4. Low-Power Management ....................................................................................................... 6 Peripheral Interface ......................................................................................................................... 6 3.1 General Purpose Input / Output Interface (GPIO).................................................................. 6 3.2 Analog-to-Digital Converter (ADC) ..................................................................
1. Overview The SoC is a 2.4GHz IEEE 802.11b/g/n Wi-Fi single chip solution with standard security features. With optimized power and RF performance, robustness, versatility, reliability, various power profiles, full features and functions, the chip is designed for a wide variety of applications, including Smart home, Wearable devices and IoT (Internet of Things). It integrates a 32-bit microcontroller, 802.11b/g/n Wi-Fi baseband, a 2.
• A-MPDU and A-MSDU aggregation • Block ACK • Wi-Fi Protected Access (WPA)/WPA2/WPA2-Enterprise/Wi-Fi Protected Setup (WPS) • SoftAP mode • BT-Coexistence interface 1.2 MCU and Advanced Features 1.2.1 CPU and Memory • 32-bit, up to 160MHz • Instruction cache controller with 8KB cache RAM memory • support XIP(executed in place) • Flash, 1 Mbytes 1.2.2 Clocks and Timers • PLL to generate a high frequency clock (typically 160 MHz) • Internal 32kHz RC oscillator • External 40 MHz crystal oscillator 1.2.
• SDIO 2.0(up to 4bit) @ 50MHz • Up to 6-channel HW PWM output • 4-channel ADC with 14-bit ENOB • 1 PGA 1.2.4 Security • IEEE 802.11 standard security features all supported, including CCMP, WPA/WPA2 • eFuse encryption • Cryptographic hardware acceleration: – AES – Random Number Generator (RNG) 1.
• Wi-Fi location-aware devices • Security ID tags • Healthcare – Proximity and movement monitoring trigger devices – Temperature sensing loggers 2. Block Diagram 2.1 Function block diagram PHY Security Accelerator RN generate MAC RTC PWM/Timer (6 channel) I2C Pad_ctrl UART0 CRPM UART1 PCU UART2 Temp sensor DMAC Process sensor SPI0 RAM 32 bit processor Antenna ROM SPI1 SDIO WATCH DOG Transceiver/ABB PMU GPIO ADC/PGA I2S Figure 2-1 TR6260 functional block diagram 2.
• Dynamic branch prediction • 16/32/64/128-entry BTB • Return address stack • 2/4 entries • Vector interrupts for internal/external interrupt controller • 2/6/10/16/24/32 hardware vector interrupt signals • Fixed/Programmable interrupt level • Edge/Level interrupt trigger type • 2/3 HW-level nested interruption • Address space up to 4GB • Radix-4 divider support • HW stack protection support • Processor Status bus support • PowerBrake support 2.2.
2.3.1 Watchdog Timers The watchdog timer provides a two-stage mechanism to prevent a system from lock-up. The first stage is called “interrupt stage”. If the watchdog interrupt is enabled and the watchdog timer is not restarted during the interrupt stage, the interrupt signal, wdt_int , will be asserted. The second stage, reset stage, begins right after the interrupt stage.
2.5.1 2.4 GHz Receiver The 2.4 GHz receiver down-converts the 2.4 GHz RF signal to quadrature baseband signals and converts them to the digital domain with 2 high-resolution, high-speed ADCs. To adapt to varying signal channel conditions, RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits and baseband filters are integrated within TR6260. 2.5.2 2.4 GHz Transmitter The 2.4 GHz transmitter up-converts the quadrature baseband signals to the 2.
The clock generator has built-in calibration and self test circuits. Quadrature clock phases and phase noise are optimized on-chip with patented calibration algorithms to ensure the best performance of the receiver and transmitter. 2.6 Wi-Fi Wi-Fi Baseband block • Full IEEE 802.11b/g/n legacy compatibility with enhanced performance. • Support 20/40MHz channel with optional SGI (64QAM Modulation). • 802.11b modulations:DSSS with DBPSK/DQPSK, 1Mbps/2Mbps, and CCK, 5.5, 11Mbps. • 802.
• AMPDU/AMSDU aggregation including block ACK. 2.7 Low-Power Management With the advanced power management technologies, TR6260 can switch between different power modes. • Power mode – SHUTDOWN mode – DEEPSLEEP mode – LIGHTSLEEP mode – IDLE mode 3. Peripheral Interface 3.1 General Purpose Input / Output Interface (GPIO) TR6260 has up to 18 GPIO pins which can be assigned to various functions by programming the appropriate registers.
3.2 Analog-to-Digital Converter (ADC) TR6260 integrates 12-bit SigmaDelta ADCs and supports measurements on 4 channels (analog enabled pins) to sample battery voltage, temperature sensor and external analog input. 3.3 SD/SDIO/MMC Host Controller This SDIO can act as SDIO/SD/MMC device, with connecting to SDIO host. CPU can write or read SDIO register and The CPU or DMAC can write or read SDIO data .
of the interfaces can be accessed by the DMA controller or directly by CPU. 3.5 I2C Interface TR6260 has I2C bus interfaces which can serve as I2C master or slave depending on the user’s configuration. The I2C interfaces support: • Standard mode (100 kbit/s) • Fast mode (400 kbit/s) • Up to 5 MHz, but constrained by SDA pull up strength • 7-bit/10-bit addressing mode • Dual addressing mode Users can program command registers to control I2C interfaces to have more flexibility. 3.
waveform for one PWM channel. The dedicated capture sub-module can accurately capture external timing events. 3.8 Serial Peripheral Interface (SPI) SPI is a Serial Peripheral Interface (SPI) controller which serves as a SPI master or a SPI slave. As a SPI master, the controller connects various SPI devices. As a SPI slave, the controller responds to the master requests for data exchange.this system support 2 spi interface. The SPI controller can act as a SPI master initiating SPI transfers on the SPI bus.
Figure 5-1 TR6260 Pin definition Pin Name Type Function 1 TEST_MODE I/O TESTMODE/GPIO16 TESTMODE=1 will enter DFT TESTMODE=0 normal mode 2 XTAL_I AI 40M XTAL N 3 XTAL_O AI 40M XTAL P 4 RESETB I RESETB 5 TOUT2 AI/DI/DO ADC IN2/BOOTMODE0/ GPIO14 6 TOUT3 AI/DI/DO ADC IN3/BOOTMODE1/GPIO15 7 UART0_RXD I/O UART0 RXD/GPIO5/SPI0_CS0 /SPI0_HOLD 8 UART0_TXD I/O UART0_TXD/GPIO6/SPI0_MOSI/ MSPI_CS1/SPI0_WP 9 SD_DATA0 Beijing Eswin Technology Co.
/MSPI_MOSI/UART0_TXD 10 SD_DATA1 I/O SD_DATA1/GPIO8/MSPI_MISO/S PI0_CS1 11 SD_DATA2 I/O SD_DATA2/GPIO9/MSPI_WP/I2C _SCL/UART1_RXD 12 SD_DATA3 I/O SD_DATA3/GPIO10/MSPI_HOLD/ I2C_SDA/UART1_TXD 13 SD_CLK I/O SD_CLK/GPIO11/MSPI_CLK/UA RT1_RXD 14 SD_CMD I/O SD_CMD/GPIO12/MSPI_CS0/UA RT1_TXD 15 TCK I/O JTAG TCK/GPIO0/SPI0_CLK/PWM_CT RL0/UART0_RXD/I2S_TXSCK/I2 C_SCL 16 TMS I/O JTAG TMS/GPIO1/SPI0_CS0/PWM_CTR L1/I2S_RXD/I2C_SDA 17 TDO I/O JTAG TDO/ GPIO2/UART1_RXD/SPI0_MOSI/ PWM_CTR
capacitor to this pin 22 VDD_BUCK PI BUCK POWER Supply, Please add 10uf+0.1uf capacitor to this pin 23 BUCK_FB PI BUCK POWER Feedback 24 LX PI 1V45 Buck switch 25 POWERKEY AI Chip Power key, add 26 VDD_VBAT1 PI Low power LDO power supply, to 3.3V typical is 3.3V, please add 0.1uf to this pin 27 VDD_1P45_DIG PI 1.45V power supply ， please connect to Buck FB(pin) if DCDC is used, please add 0.1uf capacitor to this pin.
to this pin 4.
000 BOOTMODE0 BOOTMODE Select 001 GPIO14 General purpose use 14 010 TOUT2 External ADC input, please make sure the ADC input voltage is within 3.3V, the ADC input can only support 1.2V, if the ADC input is 3.3V, please make sure the ADC DIV is 4 011 TOUT2 External ADC input, please make sure the ADC input voltage is within 3.3V, the ADC input can only support 1.2V, if the ADC input is 3.
the ADC input is 3.3V, please make sure the ADC DIV is 4 011 TOUT3 External ADC input, please make sure the ADC input voltage is within 3.3V, the ADC input can only support 1.2V, if the ADC input is 3.
011 SPI0_CS0 SPI0 Chip Select 0 100 PWM_CTRL1 Pulse Width Modulation 1 101 BT_ACTIVE BT/WIFI coexistence：BT Active 110 I2S_RXD IIS Received Data 111 I2C_SDA IIC Serial Data Truth table Function name Function 000 JTAG_TDO JTAG Data Output 001 GPIO2 General purpose use 2 010 UART1_RXD UART1 Data Received 011 SPI0_MOSI SPI0 Master Output Slave input 100 PWM_CTRL2 Pulse Width Modulation 2 101 BT_PRIORITY BT/WIFI coexistence：BT Priority 110 I2S_RXWS IIS Received Word Select
101 WIFI_ACTIVE BT/WIFI coexistence：W IFI active 110 I2S_RXSCK IIS Received data clock 111 UART2_TXD UART2 Data Transmitted Truth table Function name Function 000 JTAG_TRST JTAG Test Reset input 001 GPIO4 General purpose use 4 010 SPI0_CLK SPI0 Clock 011 SPI0_CS1 SPI0 chip select 1 100 PWM_CTRL4 Pulse Width Modulation 4 101 WIFI_PRIORITY BT/WIFI coexistence：W IFI priority 110 I2S_MCLK IIS Main clock output Truth table Function name Function 000 UART0_RXD UART0 Data Recei
001 GPIO6 General purpose use 6 010 SPI0_MOSI SPI0 Master output Slave input 011 MSPI_CS1 Main SPI chip select 1 100 SPI0_WP SPI0 flash Write protect 101 COLD_RESET Cold reset Truth table Function name Function 000 SD_DATA0 SDIO Data0 001 GPIO7 General purpose use 7 010 UART0_CTS UART0 Clear to send 011 MSPI_MOSI Main SPI master output slave input 100 USRT0_TXD UART0 Data transmitted Truth table Function name Function 000 SD_DATA1 SDIO Data1 001 GPIO8 General purpose
011 MSPI_WP Main SPI write protect 100 I2C_SCL IIC Serial Clock 101 UART1_RXD UART1 Received data SD_DATA3 Truth table Function name Function 000 SD_DATA3 SDIO Data3 001 GPIO10 General purpose use 10 010 UART1_DTR UART1 Data terminal ready 011 MSPI_HOLD Main SPI Hold enable 100 I2C_SDA IIC Serial Data 101 UART1_TXD UART1 Transmitter data SD_CLK Truth table Function name Function 000 SD_CLK SDIO Data Clock 001 GPIO11 General purpose use 11 010 UART1_RTS UART1 Request
100 UART1_TXD UART1 Transmitted data 101 32K_CLK_IN 32K RTC Clock external input Truth table Function name Function 000 WAKEUP Chip wakeup 001 GPIO13 General purpose use 13 010 I2S_TXD IIS Transmitter Data 011 SPI0_MISO SPI0 Master input slave output 100 PWM_CTRL5 Pulse Width Modulation 5 101 32K_CLK_OUT 32K RTC clock output 110 PHY_ENTRX indicate rf txon and rxon Truth table Function name Function 000 GPIO21 General purpose use 21 001 UART0_TXD UART0 Transmitted data
Parameter Symbol Min Type Max Unit Input low voltage VIL -0.3 0.3*VIO V Input high voltage VIH 0.7*VDDIO 3.6 V Output low voltage VOL -0.3 0.3*VIO V Output high voltage VOH 0.7*VDDIO 3.6 V Input pin capacitance Cpad 2 pF VDDIO VIO 3.6 V Maximum driver capability IMAX 12 mA 105 °C 3.0 Operation temperature range TSTR 3.3 3.3 -40 5.
Tx 802.11g, OFDM 54Mbps, POUT=+16dBm 165.0 mA Tx 802.11n, MCS7, POUT=+14dBm 160.0 mA Rx 802.11b, 1024 bytes packet length， -80dBm 60.0 mA Rx 802.11g, 1024 bytes packet length， -70dBm 60.0 mA Rx 802.11n, 1024 bytes packet length， -65dBm 60.0 mA Light sleep 1.0 mA Deep sleep 12.0 uA DTIM4 1.0 mA POWER OFF 0.4 uA 5.
Second-Order Input Intermodulation 45 dBm Intercept Point LO Leakage -90 dBm Quadrature Gain Error 0.5 dB Quadrature Phase Error 1 deg EVM -28 dB Input S11 -10 dB 1Mbps CCK -97.0 dBm 11Mbps CCK -88.0 dBm 6Mbps OFDM -91.0 dBm 54Mbps OFDM -74.0 dBm HT20,MCS0 -90.7 dBm HT20,MCS7 -70.6 dBm HT40,MCS0 -86.6 dBm HT40,MCS7 -69.0 dBm Maximum Receive Level 0 dBm RX Sensitivity Rx Blocking TBD Requirements Rx power on settle time Rx AGC time Beijing Eswin Technology Co.
Rx settle time when <300 ns 3 dB gain adjusted Rx RSSI accuracy 5.5 TX Specifications Table 5-5 TX Specifications Sym bol Parameter Min Type Max Unit Test Conditions/Com ments TRANSMITTER Power Control Range 30 dB Power Control Resolution 1 dB Support Channel BandWidth 20 Output S22 -8 -10 16.5 17.0 20.0 dBm 1Mbps CCK 13.0 13.5 14.0 dBm 6Mbps OFDM 12.0 12.5 13.
Parameter Symbol Min Frequency Range FVCO Frequency Offset Typ Max Unit 6400 6800 MHz -10 10 ppm Frequency Step Integrated Phase Noise 9.6 0.5 PLL locking time Start time 6. 20 50 Package Information Beijing Eswin Technology Co.
Figure 6-1 TR6260 package Information Beijing Eswin Technology Co.
FCC Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
