SOM Hardware Reference Manual Confidentiality Notice Copyright (c) 2019 eInfochips. - All rights reserved This document is authored by eInfochips and is eInfochips intellectual property, including the copyrights in all countries in the world. This document is provided under a license to use only with all other rights, including ownership rights, being retained by eInfochips.
SOM Hardware Reference Manual Contents 1 Document Details.................................................................................................................................. 7 1.1 Document History ......................................................................................................................... 7 1.2 Definition, Acronyms and Abbreviations ...................................................................................... 7 1.3 References .......................
SOM Hardware Reference Manual 7 6.3.5 Audio Interface.................................................................................................................... 35 6.3.6 Sensors ................................................................................................................................ 39 6.3.7 Micro SD Card ..................................................................................................................... 39 6.3.8 DSI to HDMI.........................
SOM Hardware Reference Manual List of Figures Figure 1 – ERAGON 624 SOM Block Diagram ............................................................................................ 17 Figure 2 – ERAGON624 SOM Top View...................................................................................................... 18 Figure 3 – ERAGON624 SOM BOT View .....................................................................................................
SOM Hardware Reference Manual List of Tables Table 1: Document History ........................................................................................................................... 7 Table 2 : Definition, Acronyms and Abbreviations ....................................................................................... 9 Table 3 : References ....................................................................................................................................
SOM Hardware Reference Manual 1 Document Details 1.1 Document History Version Author Name 1.0 eInfochips Reviewer Date 18-July 19 Name Review Comment ID Approver Name eInfochi ps Date Description Of Changes Initial release Table 1: Document History 1.
SOM Hardware Reference Manual HDMI High Definition Multimedia Interface I2C Inter-Integrated Circuit IC Integrated Circuit Inc.
SOM Hardware Reference Manual UART Universal Asynchronous Interface USB Universal Serial Bus ADB Android Debug Bridge WLAN Wireless LAN Table 2 : Definition, Acronyms and Abbreviations Version 1.
SOM Hardware Reference Manual 1.3 References No. Document Version 1 ERAGON624 SOM Schematic File 1.3 2. ERAGON624 Carrier Schematic File 1.3 Remarks Table 3 : References Version 1.
SOM Hardware Reference Manual 2 License Agreement The use of this document is subject to and governed by those terms and conditions in the eInfochips Ltd. Purchase and Software License Agreement for the APQ8053 based development platform, which you or the legal entity you represent, as the case may be, accepted and agreed to when purchasing ERAGON624 development platform from eInfochips Ltd. (“Agreement”).
SOM Hardware Reference Manual 3 Preface This document provides an overview of the ERAGON624 SOM based on Qualcomm’s APQ8053 SoC. It provides step-by-step information about hardware components and associated software release Android 8.1.0 (Oreo) used with Carrier KIT. Intended Audience This document is intended for technically qualified personnel. It is not intended for general audiences.
SOM Hardware Reference Manual 4 Overview The ERAGON624 SoM provides an ideal building block for simple integration with a wide range of products in target markets requiring rich multimedia functionality, powerful graphics processing and video capabilities, as well as high-processing power, in a compact, RoHS compliant, fan less, cost effective SoM with low power consumption.
SOM Hardware Reference Manual Key Features CPU Qualcomm Snapdragon 624 Octa-core ARM® Cortex® A53 at up to 1.8 GHz per core. Both quad’s with 512KB L2 cache 64-Bit processor Qualcomm Adreno 506 GPU. 1920 x 1080p video encoding/ decoding capability Dual 14 bit ISP(Image Signal Processing) Qualcomm Hexagon™ DSP Memory RAM: Up to 4GB LPDDR3 at up to 933 MHz clock Storage: Up to 64 GB eMMC Camera 3xMIPI CSI 4 Lane Camera Interface (Only two can work simultaneously).
SOM Hardware Reference Manual Applications The ERAGON624 SoM is used in a wide range of products across many different target markets.
SOM Hardware Reference Manual 5 Getting Started Prerequisites Before user power up the ERAGON 624 SOM board for the first time, will need following things: Eragon 624 Carrier Board or Carrier Board with Exact Pin-outs and mating connectors WiFi BT U.
SOM Hardware Reference Manual 6 System Block Diagram Figure 1 – ERAGON 624 SOM Block Diagram Version 1.
SOM Hardware Reference Manual ERAGON624 BOARD IMAGE Figure 2 – ERAGON624 SOM Top View Figure 3 – ERAGON624 SOM BOT View Version 1.
SOM Hardware Reference Manual The ERAGON 624 SOM offers a wide boost of interfaces and peripherals, including several high-speed signals through its edge connectors. The ERAGON624 SOM and Carrier are interfaced through three Hirose DF40C-100DP-0.4V Connectors. The pin outs for these three connectors is described below, SOM Pin No. J5.1 J5.2 J5.3 J5.4 J5.5 J5.6 J5.7 J5.8 J5.9 J5.10 J5.11 J5.12 J5.13 J5.14 J5.15 J5.16 J5.17 J5.18 J5.19 J5.20 J5.21 J5.22 J5.23 J5.24 J5.25 Version 1.
SOM Hardware Reference Manual SOM Pin No. Carrier Board Pin Number Signal Name Default Pin Function Operating Voltage Level J5.26 J11.26 MIPI_CSI2_LANE0_P MIPI CSI2 Lane0 Positive - J5.27 J11.27 MIPI_CSI1_LANE1_P MIPI CSI1 Lane 1 Positive - J5.28 J11.28 GND Ground - J5.29 J11.29 MIPI_CSI1_LANE1_N MIPI CSI1 Lane 1 Negative - J5.30 J11.30 MIPI_CSI2_LANE2_P MIPI CSI2 Lane 2 Positive - J5.31 J11.31 GND Ground - J5.32 J11.
SOM Hardware Reference Manual SOM Pin No. Signal Name Default Pin Function Operating Voltage Level J5.51 Carrier Board Pin Number J11.51 MIPI_CSI0_LANE0_N MIPI CSI0 Lane0 Negative - J5.52 J11.52 GND Ground - J5.53 J11.53 MIPI_CSI0_LANE0_P MIPI CSI0 Lane0 Positive - J5.54 J11.54 MIPI_DSI1_LANE1_P MIPI DSI1 Lane1 Positive - J5.55 J11.55 GND Ground - J5.56 J11.56 MIPI_DSI1_LANE1_N MIPI DSI1 Lane1 Negative - J5.57 J11.57 MIPI_CSI0_LANE1_P MIPI CSI0 Lane1 Positive - J5.
SOM Hardware Reference Manual SOM Pin No. Signal Name Default Pin Function Operating Voltage Level J5.76 Carrier Board Pin Number J11.76 GND Ground - J5.77 J11.77 CSI1_PWDN CSI1 Power Down GPIO Signal 1.8V J5.78 J11.78 MIPI_DSI0_LANE0_N MIPI DSI0 Lane0 Negative - J5.79 J11.79 CSI_I2C1_SCL CCI1 Camera I2C Clock Signal 1.8V J5.80 J11.80 MIPI_DSI0_LANE0_P MIPI DSI0 Lane0 Positive - J5.81 J11.81 CSI_I2C1_SDA CCI1 Camera I2C Data Signal 1.8V J5.82 J11.82 GND Ground - J5.
SOM Hardware Reference Manual SOM Pin No. Signal Name Default Pin Function Operating Voltage Level J4805.1 Carrier Board Pin Number J13.1 VBAT 3.5V-4.4V Input voltage 3.8 J4805.2 J13.2 VBAT 3.5V-4.4V Input voltage 3.8 J4805.3 J13.3 VBAT 3.5V-4.4V Input voltage 3.8 J4805.4 J13.4 VBAT 3.5V-4.4V Input voltage 3.8 J4805.5 J13.5 VBAT 3.5V-4.4V Input voltage 3.8 J4805.6 J13.6 VBAT 3.5V-4.4V Input voltage 3.8 J4805.7 J13.7 VBAT 3.5V-4.4V Input voltage 3.8 J4805.8 J13.
SOM Hardware Reference Manual SOM Pin No. Signal Name Default Pin Function Operating Voltage Level J4805.26 Carrier Board Pin Number J13.26 GND Ground - J4805.27 J13.27 VBUS_USB_IN 5 J4805.28 J13.28 GND USB Input from the USB 3.0 Connector Ground J4805.29 J13.29 VBUS_USB_IN 5 J4805.30 J13.30 VSENSE_BATT_M J4805.31 J13.31 VBUS_USB_IN J4805.32 J13.32 VSENSE_BATT_P J4805.33 J13.33 VBUS_USB_IN J4805.34 J13.34 VREF_BAT_THERM J4805.35 J13.
SOM Hardware Reference Manual SOM Pin No. Carrier Board Pin Number J4805.51 J13.51 Signal Name Default Pin Function Operating Voltage Level USB_HS_D_M USB2.0 High speed negative - J4805.52 J13.52 PMIC_SPKR_DRV_P PMIC speaker out positive - J4805.53 J13.53 USB_HS_D_P USB2.0 High speed positive - J4805.54 J13.54 PMIC_MIC3_IN_P PMIC MIC3 Input positive J4805.55 J13.55 GND Ground - J4805.56 J13.56 PMIC_MIC3_IN_M PMIC MIC3 Input negative - J4805.57 J13.
SOM Hardware Reference Manual SOM Pin No. Signal Name Default Pin Function Operating Voltage Level J4805.76 Carrier Board Pin Number J13.76 EAR0_P Earpiece out positive - J4805.77 J13.77 USB_CC2 USB type C input CC2 - J4805.78 J13.78 TX_GTR_THRES GPIO_112 1.8 J4805.79 J13.79 USB_ID PMI USB ID input 1.8 J4805.80 J13.80 CDC_LO_M Codec Lineout negative - J4805.81 J13.81 GND Ground - J4805.82 J13.82 CDC_LO_P Codec Lineout positive - J4805.83 J13.
SOM Hardware Reference Manual SOM Pin No. Signal Name Default Pin Function Operating Voltage Level J4804.1 Carrier Board Pin Number J16.1 DSI_TOUCH_INT Display touch interrupt 1.8 J4804.2 J16.2 GND Ground - J4804.3 J16.3 TOUCH_RST Display touch reset 1.8 J4804.4 J16.4 APQ_BOOT_CONFIG1 Boot config pin 1 1.8 J4804.5 J16.5 FLASH_STROBE_NOW PMI_MPP_4/Flash strobe - J4804.6 J16.6 APQ_BOOT_CONFIG3 Boot config pin 3 1.8 J4804.7 J16.7 LCD_RST_N Display Reset 1.8 J4804.8 J16.
SOM Hardware Reference Manual SOM Pin No. Signal Name Default Pin Function Operating Voltage Level J4804.26 Carrier Board Pin Number J16.26 BLSP1_SPI_CLK BLSP1 SPI clock 1.8 J4804.27 J16.27 SD_WRITE_PROTECT Test point 1.8 J4804.28 J16.28 BLSP5_UART_TX BLSP5 UART TX 1.8 J4804.29 J16.29 GND Ground - J4804.30 J16.30 BLSP5_UART_RTS BLSP5 UART RTS 1.8 J4804.31 J16.31 USB_SS_SEL USB switch select 1.8 J4804.32 J16.32 SPKR_AMP_EN2 Speaker amplifier Enable 2 1.8 J4804.33 J16.
SOM Hardware Reference Manual SOM Pin No. Carrier Board Pin Number J4804.51 J16.51 Signal Name Default Pin Function Operating Voltage Level ALSP_INT_N ALSP sensor interrupt 1.8 J4804.52 J16.52 MI2S_2_D1 MI2S2 Data1 1.8 J4804.53 J16.53 GND Ground - J4804.54 J16.54 MI2S_2_WS MI2S2 Word Sync clock 1.8 J4804.55 J16.55 VREG_L5_1P8 PMIC LDO5 output 1.8 J4804.56 J16.56 MI2S_2_SCK MI2S2 clock 1.8 J4804.57 J16.57 VREG_L5_1P8 PMIC LDO5 output 1.8 J4804.58 J16.
SOM Hardware Reference Manual SOM Pin No. Signal Name Default Pin Function Operating Voltage Level J4804.76 Carrier Board Pin Number J16.76 BLSP6_I2C_SDA BLSP6 I2C Data 1.8 J4804.77 J16.77 KEY_SNAPSHOT GPIO86/HDMI Hot Plug detect 1.8 J4804.78 J16.78 BLSP6_I2C_SCL BLSP6 I2C clock 1.8 J4804.79 J16.79 KEY_VOL_UP_N GPIO85/ Volume Up key 1.8 J4804.80 J16.80 BLSP6_UART_TX BLSP6 UART transmit 1.8 J4804.81 J16.81 BLSP8_SPI_CS0_N BLSP8 SPI CS0 1.8 J4804.82 J16.
SOM Hardware Reference Manual Major Blocks of ERAGON624 SOM Module 6.2.1 Processor APQ8053 - Features and interfaces The Qualcomm APQ8053 includes a customized 64-bit ARM Cortex-A53, 1.8GHz high performance Octacore Processor. It embraces Qualcomm AdrenoTM 506 Graphics Processing Unit; up to 650MHz 3D graphics accelerator with 64-bit addressing. Qualcomm HexagonTM DSP to support always-on use cases.
SOM Hardware Reference Manual Wireless Connectivity With WCN3680B, it supports 802.11 b/g/n mode for 2.4GHz band and with external FEM module; it supports 802.11 a/n/ac mode for 5GHz band. WCN3680B also supports Bluetooth 4.2 LE and earlier. With WGR7640 receiver, APQ8053 supports GPS location suite. Power Management 6.2.2 Combination of PM8953 and PMI8952 interfaced through two 2-line SPMI. Dedicated clock and reset lines; plus other GPIOs as needed.
SOM Hardware Reference Manual 6.2.5 PMIC Interface ERAGON624 SOM module has combination of PM8953 and PMI8952 for Power management. Both the PMICs are interfaced to APQ8053 through two-line SPMI bus. 6.2.6 System LEDs There are three notification LEDs provided on SOM module as described below, 6.2.7 LED2 (APQ reset out LED): It’s glow indicates that processor came out of reset and booted successfully. LED3 (Charging LED): Indicates battery charging.
SOM Hardware Reference Manual Guidelines to Design Carrier Board 6.3.1 Power Supply ERAGON624 SOM can be powered through 3.8V@4.2A DC input to give power to VBAT pins (as per pinouts table between SOM & Carrier). 6.3.2 Boot Configuration The ERAGON624 can be configured to function in different modes placing the switch on carrier card.
SOM Hardware Reference Manual Figure 5 – Boot Configuration Switch (SW1) 6.3.3 General Purpose Keys (as per Eragon624 Carrier Board) There are three general-purpose keys provided on carrier card. Their applications are as below, SW6 (Power ON/Sleep mode switch): After power ON the board, this key need to be press for 2-3 seconds to boot SOM module. Also if board goes in the sleep mode, then by pressing SW6 we can get board out of sleep mode.
SOM Hardware Reference Manual ERAGON624 supports 5 analog MICs,1 headset MIC, 3 Digital MICs, 2 stereo speaker outputs, 1 headset output, 1 Earpiece output, 2 Line outputs and all these peripherals excluding can be connected on headset connector J19, Female headers J17 & J18. These Provisions can be given to carrier board for Audio interfaces. Figure 7 – WCD9335 Audio Code Daughter Board (custom made by eInfochips) Below is the Schematic portion for J28 & J29 to connect the Audio Daughter Board.
SOM Hardware Reference Manual Figure 9 – Schematic-2 on Carrier Board for Audio Code Daughter Board Figure 10 – Audio Headset Jack Figure 11 – Audio Headset Jack schematic Version 1.
SOM Hardware Reference Manual Below is the Pinout Specification of Headset Jack, Pin Number Net Name J19.1 J19.2 J19.3 J19.4 J19.5 J19.6 CONN_CDC_MIC2_P CDC_HPH_L CDC_HPH_R CDC_HPH_REF MBHC NP Pin Function MIC2 Input Positive Headphone Left Channel Headphone Right Channel Headphone Reference Signal (Ground) Headset Detect Signal Connected to Ground Table 5: Headset (J19) Pinout Figure 12 – Analog and Digital Codec Headers (J17 & J18) Below is the Pinout Specification of J17, Pin Number J17.1 J17.2 J17.
SOM Hardware Reference Manual J17.16 CDC_SPEAKER2_OUT_M Speaker2 Output Negative Table 6: Audio Header (J17) Pinout Below is the Pinout Specification of J18, Pin Number Net Name J18.1 J18.2 J18.3 J18.4 J18.5 J18.6 J18.7 J18.8 J18.9 J18.10 J18.11 J18.12 J18.13 J18.14 J18.15 J18.
SOM Hardware Reference Manual Figure 13 – Micro SD card connector schematic for carrier 6.3.8 DSI to HDMI The Qualcomm APQ8053 Processor does not include a built-in HDMI interface. The ERAGON624 has the built-in MIPI-DSI 4 lanes interface, which is used, as a source for the HDMI output. A DSI to HDMI Bridge Board can be used to performs this task and it supports a resolution from 480p to 720p at 30Hz.
SOM Hardware Reference Manual A 3-wire (audio out only) I2S channel is routed directly from the APQ8053 SoC I2S interface pins to the DSI-HDMI bridge Board through HDMI Audio connector. Figure 14 – DSI to HDMI Audio Connector J26 Pin specifications for J26 is mentioned below, Pin Number Net Name Pin Function J26.1 J26.2 J26.3 J26.4 J26.5 J26.6 J26.7 J26.8 J26.9 J26.10 J26.11 J26.12 J26.13 J26.
SOM Hardware Reference Manual Figure 15 – HDMI to CSI Audio Connector J27 Pin specifications for J27 is mentioned below, Pin Number Net Name J27.1 J27.2 J27.3 J27.4 J27.5 J27.6 J27.7 J27.8 J27.9 J27.10 J27.11 J27.12 J27.13 J27.14 J27.15 J27.16 VCC_3V3 VCC_3V3 VREG_L2_1P1 VCC_1V8 HDMI_I2C_SDA HDMI_I2C_SCL MI2S_1_SCK MI2S_1_WS MI2S_1_D3 MI2S_1_D2 MI2S_1_D1 MI2S_1_D0 HDMI_INT_GPIO HDMI_RST_N GND GND Pin Function 3.3V Supply 3.3V Supply 1.2V Supply 1.
SOM Hardware Reference Manual Figure 16 – Routing of UFL cable from SOM to Carrier 6.3.11 GPS chip antenna GPS receiver signal received from GPS chip antenna 1575AT54A0010E mounted on Carrier card (ref ANT1) after passing through SAW filter and LNA is routed to SOM module through U.FL-to-U.FL cable connected from connector J21 at Carrier Card to connector J1 at SOM module. Figure 17 – Routing of UFL cable from SOM to Carrier 6.3.12 M.
SOM Hardware Reference Manual Figure 18 – M.2 connector (J35) Figure 19 – SIM card connectors (J38 & J36) Pinout specifications of J35 are below, Pin Number Net Name Pin Function J35.1 CONFIG_3 J35.2 J35.3 J35.4 J35.5 J35.6 J35.7 J35.8 J35.9 J35.10 J35.11 J35.12 J35.13 J35.14 J35.15 J35.16 J35.17 J35.18 J35.19 J35.20 VCC_3V7_LTE GND VCC_3V7_LTE GND LTE_MODEM_POWER USBDN_DP2 LTE_MODEM_W_DISABLE#1 USBDN_DM2 LTE_MODEM_LED#1 GND NC NC NC NC NC NC NC NC MI2S_2_SCK Version 1.0 - 44 - DNP Pull up (1.
SOM Hardware Reference Manual J35.21 J35.22 J35.23 J35.24 J35.25 J35.26 J35.27 J35.28 J35.29 J35.30 Pin Number J35.31 J35.32 J35.33 J35.34 J35.35 J35.36 J35.37 J35.38 J35.39 J35.40 J35.41 J35.42 J35.43 J35.44 J35.45 J35.46 J35.47 J35.48 J35.49 J35.50 J35.51 J35.52 J35.53 J35.54 J35.55 J35.56 J35.57 J35.58 J35.59 J35.60 J35.61 J35.62 Version 1.
SOM Hardware Reference Manual J35.63 J35.64 J35.65 J35.66 J35.67 J35.68 J35.69 J35.70 TP28 BLSP4_UART_RX TP29 SIM1_DETECT LTE_MODEM_RST# NC CONFIG_1 VCC_3V7_LTE_RF Pin Number Test Point Coexistence UART Receive Test Point SIM Card _1 Detect Signal Modem Reset Signal Not Connected DNP Pull Up (1.8V) Option 3.7V LTE RF Power Supply Net Name J35.71 J35.72 J35.73 J35.74 J35.75 Pin Function GND VCC_3V7_LTE_RF GND VCC_3V7_LTE_RF CONFIG_2 Ground 3.7V LTE RF Power Supply Ground 3.
SOM Hardware Reference Manual 6.3.13 RTC For Time and Date update, ERAGON624 has a support to connect external rechargeable Coin Cell battery on connector J8 at Carrier card. Connect +Ve terminal of battery to J8.1 pin and GND to J8.2 pin. Figure 20 – RTC connector (J8) 6.3.14 Debug Port ERAGON624 support a debug Port to capture the system logs. Carrier card has on board UART to USB converter chip FT230XQ-R (U55).
SOM Hardware Reference Manual 7 Electrical Specification Absolute Maximum Ratings Parameter Min Max Unit VBATT+ Main Battery Input Supply Voltage -0.3 6.0 V VCOIN RTC Input Supply Voltage -0.5 3.5 V USB_VBUS USB VBUS Input Supply Voltage -0.3 28 V Table 14 : Absolute Maximum Ratings Operating Conditions Parameter Min Typ Max Unit VBATT+ Main Battery Input Supply Voltage 2.5 3.6 4.75 V VCOIN RTC Input Supply Voltage 2.0 3.0 3.
SOM Hardware Reference Manual 8 Mechanical Specification SOM Board Dimensions Figure 22 – SOM Module Dimension Shields Dimensions Figure 23 – SOM Module TOP side Shields Version 1.
SOM Hardware Reference Manual Figure 24 – SOM Module BOT side Shield Version 1.
SOM Hardware Reference Manual 9 Special Care when using ERAGON624 SOM Board Development Device Notice This device contains RF/digital hardware and software intended for engineering development, engineering evaluation, or demonstration purposes only and is intended for use in a controlled environment. This device is not being placed on the market, leased or sold for use in a residential environment or for use by the general public as an end user device.
SOM Hardware Reference Manual 10 About eInfochips eInfochips is a partner of choice for Fortune 500 companies for product innovation and hi-tech engineering consulting. Since 1994, eInfochips has provided solutions to key verticals like Aerospace & Defense, Consumer Electronics, Energy & Utilities, Healthcare, Home, Office, and Industrial Automation, Media & Broadcast, Medical Devices, Retail & e-Commerce, Security & Surveillance, Semiconductor, Software/ISV and Storage & Compute.
FCC Warning This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Any Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.
IC Warning This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.