s e ri 0 2 5 1 S D E D C L e S iv r d w r e ith M A R l a M al ic n ch Te a nu
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CONTENTS Selection Guide 1. SED1510 Series 2. SED1520 Series 3. SED152A Series 4. SED1526 Series 5. SED1530 Series 6. SED1540 Series 7. SED1560 Series 8. SED1565 Series 9.
SED1500 Series Selection Guide
■ LCD drivers with RAM for smalland medium-sized displays Ultra-low power consumption and on-chip RAM make this series ideal for compact LCD-based equipment. SED1500 series Part number Supply voltage LCD voltage range (V) range (V) Duty Segment Common Display Microprocessor Frequency RAM (bits) interface (KHz) Package SED1510D0C AI pad chip SED1510D0B Au bump chip SED1510F0C 0.9–6.0 1.8–6.
Part number Supply voltage LCD voltage range (V) range (V) Duty Segment Common Display Microprocessor Frequency RAM (bits) interface (KHz) SED1560D0A Package Al pad chip SED1560DAA Al pad chip SED1560D0B 1/48, 1/49 SED1560DAB 1/64, 1/65 102 Au bump chip 65 Au bump chip SED1560T0B TCP SED1560TQA QTCP SED1561D0A Al pad chip SED1561DAA SED1561D0B 166×65 2.4–6.0 6.0–16.
Part number Supply voltage LCD voltage range (V) range (V) Duty Segment Common Display Microprocessor Frequency RAM (bits) interface (KHz) Package Al pad chip SED1530D0A Al pad chip SED1530DAA SED1530D0B 1/32, 1/33 100 Au bump chip 33 Au bump chip SED1530DAB SED1530TAA TCP SED1531D0A Al pad chip SED1531D0B SED1531T0A 132 2.4–6.0 – 4.5–16.
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SED1520 Series Contents OVERVIEW .......................................................................................................................................................... 2-1 BLOCK DIAGRAM ................................................................................................................................................ 2-2 PACKAGE OUTLINE ...........................................................................................................................................
OVERVIEW FEATURES The SED1520 family of dot matrix LCD drivers are designed for the display of characters and graphics. The drivers generate LCD drive signals derived from bit mapped data stored in an internal RAM. The drivers are available in two configurations The SED1520 family drivers incorporate innovative circuit design strategies to achieve very low power dissipation at a wide range of operating voltages.
SED1520 Series BLOCK DIAGRAM An example of SED1520 AA: LCD drive circuit Display data RAM (2560-bit) I/O buffer Display data latch circuit Line address decoder Line counter Display start line register Common counter FR Display timing generator circuit Column address counter Column address register Command decoder Status 2–2 RES RD,WR EPSON (E,R/W) M/S A0,CS D0~D7 MPU interface Bus holder CL Low-address register Column address decoder VSS VDD SEG0 to SEG60 V1,V2,V3,V4,V5 COM0
SED1520 Series PACKAGE OUTLINE 85 45 90 40 Index 95 25 20 15 5 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 100 10 35 SED1520 Series 55 60 65 75 CS2 CS3 CS4 CS5 CS6 CS7 VDD RES F2 V5 V1 V2 M/S V4 V1 COM0 COM1 COM2 COM3 COM4 70 SEG21 SEG20 S
SED1520 Series PAD Pad Arrangement Chip specifications of gold bump package Chip specifications of AL pad package Chip size: 4.80×7.04×0.400 mm Pad pitch: 100×100 µm 100 Chip size: Bump pitch: Bump height: Bump size: 95 90 4.80×7.04×0.525 mm 199 µm (Min.) 22.5 µm (Typ.) 132×111 µm (±20 µm) for mushroom model 116×92 µm (±4 µm) for vertical model 85 80 1 5 75 Y 15 70 7.04 mm 10 X (0, 0) 65 20 25 30 D1520D AA * 60 55 35 40 45 50 4.
SED1520 Series PAD ARRANGEMENT An example of SED1520DA* pin names is given. The SED1520DAB Pad Center Coordinates Pad No.
SED1520 Series PIN DESCRIPTION (1) Power Pins Name Description VDD Connected to the +5Vdc power. Common to the VCC MPU power pin. VSS 0 Vdc pin connected to the system ground. V1, V2, V3, V4, V5 Multi-level power supplies for LCD driving. The voltage determined for each liquid crystal cell is divided by resistance or it is converted in impedance by the op amp, and supplied.
SED1520 Series Name Description CL Input. Effective for an external clock operation model only. This is a display data latch signal to count up the line counter and common counter at each signal falling and rising edges. If the system has a built-in oscillator, this is used as an output pin of the oscillator amp and an Rf oscillator resistor is connected to it. FR Input/output. This is an I/P pin of LCD AC signals, and connected to the M terminal of common driver.
SED1520 Series BLOCK DESCRIPTION System Bus MPU interface level after reset (see Table 1). When the CS signal is high, the SED1520 series is disconnected from the MPU bus and set to stand by. However, the reset signal is entered regardless of the internal setup status. 1. Selecting an interface type The SED1520 series transfers data via 8-bit bidirectional data buses (D0 to D7).
SED1520 Series WRITE WR MPU Internal timing N N+1 N+2 N+3 SED1520 Series DATA Bus N+1 N hold N+2 N+3 WR READ WR RD MPU DATA N N Address set at N n Dummy read Data read at N n+1 Data read at N + 1 WR RD Internal timing Column N address Bus hold N+1 N n N+2 n+1 n+2 Figure 1 Bus Buffer Delay Busy flag Column Address Counter When the Busy flag is logical 1, the SED1520 series is executing its internal operations.
SED1520 Series Common Timing Generator Circuit Generates common timing signals and FR frame signals from the CL basic clock. The 1/16 or 1/32 duty (for SED1520) or 1/8 or 1/16 duty (for SED1522) can be selected by the Duty Select command. If the 1/32 duty is selected for the SED1520 and 1/16 duty is selected for the SED1522, the 1/32 and 1/16 duties are provided by two chips consisting of the master and slave chips in the common multi-chip mode.
SED1520 Series Oscillator Circuit (SED1520 *0A Only) SED1520 Series A low power-consumption CR oscillator for adjusting the oscillation frequency using Rf oscillation resistor only. This circuit generates a display timing signal. Some of SED1520 and SED1522 series models have a built-in oscillator and others use an external clock. This difference must be checked before use. Connect the Rf oscillation resistor as follows.
SED1520 Series Page address Page 0 Line address Start line (Example) Start 1/16 Response Common output COM 0 COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 COM 10 COM 11 COM 12 COM 13 COM 14 COM 15 COM 16 COM 17 COM 18 COM 19 COM 20 COM 21 COM 22 COM 23 COM 24 COM 25 COM 26 COM 27 COM 28 COM 29 COM 30 COM 31 Figure 2 Display Data RAM Addressing D1,D2 = 0,0 Page 1 Page 2 Page 3 00 H 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F EPSON 2–12
SED1520 Series 1/5 bias, 1/16 duty 1/6 bias, 1/32 duty 15 0 1 2 3 31 0 1 2 3 FR COM0 COM0 COM1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM2 COM8 COM9 COM10 COM11 COM12 SEG0 COM13 COM14 SEG4 SEG3 SEG2 SEG1 SEG0 COM15 SEG1 COM0—SEG0 COM0—SEG1 15 31 V DD V SS V DD V1 V2 V3 V4 V5 SED1520 Series 0 1 2 3 0 1 2 3 V DD V1 V2 V3 V4 V5 V DD V1 V2 V3 V4 V5 V DD V1 V2 V3 V4 V5 V DD V1 V2 V3 V4 V5 V5 V4 V3 V2 V1 V DD -V1 -V2 -V3 -V4 -V5 V5 V4 V3 V2 V1 V DD -V1 -V2 -V3 -V4 -V5 Figure 4 LCD drive wavefor
SED1520 Series COMMANDS Summary Command A0 RD WR D7 D6 Code D5 D4 D3 D2 D1 D0 1 1 1 0/1 Display On/OFF 0 1 0 1 0 1 0 Display start line 0 1 0 1 1 0 Display start address (0 to 31) Set page address 0 1 0 1 0 1 1 Set column (segment) address 0 1 0 0 Read status 0 0 1 Busy Write display data 1 1 0 Write data Read display data 1 0 1 Read data Select ADC Statis drive ON/OFF 0 1 0 1 0 1 0 1 0 1 0 Select duty 0 1 0 1 Read-Modify-Write End
SED1520 Series Command Description Table 3 is the command table. The SED1520 series identifies a data bus using a combination of A0 and R/W (RD or WR) signals. As the MPU translates a command in the internal timing only (independent from the external clock), its speed is very high. The busy check is usually not required. A0 RD R/W WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 1 1 D SED1520 Series Display ON/OFF AEH, AFH This command turns the display on and off.
SED1520 Series Set Column Address This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU continuously, the column address is incremented by 1 each time it is accessed from the set address. Therefore, the MPU can access to data continuously. The column address stops to be incremented at address 80, and the page address is not changed continuously.
SED1520 Series Read Display Data RD R/W WR 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 Read data Reads 8-bits of data from the data I/O latch, updates the contents of the I/O latch with display data from the display data RAM location specified by the contents of the column address and page address registers and then increments the column address register. After loading a new address into the column address register one dummy read is required before valid data is obtained.
SED1520 Series Read-Modify-Write A0 RD R/W WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 0 0 E0H This command defeats column address register auto-increment after data reads. The current conetents of the column address register are saved. This mode remains active until an End command is received. • Operation sequence during cursor display When the End command is entered, the column address is returned to the one used during input of Read-Modify-Write command.
SED1520 Series Reset RD R/W WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 0 E2H This command clears • the display start line register. • and set page address register to 3 page. It does not affect the contents of the display data RAM. When the power supply is turned on, a Reset signal is entered in the RES pin. The Reset command cannot be used instead of this Reset signal.
SED1520 Series SPECIFICATIONS Absolute Maximum Ratings Parameter Symbol Rating Unit Supply voltage (1) VSS –8.0 to +0.3 V Supply voltage (2) V5 –16.5 to +0.3 V Supply voltage (3) V1, V4, V2, V3 V5 to +0.3 V Input voltage VIN VSS–0.3 to +0.3 V Output voltage VO VSS–0.3 to +0.3 V Power dissipation PD 250 mW Operating temperature Topr –40 to +85 deg. C Storage temperature Tstg –65 to +150 deg. C Soldering temperature time at lead Tsol 260, 10 deg. C, sec Notes: 1.
SED1520 Series DC Characteristics (Cont’d) Ta = –20 to 75 deg. C, VDD = 0 V unless stated otherwise Low-level output voltage Input leakage current Output leakage current Symbol VOLT VOLC1 VOLC2 VOLT VOLC1 VOLC2 ILI ILO Condition IOL = 3.0 mA IOL = 2.0 mA IOL = 120 µA VSS = –3 V VSS = –3 V VSS = –3 V IOL = 2 mA IOL = 2 mA IOL = 50 µA –1.0 –3.0 V5 = –5.0 V LCD driver ON resistance RON IDDQ CS = CL = VDD fCL = 2 kHz During display Rf = 1 MΩ V5 = –5.
SED1520 Series Relationship between fOSC, fFR and Rf, and operating bounds on VSS and V5 *9 • Relationship between oscillation frequency, frames and Rf (SED1520F0A), (SED1522F0A) OSC1 Rf OSC2 Ta=25°C V SS =-5V Ta=25°C VSS =-5V [Hz] 200 30 VSS =-5V SED1522 20 Frame fosc [kHz] 40 Same for 1/16 and 1/32 duties VSS =-3V 100 SED1520 10 0 0.5 1.0 1.5 2.0 0 2.5 0.5 [M Ω] Rf 1.0 Rf Figure 5 (a) 1.5 2.0 2.
SED1520 Series AC Characteristics • MPU Bus Read/Write I (80-family MPU) t AW8 t CC SED1520 Series A0,CS t AH8 WR,RD tr t CYC8 tf t DH8 t DS8 D0 to D7 (WRITE) t OH8 t ACC8 D0 to D7 (READ) Ta = –20 to 75 deg. C, VSS = –5.
SED1520 Series • MPU Bus Read/Write II (68-family MPU) t CYC6 E t EW tr tf t AW6 t DS6 R/W t AH6 A0,CS t DH6 D0 to D7 (WRITE) t ACC6 t OH6 D0 to D7 (READ) Ta = –20 to 75 deg. C, VSS = –5 V ±10 unless stated otherwise Parameter System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time Access time Enable Read pulsewidth Write Rise and fall time Symbol tCYC6 tAW6 tAH6 tDS6 tDH6 tOH6 tACC6 Condition CL = 100 pF tEW tr, tf — Rating Min. Max.
SED1520 Series • Display Control Signal Timing tf tr CL t WLCL SED1520 Series t WHCL t DFR FR Input Ta = –20 to 75 deg. C, VSS = –5.0 V ±10% unless stated otherwise Parameter Symbol Low-level pulsewidth High-level pulsewidth Rise time Fall time FR delay time tWLCL tWHCL tr tf tDFR Condition Min. 35 35 — — –2.0 Rating Typ. — — 30 30 0.2 Max. — — 150 150 2.0 Min. 70 70 — — –4.0 Rating Typ. — — 60 60 0.4 Max. — — 300 300 4.0 Unit Signal µs µs ns ns µs FR Unit Signal CL VSS = –2.7 to –4.
SED1520 Series APPLICATION NOTES MPU Interface Configuration 80 Family MPU VCC A1 to A7 IOQR MPU A0 A0 Decoder RD RD WR WR RES VSS RES RESET 2–26 CS SED1520FAA D0 to D7 D0 to D7 GND VDD EPSON V5
SED1520 Series LCD Drive Interface Configuration To LCD SEG To LCD COM To LCD SEG VDD To LCD COM SED1520F0A SED1520F0A Master Slave M/S M/S OSC1 OSC2 FR OSC1 OSC2 FR VSS Rf SED1520FAA–SED1520FAA SED1522FAA–SED1522FAA To LCD SEG To LCD COM To LCD SEG SED1520FAA VDD To LCD COM SED1520FAA Master Slave M/S M/S CL FR CL FR VSS External clock SED1520F0A )–SED1521F0A (See note 1) SED1522F0A To LCD SEG To LCD SEG SED1520F0A SED1521F0A Master Slave To LCD COM VDD M/S OSC1
SED1520 Series SED1520FAA–SED1521FAA To LCD SEG To LCD COM To LCD SEG SED1520FAA SED1521FAA VDD M/S CL FR External clock Notes: 1. The duty cycle of the slave must be the same as that for the master. 2. If a system has two or more slave drivers a CMOS buffer will be required.
SED1520 Series ×8 dots.
SED1520 Series Package Dimensions • Plastic QFP5–100 pin Dimensions: inches (mm) 1.008 ± 0.016 (25.6 ± 0.4) 0.787 ± 0.004 (20 ± 0.1) 80 51 81 Index 31 0.106 ± 0.004 (2.7 ± 0.1) 0.006 ± 0.002 (0.15 ± 0.05) 100 0.772 ± 0.016 (19.6 ± 0.4) 0.551 ± 0.004 (14 ± 0.1) 50 0.026 ± 0.004 (0.65 ± 0.1) 1 30 0.012 ± 0.004 (0.30 ± 0.1) 0~12° 0.110 (2.8) 0.059 ± 0 .012 (1.5 ± 0.3 ) • Plastic QFP15–100 pin 0.630 ± 0.016 (16.0 ± 0.4) 0.551 ± 0.004 (14.0 ± 0.1) 75 51 Index 0.005 ± 0.002 (0.127 ± 0.05) 0.
Punching hole for good product (Mold, marking area) EPSON SED1520 Series Specifications • Base: U-rexS, 75µm • Copper foil: Electrolytic copper foil, 35µm • Sn plating • Product pitch: 81P (28.5mm) • Solder resist positional tolerance: ±0.
